1 /*!
2 \file gd32fxxx_dac.c
3 \brief DAC driver
4
5 \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7
8 /*
9 Copyright (c) 2022, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32a50x_dac.h"
36
37 /* DAC register bit offset */
38 #define OUT1_REG_OFFSET ((uint32_t)0x00000010U)
39 #define DH_12BIT_OFFSET ((uint32_t)0x00000010U)
40 #define DH_8BIT_OFFSET ((uint32_t)0x00000008U)
41
42 /*!
43 \brief deinitialize DAC
44 \param[in] none
45 \param[out] none
46 \retval none
47 */
dac_deinit(void)48 void dac_deinit(void)
49 {
50 rcu_periph_reset_enable(RCU_DACRST);
51 rcu_periph_reset_disable(RCU_DACRST);
52 }
53
54 /*!
55 \brief enable DAC
56 \param[in] none
57 \param[out] none
58 \retval none
59 */
dac_enable(void)60 void dac_enable(void)
61 {
62 DAC_CTL |= DAC_CTL_DEN;
63 }
64
65 /*!
66 \brief disable DAC
67 \param[in] none
68 \param[out] none
69 \retval none
70 */
dac_disable(void)71 void dac_disable(void)
72 {
73 DAC_CTL &= ~DAC_CTL_DEN;
74 }
75
76 /*!
77 \brief enable DAC DMA function
78 \param[in] none
79 \param[out] none
80 \retval none
81 */
dac_dma_enable(void)82 void dac_dma_enable(void)
83 {
84 DAC_CTL |= DAC_CTL_DDMAEN;
85 }
86
87 /*!
88 \brief disable DAC DMA function
89 \param[in] none
90 \param[out] none
91 \retval none
92 */
dac_dma_disable(void)93 void dac_dma_disable(void)
94 {
95 DAC_CTL &= ~DAC_CTL_DDMAEN;
96 }
97
98 /*!
99 \brief enable DAC output buffer
100 \param[in] none
101 \param[out] none
102 \retval none
103 */
dac_output_buffer_enable(void)104 void dac_output_buffer_enable(void)
105 {
106 DAC_CTL &= ~DAC_CTL_DBOFF;
107 }
108
109 /*!
110 \brief disable DAC output buffer
111 \param[in] none
112 \param[out] none
113 \retval none
114 */
dac_output_buffer_disable(void)115 void dac_output_buffer_disable(void)
116 {
117 DAC_CTL |= DAC_CTL_DBOFF;
118 }
119
120 /*!
121 \brief get DAC output value
122 \param[in] none
123 \param[out] none
124 \retval DAC output data: 0~4095
125 */
dac_output_value_get(void)126 uint16_t dac_output_value_get(void)
127 {
128 uint16_t data = 0U;
129 data = (uint16_t)OUT_DO;
130
131 return data;
132 }
133
134 /*!
135 \brief set DAC data holding register value
136 \param[in] dac_align: DAC data alignment mode
137 only one parameter can be selected which is shown as below:
138 \arg DAC_ALIGN_12B_R: 12-bit right-aligned data
139 \arg DAC_ALIGN_12B_L: 12-bit left-aligned data
140 \arg DAC_ALIGN_8B_R: 8-bit right-aligned data
141 \param[in] data: data to be loaded, 0~4095
142 \param[out] none
143 \retval none
144 */
dac_data_set(uint32_t dac_align,uint16_t data)145 void dac_data_set(uint32_t dac_align, uint16_t data)
146 {
147 switch(dac_align){
148 /* 12-bit right-aligned data */
149 case DAC_ALIGN_12B_R:
150 OUT_R12DH = data;
151 break;
152 /* 12-bit left-aligned data */
153 case DAC_ALIGN_12B_L:
154 OUT_L12DH = data;
155 break;
156 /* 8-bit right-aligned data */
157 case DAC_ALIGN_8B_R:
158 OUT_R8DH = data;
159 break;
160 default:
161 break;
162 }
163 }
164
165 /*!
166 \brief enable DAC trigger
167 \param[in] none
168 \param[out] none
169 \retval none
170 */
dac_trigger_enable(void)171 void dac_trigger_enable(void)
172 {
173 DAC_CTL |= DAC_CTL_DTEN;
174 }
175
176 /*!
177 \brief disable DAC trigger
178 \param[in] none
179 \param[out] none
180 \retval none
181 */
dac_trigger_disable(void)182 void dac_trigger_disable(void)
183 {
184 DAC_CTL &= ~DAC_CTL_DTEN;
185 }
186
187 /*!
188 \brief configure DAC trigger source
189 \param[in] triggersource: external triggers of DAC
190 only one parameter can be selected which is shown as below:
191 \arg DAC_TRIGGER_EXTRIG: TRIGSEL trigger
192 \arg DAC_TRIGGER_SOFTWARE: software trigger
193 \param[out] none
194 \retval none
195 */
dac_trigger_source_config(uint32_t triggersource)196 void dac_trigger_source_config(uint32_t triggersource)
197 {
198 /* configure DAC trigger source */
199 DAC_CTL &= (uint32_t)(~DAC_CTL_DTSEL);
200 DAC_CTL |= triggersource;
201 }
202
203 /*!
204 \brief enable DAC software trigger
205 \param[in] none
206 \retval none
207 */
dac_software_trigger_enable(void)208 void dac_software_trigger_enable(void)
209 {
210 DAC_SWT |= DAC_SWT_SWTR;
211 }
212
213 /*!
214 \brief disable DAC software trigger
215 \param[in] none
216 \param[out] none
217 \retval none
218 */
dac_software_trigger_disable(void)219 void dac_software_trigger_disable(void)
220 {
221 DAC_SWT &= ~DAC_SWT_SWTR;
222 }
223
224 /*!
225 \brief configure DAC wave mode
226 \param[in] wave_mode: DAC wave mode
227 only one parameter can be selected which is shown as below:
228 \arg DAC_WAVE_DISABLE: wave mode disable
229 \arg DAC_WAVE_MODE_LFSR: LFSR noise mode
230 \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
231 \param[out] none
232 \retval none
233 */
dac_wave_mode_config(uint32_t wave_mode)234 void dac_wave_mode_config(uint32_t wave_mode)
235 {
236 /* configure DAC wave mode */
237 DAC_CTL &= ~DAC_CTL_DWM;
238 DAC_CTL |= wave_mode;
239 }
240
241 /*!
242 \brief configure DAC wave bit width
243 \param[in] bit_width: DAC noise wave bit width
244 only one parameter can be selected which is shown as below:
245 \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
246 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
247 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
248 \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
249 \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
250 \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
251 \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
252 \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
253 \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
254 \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
255 \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
256 \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
257 \param[out] none
258 \retval none
259 */
dac_wave_bit_width_config(uint32_t bit_width)260 void dac_wave_bit_width_config(uint32_t bit_width)
261 {
262 /* configure DAC wave bit width */
263 DAC_CTL &= ~DAC_CTL_DWBW;
264 DAC_CTL |= bit_width;
265 }
266
267 /*!
268 \brief configure DAC LFSR noise mode
269 \param[in] unmask_bits: LFSR noise unmask bits
270 only one parameter can be selected which is shown as below:
271 \arg DAC_LFSR_BIT0: unmask the LFSR bit0
272 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
273 \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
274 \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
275 \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
276 \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
277 \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
278 \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
279 \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
280 \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
281 \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
282 \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
283 \param[out] none
284 \retval none
285 */
dac_lfsr_noise_config(uint32_t unmask_bits)286 void dac_lfsr_noise_config(uint32_t unmask_bits)
287 {
288 /* configure DAC LFSR noise mode */
289 DAC_CTL &= ~DAC_CTL_DWBW;
290 DAC_CTL |= unmask_bits;
291 }
292
293 /*!
294 \brief configure DAC triangle noise mode
295 \param[in] amplitude: the amplitude of the triangle
296 only one parameter can be selected which is shown as below:
297 \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
298 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
299 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
300 \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
301 \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
302 \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
303 \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
304 \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
305 \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
306 \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
307 \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
308 \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
309 \param[out] none
310 \retval none
311 */
dac_triangle_noise_config(uint32_t amplitude)312 void dac_triangle_noise_config(uint32_t amplitude)
313 {
314 /* configure DAC triangle noise mode */
315 DAC_CTL &= ~DAC_CTL_DWBW;
316 DAC_CTL |= amplitude;
317 }
318
319 /*!
320 \brief get DAC flag
321 \param[in] dac_flag: DAC flag
322 only one parameter can be selected which is shown as below:
323 \arg DAC_FLAG_DDUDR: DMA underrun flag
324 \param[out] none
325 \retval FlagStatus: SET or RESET
326 */
dac_flag_get(uint32_t flag)327 FlagStatus dac_flag_get(uint32_t flag)
328 {
329 /* check DAC flag */
330 if(DAC_FLAG_DDUDR == flag){
331 if(0U != (DAC_STAT & DAC_STAT_DDUDR)){
332 return SET;
333 }
334 }
335 return RESET;
336 }
337
338 /*!
339 \brief clear DAC flag
340 \param[in] flag: DAC flag
341 only one parameter can be selected which is shown as below:
342 \arg DAC_FLAG_DDUDR: DMA underrun flag
343 \param[out] none
344 \retval none
345 */
dac_flag_clear(uint32_t flag)346 void dac_flag_clear(uint32_t flag)
347 {
348 /* clear DAC_OUT0 flag */
349 if(DAC_FLAG_DDUDR == flag){
350 DAC_STAT |= (uint32_t)DAC_STAT_DDUDR;
351 }
352 }
353
354 /*!
355 \brief enable DAC interrupt
356 \param[in] interrupt: the DAC interrupt
357 only one parameter can be selected which is shown as below:
358 \arg DAC_INT_DDUDRIE: DMA underrun interrupt enable
359 \param[out] none
360 \retval none
361 */
dac_interrupt_enable(uint32_t interrupt)362 void dac_interrupt_enable(uint32_t interrupt)
363 {
364 /* enable DAC interrupt */
365 if(DAC_INT_DDUDRIE == interrupt){
366 DAC_CTL |= (uint32_t)DAC_CTL_DDUDRIE;
367 }
368 }
369
370 /*!
371 \brief disable DAC interrupt
372 \param[in] interrupt: the DAC interrupt
373 only one parameter can be selected which is shown as below:
374 \arg DAC_INT_DDUDRIE: DMA underrun interrupt disable
375 \param[out] none
376 \retval none
377 */
dac_interrupt_disable(uint32_t interrupt)378 void dac_interrupt_disable(uint32_t interrupt)
379 {
380 /* disable DAC interrupt */
381 if(DAC_INT_DDUDRIE == interrupt){
382 DAC_CTL &= (uint32_t)(~DAC_CTL_DDUDRIE);
383 }
384 }
385
386 /*!
387 \brief get DAC interrupt flag
388 \param[in] int_flag: DAC interrupt flag
389 only one parameter can be selected which is shown as below:
390 \arg DAC_INT_FLAG_DDUDR: DMA underrun interrupt flag
391 \param[out] none
392 \retval the state of DAC interrupt flag(SET or RESET)
393 */
dac_interrupt_flag_get(uint32_t int_flag)394 FlagStatus dac_interrupt_flag_get(uint32_t int_flag)
395 {
396 uint32_t reg1 = 0U, reg2 = 0U;
397
398 /* check DAC interrupt flag */
399 if(DAC_INT_FLAG_DDUDR == int_flag){
400 reg1 = DAC_STAT & DAC_STAT_DDUDR;
401 reg2 = DAC_CTL & DAC_CTL_DDUDRIE;
402 }
403
404 /*get DAC interrupt flag status */
405 if((0U != reg1) && (0U != reg2)){
406 return SET;
407 }else{
408 return RESET;
409 }
410 }
411
412 /*!
413 \brief clear DAC interrupt flag
414 \param[in] int_flag: DAC interrupt flag
415 only one parameter can be selected which is shown as below:
416 \arg DAC_INT_FLAG_DDUDR: DMA underrun interrupt flag
417 \param[out] none
418 \retval none
419 */
dac_interrupt_flag_clear(uint32_t int_flag)420 void dac_interrupt_flag_clear(uint32_t int_flag)
421 {
422 /* clear DAC interrupt flag */
423 if(DAC_INT_FLAG_DDUDR == int_flag){
424 DAC_STAT |= (uint32_t)DAC_STAT_DDUDR;
425 }
426 }
427
