1 /*! 2 \file gd32a50x_dbg.h 3 \brief definitions for the DBG 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_DBG_H 36 #define GD32A50X_DBG_H 37 38 #include "gd32a50x.h" 39 40 /* DBG definitions */ 41 #define DBG DBG_BASE /*!< DBG base address */ 42 43 /* registers definitions */ 44 #define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ 45 #define DBG_CTL REG32(DBG + 0x00000004U) /*!< DBG control register */ 46 47 /* bits definitions */ 48 /* DBG_ID */ 49 #define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code */ 50 51 /* DBG_CTL */ 52 #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ 53 #define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ 54 #define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ 55 #define DBG_CTL_FWDGT_HOLD BIT(8) /*!< hold FWDGT counter when core is halted */ 56 #define DBG_CTL_WWDGT_HOLD BIT(9) /*!< hold WWDGT counter when core is halted */ 57 #define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ 58 #define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ 59 #define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus timeout when core is halted */ 60 #define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus timeout when core is halted */ 61 #define DBG_CTL_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */ 62 #define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ 63 #define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ 64 #define DBG_CTL_MFCOM_HOLD BIT(21) /*!< hold MFCOM counter when core is halted */ 65 #define DBG_CTL_CAN0_HOLD BIT(22) /*!< hold CAN0 counter when core is halted */ 66 #define DBG_CTL_CAN1_HOLD BIT(23) /*!< hold CAN1 counter when core is halted */ 67 #define DBG_CTL_TIMER20_HOLD BIT(30) /*!< hold TIMER20 counter when core is halted */ 68 #define DBG_CTL_TIMER19_HOLD BIT(31) /*!< hold TIMER19 counter when core is halted */ 69 70 71 /* constants definitions */ 72 #define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ 73 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ 74 #define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ 75 76 /* define the peripheral debug hold bit position and its register index offset */ 77 #define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) 78 #define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) 79 #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 80 81 /* register index */ 82 #define DBG_IDX_CTL ((uint32_t)0x00000004U) 83 84 typedef enum 85 { 86 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 8U), /*!< hold FWDGT counter when core is halted */ 87 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 9U), /*!< hold WWDGT counter when core is halted */ 88 DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 10U), /*!< hold TIMER0 counter when core is halted */ 89 DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 11U), /*!< hold TIMER1 counter when core is halted */ 90 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 15U), /*!< hold I2C0 smbus timeout when core is halted */ 91 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 16U), /*!< hold I2C1 smbus timeout when core is halted */ 92 DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 17U), /*!< hold TIMER7 counter when core is halted */ 93 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 19U), /*!< hold TIMER5 counter when core is halted */ 94 DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 20U), /*!< hold TIMER6 counter when core is halted */ 95 DBG_MFCOM_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 21U), /*!< hold MFCOM counter when core is halted */ 96 DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 22U), /*!< hold CAN0 counter when core is halted */ 97 DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 23U), /*!< hold CAN1 counter when core is halted */ 98 DBG_TIMER20_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 30U), /*!< hold TIMER20 counter when core is halted */ 99 DBG_TIMER19_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 31U), /*!< hold TIMER19 counter when core is halted */ 100 }dbg_periph_enum; 101 102 103 /* function declarations */ 104 /* deinitialize the DBG */ 105 void dbg_deinit(void); 106 /* read DBG_ID code register */ 107 uint32_t dbg_id_get(void); 108 109 /* enable low power behavior when the MCU is in debug mode */ 110 void dbg_low_power_enable(uint32_t dbg_low_power); 111 /* disable low power behavior when the MCU is in debug mode */ 112 void dbg_low_power_disable(uint32_t dbg_low_power); 113 114 /* enable peripheral behavior when the MCU is in debug mode */ 115 void dbg_periph_enable(dbg_periph_enum dbg_periph); 116 /* disable peripheral behavior when the MCU is in debug mode */ 117 void dbg_periph_disable(dbg_periph_enum dbg_periph); 118 119 120 #endif /* GD32A50X_DBG_H */ 121
