1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache 2.0 5 */ 6 7 #include "gd32vf103xx-afio.h" 8 9 /* ADC01_IN0 */ 10 #define ADC01_IN0_PA0 \ 11 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 12 13 /* ADC01_IN1 */ 14 #define ADC01_IN1_PA1 \ 15 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 16 17 /* ADC01_IN10 */ 18 #define ADC01_IN10_PC0 \ 19 GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) 20 21 /* ADC01_IN11 */ 22 #define ADC01_IN11_PC1 \ 23 GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) 24 25 /* ADC01_IN12 */ 26 #define ADC01_IN12_PC2 \ 27 GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) 28 29 /* ADC01_IN13 */ 30 #define ADC01_IN13_PC3 \ 31 GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) 32 33 /* ADC01_IN14 */ 34 #define ADC01_IN14_PC4 \ 35 GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) 36 37 /* ADC01_IN15 */ 38 #define ADC01_IN15_PC5 \ 39 GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) 40 41 /* ADC01_IN2 */ 42 #define ADC01_IN2_PA2 \ 43 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 44 45 /* ADC01_IN3 */ 46 #define ADC01_IN3_PA3 \ 47 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 48 49 /* ADC01_IN4 */ 50 #define ADC01_IN4_PA4 \ 51 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 52 53 /* ADC01_IN5 */ 54 #define ADC01_IN5_PA5 \ 55 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 56 57 /* ADC01_IN6 */ 58 #define ADC01_IN6_PA6 \ 59 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 60 61 /* ADC01_IN7 */ 62 #define ADC01_IN7_PA7 \ 63 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 64 65 /* ADC01_IN8 */ 66 #define ADC01_IN8_PB0 \ 67 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 68 69 /* ADC01_IN9 */ 70 #define ADC01_IN9_PB1 \ 71 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 72 73 /* ANALOG */ 74 #define ANALOG_PA0 \ 75 GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) 76 #define ANALOG_PA1 \ 77 GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) 78 #define ANALOG_PA2 \ 79 GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) 80 #define ANALOG_PA3 \ 81 GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) 82 #define ANALOG_PA4 \ 83 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 84 #define ANALOG_PA5 \ 85 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 86 #define ANALOG_PA6 \ 87 GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) 88 #define ANALOG_PA7 \ 89 GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) 90 #define ANALOG_PA8 \ 91 GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) 92 #define ANALOG_PA9 \ 93 GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) 94 #define ANALOG_PA10 \ 95 GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) 96 #define ANALOG_PA11 \ 97 GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) 98 #define ANALOG_PA12 \ 99 GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) 100 #define ANALOG_PA13 \ 101 GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) 102 #define ANALOG_PA14 \ 103 GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) 104 #define ANALOG_PA15 \ 105 GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) 106 #define ANALOG_PB0 \ 107 GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) 108 #define ANALOG_PB1 \ 109 GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) 110 #define ANALOG_PB2 \ 111 GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) 112 #define ANALOG_PB3 \ 113 GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) 114 #define ANALOG_PB4 \ 115 GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) 116 #define ANALOG_PB5 \ 117 GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) 118 #define ANALOG_PB6 \ 119 GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) 120 #define ANALOG_PB7 \ 121 GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) 122 #define ANALOG_PB8 \ 123 GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) 124 #define ANALOG_PB9 \ 125 GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) 126 #define ANALOG_PB10 \ 127 GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) 128 #define ANALOG_PB11 \ 129 GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) 130 #define ANALOG_PB12 \ 131 GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) 132 #define ANALOG_PB13 \ 133 GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) 134 #define ANALOG_PB14 \ 135 GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) 136 #define ANALOG_PB15 \ 137 GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) 138 #define ANALOG_PC0 \ 139 GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) 140 #define ANALOG_PC1 \ 141 GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) 142 #define ANALOG_PC2 \ 143 GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) 144 #define ANALOG_PC3 \ 145 GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) 146 #define ANALOG_PC4 \ 147 GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) 148 #define ANALOG_PC5 \ 149 GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) 150 #define ANALOG_PC6 \ 151 GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP) 152 #define ANALOG_PC7 \ 153 GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP) 154 #define ANALOG_PC8 \ 155 GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP) 156 #define ANALOG_PC9 \ 157 GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP) 158 #define ANALOG_PC10 \ 159 GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP) 160 #define ANALOG_PC11 \ 161 GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP) 162 #define ANALOG_PC12 \ 163 GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP) 164 #define ANALOG_PC13 \ 165 GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) 166 #define ANALOG_PC14 \ 167 GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) 168 #define ANALOG_PC15 \ 169 GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) 170 #define ANALOG_PD0 \ 171 GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) 172 #define ANALOG_PD1 \ 173 GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) 174 #define ANALOG_PD2 \ 175 GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP) 176 177 /* CAN0_RX */ 178 #define CAN0_RX_PA11_NORMP \ 179 GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP) 180 #define CAN0_RX_PB8_PRMP \ 181 GD32_PINMUX_AFIO('B', 8, GPIO_IN, CAN0_PRMP) 182 #define CAN0_RX_PD0_FRMP \ 183 GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP) 184 185 /* CAN0_TX */ 186 #define CAN0_TX_PA12_NORMP \ 187 GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP) 188 #define CAN0_TX_PB9_PRMP \ 189 GD32_PINMUX_AFIO('B', 9, ALTERNATE, CAN0_PRMP) 190 #define CAN0_TX_PD1_FRMP \ 191 GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP) 192 193 /* CAN1_RX */ 194 #define CAN1_RX_PB12_NORMP \ 195 GD32_PINMUX_AFIO('B', 12, GPIO_IN, CAN1_NORMP) 196 #define CAN1_RX_PB5_RMP \ 197 GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP) 198 199 /* CAN1_TX */ 200 #define CAN1_TX_PB13_NORMP \ 201 GD32_PINMUX_AFIO('B', 13, ALTERNATE, CAN1_NORMP) 202 #define CAN1_TX_PB6_RMP \ 203 GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP) 204 205 /* CK_OUT0 */ 206 #define CK_OUT0_PA8 \ 207 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 208 209 /* DAC_OUT0 */ 210 #define DAC_OUT0_PA4 \ 211 GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) 212 213 /* DAC_OUT1 */ 214 #define DAC_OUT1_PA5 \ 215 GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) 216 217 /* I2C0_SCL */ 218 #define I2C0_SCL_PB6_NORMP \ 219 GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) 220 #define I2C0_SCL_PB8_RMP \ 221 GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) 222 223 /* I2C0_SDA */ 224 #define I2C0_SDA_PB7_NORMP \ 225 GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) 226 #define I2C0_SDA_PB9_RMP \ 227 GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) 228 229 /* I2C0_SMBA */ 230 #define I2C0_SMBA_PB5 \ 231 GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) 232 233 /* I2C1_SCL */ 234 #define I2C1_SCL_PB10 \ 235 GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) 236 237 /* I2C1_SDA */ 238 #define I2C1_SDA_PB11 \ 239 GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) 240 241 /* I2C1_SMBA */ 242 #define I2C1_SMBA_PB12 \ 243 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 244 245 /* I2S1_CK */ 246 #define I2S1_CK_PB13_INP \ 247 GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) 248 #define I2S1_CK_PB13_OUT \ 249 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 250 251 /* I2S1_MCK */ 252 #define I2S1_MCK_PC6 \ 253 GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) 254 255 /* I2S1_SD */ 256 #define I2S1_SD_PB15_INP \ 257 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 258 #define I2S1_SD_PB15_OUT \ 259 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 260 261 /* I2S1_WS */ 262 #define I2S1_WS_PB12_INP \ 263 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 264 #define I2S1_WS_PB12_OUT \ 265 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 266 267 /* I2S2_CK */ 268 #define I2S2_CK_PB3_INP_NORMP \ 269 GD32_PINMUX_AFIO('B', 3, GPIO_IN, I2S2_NORMP) 270 #define I2S2_CK_PB3_OUT_NORMP \ 271 GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) 272 #define I2S2_CK_PC10_INP_RMP \ 273 GD32_PINMUX_AFIO('C', 10, GPIO_IN, I2S2_RMP) 274 #define I2S2_CK_PC10_OUT_RMP \ 275 GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP) 276 277 /* I2S2_MCK */ 278 #define I2S2_MCK_PC7 \ 279 GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) 280 281 /* I2S2_SD */ 282 #define I2S2_SD_PB5_INP_NORMP \ 283 GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) 284 #define I2S2_SD_PB5_OUT_NORMP \ 285 GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) 286 #define I2S2_SD_PC12_INP_RMP \ 287 GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP) 288 #define I2S2_SD_PC12_OUT_RMP \ 289 GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP) 290 291 /* I2S2_WS */ 292 #define I2S2_WS_PA15_INP_NORMP \ 293 GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) 294 #define I2S2_WS_PA15_OUT_NORMP \ 295 GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) 296 #define I2S2_WS_PA4_INP_RMP \ 297 GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) 298 #define I2S2_WS_PA4_OUT_RMP \ 299 GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) 300 301 /* SPI0_MISO */ 302 #define SPI0_MISO_PA6_INP_NORMP \ 303 GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) 304 #define SPI0_MISO_PA6_OUT_NORMP \ 305 GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) 306 #define SPI0_MISO_PB4_INP_RMP \ 307 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) 308 #define SPI0_MISO_PB4_OUT_RMP \ 309 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) 310 311 /* SPI0_MOSI */ 312 #define SPI0_MOSI_PA7_INP_NORMP \ 313 GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) 314 #define SPI0_MOSI_PA7_OUT_NORMP \ 315 GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) 316 #define SPI0_MOSI_PB5_INP_RMP \ 317 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) 318 #define SPI0_MOSI_PB5_OUT_RMP \ 319 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) 320 321 /* SPI0_NSS */ 322 #define SPI0_NSS_PA4_INP_NORMP \ 323 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) 324 #define SPI0_NSS_PA4_OUT_NORMP \ 325 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) 326 #define SPI0_NSS_PA15_INP_RMP \ 327 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) 328 #define SPI0_NSS_PA15_OUT_RMP \ 329 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) 330 331 /* SPI0_SCK */ 332 #define SPI0_SCK_PA5_INP_NORMP \ 333 GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) 334 #define SPI0_SCK_PA5_OUT_NORMP \ 335 GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) 336 #define SPI0_SCK_PB3_INP_RMP \ 337 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) 338 #define SPI0_SCK_PB3_OUT_RMP \ 339 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) 340 341 /* SPI1_MISO */ 342 #define SPI1_MISO_PB14_INP \ 343 GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) 344 #define SPI1_MISO_PB14_OUT \ 345 GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) 346 347 /* SPI1_MOSI */ 348 #define SPI1_MOSI_PB15_INP \ 349 GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) 350 #define SPI1_MOSI_PB15_OUT \ 351 GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) 352 353 /* SPI1_NSS */ 354 #define SPI1_NSS_PB12_INP \ 355 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 356 #define SPI1_NSS_PB12_OUT \ 357 GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) 358 359 /* SPI1_SCK */ 360 #define SPI1_SCK_PB13_INP \ 361 GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) 362 #define SPI1_SCK_PB13_OUT \ 363 GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) 364 365 /* SPI2_MISO */ 366 #define SPI2_MISO_PB4_INP_NORMP \ 367 GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) 368 #define SPI2_MISO_PB4_OUT_NORMP \ 369 GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) 370 #define SPI2_MISO_PC11_INP_RMP \ 371 GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP) 372 #define SPI2_MISO_PC11_OUT_RMP \ 373 GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP) 374 375 /* SPI2_MOSI */ 376 #define SPI2_MOSI_PB5_INP_NORMP \ 377 GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) 378 #define SPI2_MOSI_PB5_OUT_NORMP \ 379 GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) 380 #define SPI2_MOSI_PC12_INP_RMP \ 381 GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP) 382 #define SPI2_MOSI_PC12_OUT_RMP \ 383 GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP) 384 385 /* SPI2_NSS */ 386 #define SPI2_NSS_PA15_INP_NORMP \ 387 GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) 388 #define SPI2_NSS_PA15_OUT_NORMP \ 389 GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) 390 #define SPI2_NSS_PA4_INP_RMP \ 391 GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) 392 #define SPI2_NSS_PA4_OUT_RMP \ 393 GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) 394 395 /* SPI2_SCK */ 396 #define SPI2_SCK_PB3_INP_NORMP \ 397 GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) 398 #define SPI2_SCK_PB3_OUT_NORMP \ 399 GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) 400 #define SPI2_SCK_PC10_INP_RMP \ 401 GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP) 402 #define SPI2_SCK_PC10_OUT_RMP \ 403 GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP) 404 405 /* TAMPER */ 406 #define TAMPER_PC13 \ 407 GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) 408 409 /* TIMER0_BRKIN */ 410 #define TIMER0_BRKIN_PB12 \ 411 GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) 412 413 /* TIMER0_CH0 */ 414 #define TIMER0_CH0_PA8_INP_NORMP \ 415 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) 416 #define TIMER0_CH0_PA8_OUT_NORMP \ 417 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) 418 #define TIMER0_CH0_PA8_INP_PRMP \ 419 GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) 420 #define TIMER0_CH0_PA8_OUT_PRMP \ 421 GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) 422 423 /* TIMER0_CH0_ON */ 424 #define TIMER0_CH0_ON_PB13_NORMP \ 425 GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) 426 #define TIMER0_CH0_ON_PA7_PRMP \ 427 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) 428 429 /* TIMER0_CH1 */ 430 #define TIMER0_CH1_PA9_INP_NORMP \ 431 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) 432 #define TIMER0_CH1_PA9_OUT_NORMP \ 433 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) 434 #define TIMER0_CH1_PA9_INP_PRMP \ 435 GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) 436 #define TIMER0_CH1_PA9_OUT_PRMP \ 437 GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) 438 439 /* TIMER0_CH1_ON */ 440 #define TIMER0_CH1_ON_PB14_NORMP \ 441 GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) 442 #define TIMER0_CH1_ON_PB0_PRMP \ 443 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) 444 445 /* TIMER0_CH2 */ 446 #define TIMER0_CH2_PA10_INP_NORMP \ 447 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) 448 #define TIMER0_CH2_PA10_OUT_NORMP \ 449 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) 450 #define TIMER0_CH2_PA10_INP_PRMP \ 451 GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) 452 #define TIMER0_CH2_PA10_OUT_PRMP \ 453 GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) 454 455 /* TIMER0_CH2_ON */ 456 #define TIMER0_CH2_ON_PB15_NORMP \ 457 GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) 458 #define TIMER0_CH2_ON_PB1_PRMP \ 459 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) 460 461 /* TIMER0_CH3 */ 462 #define TIMER0_CH3_PA11_INP_NORMP \ 463 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) 464 #define TIMER0_CH3_PA11_OUT_NORMP \ 465 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) 466 #define TIMER0_CH3_PA11_INP_PRMP \ 467 GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) 468 #define TIMER0_CH3_PA11_OUT_PRMP \ 469 GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) 470 471 /* TIMER0_ETI */ 472 #define TIMER0_ETI_PA12_NORMP \ 473 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) 474 #define TIMER0_ETI_PA12_PRMP \ 475 GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) 476 477 /* TIMER1_CH0 */ 478 #define TIMER1_CH0_PA0_INP_NORMP \ 479 GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_NORMP) 480 #define TIMER1_CH0_PA0_OUT_NORMP \ 481 GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_NORMP) 482 #define TIMER1_CH0_PA0_INP_PRMP2 \ 483 GD32_PINMUX_AFIO('A', 0, GPIO_IN, TIMER1_PRMP2) 484 #define TIMER1_CH0_PA0_OUT_PRMP2 \ 485 GD32_PINMUX_AFIO('A', 0, ALTERNATE, TIMER1_PRMP2) 486 #define TIMER1_CH0_PA15_INP_PRMP1 \ 487 GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_PRMP1) 488 #define TIMER1_CH0_PA15_OUT_PRMP1 \ 489 GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_PRMP1) 490 #define TIMER1_CH0_PA15_INP_FRMP \ 491 GD32_PINMUX_AFIO('A', 15, GPIO_IN, TIMER1_FRMP) 492 #define TIMER1_CH0_PA15_OUT_FRMP \ 493 GD32_PINMUX_AFIO('A', 15, ALTERNATE, TIMER1_FRMP) 494 495 /* TIMER1_CH1 */ 496 #define TIMER1_CH1_PA1_INP_NORMP \ 497 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) 498 #define TIMER1_CH1_PA1_OUT_NORMP \ 499 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) 500 #define TIMER1_CH1_PA1_INP_PRMP2 \ 501 GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) 502 #define TIMER1_CH1_PA1_OUT_PRMP2 \ 503 GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) 504 #define TIMER1_CH1_PB3_INP_PRMP1 \ 505 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) 506 #define TIMER1_CH1_PB3_OUT_PRMP1 \ 507 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) 508 #define TIMER1_CH1_PB3_INP_FRMP \ 509 GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) 510 #define TIMER1_CH1_PB3_OUT_FRMP \ 511 GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) 512 513 /* TIMER1_CH2 */ 514 #define TIMER1_CH2_PA2_INP_NORMP \ 515 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) 516 #define TIMER1_CH2_PA2_OUT_NORMP \ 517 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) 518 #define TIMER1_CH2_PA2_INP_PRMP1 \ 519 GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) 520 #define TIMER1_CH2_PA2_OUT_PRMP1 \ 521 GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) 522 #define TIMER1_CH2_PB10_INP_PRMP2 \ 523 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) 524 #define TIMER1_CH2_PB10_OUT_PRMP2 \ 525 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) 526 #define TIMER1_CH2_PB10_INP_FRMP \ 527 GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) 528 #define TIMER1_CH2_PB10_OUT_FRMP \ 529 GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) 530 531 /* TIMER1_CH3 */ 532 #define TIMER1_CH3_PA3_INP_NORMP \ 533 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) 534 #define TIMER1_CH3_PA3_OUT_NORMP \ 535 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) 536 #define TIMER1_CH3_PA3_INP_PRMP1 \ 537 GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) 538 #define TIMER1_CH3_PA3_OUT_PRMP1 \ 539 GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) 540 #define TIMER1_CH3_PB11_INP_PRMP2 \ 541 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) 542 #define TIMER1_CH3_PB11_OUT_PRMP2 \ 543 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) 544 #define TIMER1_CH3_PB11_INP_FRMP \ 545 GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) 546 #define TIMER1_CH3_PB11_OUT_FRMP \ 547 GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) 548 549 /* TIMER2_CH0 */ 550 #define TIMER2_CH0_PA6_INP_NORMP \ 551 GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) 552 #define TIMER2_CH0_PA6_OUT_NORMP \ 553 GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) 554 #define TIMER2_CH0_PB4_INP_PRMP \ 555 GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) 556 #define TIMER2_CH0_PB4_OUT_PRMP \ 557 GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) 558 #define TIMER2_CH0_PC6_INP_FRMP \ 559 GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP) 560 #define TIMER2_CH0_PC6_OUT_FRMP \ 561 GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP) 562 563 /* TIMER2_CH1 */ 564 #define TIMER2_CH1_PA7_INP_NORMP \ 565 GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) 566 #define TIMER2_CH1_PA7_OUT_NORMP \ 567 GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) 568 #define TIMER2_CH1_PB5_INP_PRMP \ 569 GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) 570 #define TIMER2_CH1_PB5_OUT_PRMP \ 571 GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) 572 #define TIMER2_CH1_PC7_INP_FRMP \ 573 GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP) 574 #define TIMER2_CH1_PC7_OUT_FRMP \ 575 GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP) 576 577 /* TIMER2_CH2 */ 578 #define TIMER2_CH2_PB0_INP_NORMP \ 579 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) 580 #define TIMER2_CH2_PB0_OUT_NORMP \ 581 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) 582 #define TIMER2_CH2_PB0_INP_PRMP \ 583 GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) 584 #define TIMER2_CH2_PB0_OUT_PRMP \ 585 GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) 586 #define TIMER2_CH2_PC8_INP_FRMP \ 587 GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP) 588 #define TIMER2_CH2_PC8_OUT_FRMP \ 589 GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP) 590 591 /* TIMER2_CH3 */ 592 #define TIMER2_CH3_PB1_INP_NORMP \ 593 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) 594 #define TIMER2_CH3_PB1_OUT_NORMP \ 595 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) 596 #define TIMER2_CH3_PB1_INP_PRMP \ 597 GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) 598 #define TIMER2_CH3_PB1_OUT_PRMP \ 599 GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) 600 #define TIMER2_CH3_PC9_INP_FRMP \ 601 GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP) 602 #define TIMER2_CH3_PC9_OUT_FRMP \ 603 GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP) 604 605 /* TIMER2_ETI */ 606 #define TIMER2_ETI_PD2 \ 607 GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) 608 609 /* TIMER3_CH0 */ 610 #define TIMER3_CH0_PB6_INP_NORMP \ 611 GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) 612 #define TIMER3_CH0_PB6_OUT_NORMP \ 613 GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) 614 615 /* TIMER3_CH1 */ 616 #define TIMER3_CH1_PB7_INP_NORMP \ 617 GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) 618 #define TIMER3_CH1_PB7_OUT_NORMP \ 619 GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) 620 621 /* TIMER3_CH2 */ 622 #define TIMER3_CH2_PB8_INP_NORMP \ 623 GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) 624 #define TIMER3_CH2_PB8_OUT_NORMP \ 625 GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) 626 627 /* TIMER3_CH3 */ 628 #define TIMER3_CH3_PB9_INP_NORMP \ 629 GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) 630 #define TIMER3_CH3_PB9_OUT_NORMP \ 631 GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) 632 633 /* TIMER4_CH1 */ 634 #define TIMER4_CH1_PA1_INP \ 635 GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) 636 #define TIMER4_CH1_PA1_OUT \ 637 GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) 638 639 /* TIMER4_CH2 */ 640 #define TIMER4_CH2_PA2_INP \ 641 GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) 642 #define TIMER4_CH2_PA2_OUT \ 643 GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) 644 645 /* TIMER4_CH3 */ 646 #define TIMER4_CH3_PA3_INP \ 647 GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) 648 #define TIMER4_CH3_PA3_OUT \ 649 GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) 650 651 /* UART3_RX */ 652 #define UART3_RX_PC11 \ 653 GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP) 654 655 /* UART3_TX */ 656 #define UART3_TX_PC10 \ 657 GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP) 658 659 /* UART4_RX */ 660 #define UART4_RX_PD2 \ 661 GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) 662 663 /* UART4_TX */ 664 #define UART4_TX_PC12 \ 665 GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP) 666 667 /* USART0_CK */ 668 #define USART0_CK_PA8 \ 669 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 670 671 /* USART0_CTS */ 672 #define USART0_CTS_PA11 \ 673 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 674 675 /* USART0_RTS */ 676 #define USART0_RTS_PA12 \ 677 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 678 679 /* USART0_RX */ 680 #define USART0_RX_PA10_NORMP \ 681 GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) 682 #define USART0_RX_PB7_RMP \ 683 GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) 684 685 /* USART0_TX */ 686 #define USART0_TX_PA9_NORMP \ 687 GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) 688 #define USART0_TX_PB6_RMP \ 689 GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) 690 691 /* USART1_CK */ 692 #define USART1_CK_PA4_NORMP \ 693 GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) 694 695 /* USART1_CTS */ 696 #define USART1_CTS_PA0_NORMP \ 697 GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) 698 699 /* USART1_RTS */ 700 #define USART1_RTS_PA1_NORMP \ 701 GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) 702 703 /* USART1_RX */ 704 #define USART1_RX_PA3_NORMP \ 705 GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) 706 707 /* USART1_TX */ 708 #define USART1_TX_PA2_NORMP \ 709 GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) 710 711 /* USART2_CK */ 712 #define USART2_CK_PB12_NORMP \ 713 GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) 714 #define USART2_CK_PC12_PRMP \ 715 GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP) 716 717 /* USART2_CTS */ 718 #define USART2_CTS_PB13_NORMP \ 719 GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) 720 #define USART2_CTS_PB13_PRMP \ 721 GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) 722 723 /* USART2_RTS */ 724 #define USART2_RTS_PB14_NORMP \ 725 GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) 726 #define USART2_RTS_PB14_PRMP \ 727 GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) 728 729 /* USART2_RX */ 730 #define USART2_RX_PB11_NORMP \ 731 GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) 732 #define USART2_RX_PC11_PRMP \ 733 GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP) 734 735 /* USART2_TX */ 736 #define USART2_TX_PB10_NORMP \ 737 GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) 738 #define USART2_TX_PC10_PRMP \ 739 GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP) 740 741 /* USBFS_DM */ 742 #define USBFS_DM_PA11_INP \ 743 GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) 744 #define USBFS_DM_PA11_OUT \ 745 GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) 746 747 /* USBFS_DP */ 748 #define USBFS_DP_PA12_INP \ 749 GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) 750 #define USBFS_DP_PA12_OUT \ 751 GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) 752 753 /* USBFS_ID */ 754 #define USBFS_ID_PA10_INP \ 755 GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) 756 #define USBFS_ID_PA10_OUT \ 757 GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) 758 759 /* USBFS_SOF */ 760 #define USBFS_SOF_PA8 \ 761 GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) 762 763 /* USBFS_VBUS */ 764 #define USBFS_VBUS_PA9 \ 765 GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) 766 767 /* WKUP */ 768 #define WKUP_PA0 \ 769 GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) 770
