1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32-af.h"
8 
9 /* ADC0_IN0 */
10 #define ADC0_IN0_PC11 \
11 	GD32_PINMUX_AF('C', 11, ANALOG)
12 
13 /* ADC0_IN1 */
14 #define ADC0_IN1_PC10 \
15 	GD32_PINMUX_AF('C', 10, ANALOG)
16 
17 /* ADC0_IN10 */
18 #define ADC0_IN10_PA4 \
19 	GD32_PINMUX_AF('A', 4, ANALOG)
20 
21 /* ADC0_IN11 */
22 #define ADC0_IN11_PA3 \
23 	GD32_PINMUX_AF('A', 3, ANALOG)
24 
25 /* ADC0_IN12 */
26 #define ADC0_IN12_PE12 \
27 	GD32_PINMUX_AF('E', 12, ANALOG)
28 
29 /* ADC0_IN13 */
30 #define ADC0_IN13_PE11 \
31 	GD32_PINMUX_AF('E', 11, ANALOG)
32 
33 /* ADC0_IN14 */
34 #define ADC0_IN14_PE10 \
35 	GD32_PINMUX_AF('E', 10, ANALOG)
36 
37 /* ADC0_IN15 */
38 #define ADC0_IN15_PE9 \
39 	GD32_PINMUX_AF('E', 9, ANALOG)
40 
41 /* ADC0_IN2 */
42 #define ADC0_IN2_PD10 \
43 	GD32_PINMUX_AF('D', 10, ANALOG)
44 
45 /* ADC0_IN3 */
46 #define ADC0_IN3_PD9 \
47 	GD32_PINMUX_AF('D', 9, ANALOG)
48 
49 /* ADC0_IN4 */
50 #define ADC0_IN4_PB14 \
51 	GD32_PINMUX_AF('B', 14, ANALOG)
52 
53 /* ADC0_IN5 */
54 #define ADC0_IN5_PB13 \
55 	GD32_PINMUX_AF('B', 13, ANALOG)
56 
57 /* ADC0_IN6 */
58 #define ADC0_IN6_PE14 \
59 	GD32_PINMUX_AF('E', 14, ANALOG)
60 
61 /* ADC0_IN7 */
62 #define ADC0_IN7_PE13 \
63 	GD32_PINMUX_AF('E', 13, ANALOG)
64 
65 /* ADC0_IN8 */
66 #define ADC0_IN8_PB2 \
67 	GD32_PINMUX_AF('B', 2, ANALOG)
68 #define ADC0_IN8_PC7 \
69 	GD32_PINMUX_AF('C', 7, ANALOG)
70 
71 /* ADC0_IN9 */
72 #define ADC0_IN9_PB1 \
73 	GD32_PINMUX_AF('B', 1, ANALOG)
74 
75 /* ADC1_IN0 */
76 #define ADC1_IN0_PA11 \
77 	GD32_PINMUX_AF('A', 11, ANALOG)
78 
79 /* ADC1_IN1 */
80 #define ADC1_IN1_PA10 \
81 	GD32_PINMUX_AF('A', 10, ANALOG)
82 
83 /* ADC1_IN10 */
84 #define ADC1_IN10_PD4 \
85 	GD32_PINMUX_AF('D', 4, ANALOG)
86 
87 /* ADC1_IN11 */
88 #define ADC1_IN11_PD3 \
89 	GD32_PINMUX_AF('D', 3, ANALOG)
90 
91 /* ADC1_IN14 */
92 #define ADC1_IN14_PB14 \
93 	GD32_PINMUX_AF('B', 14, ANALOG)
94 
95 /* ADC1_IN15 */
96 #define ADC1_IN15_PB13 \
97 	GD32_PINMUX_AF('B', 13, ANALOG)
98 
99 /* ADC1_IN2 */
100 #define ADC1_IN2_PA9 \
101 	GD32_PINMUX_AF('A', 9, ANALOG)
102 
103 /* ADC1_IN3 */
104 #define ADC1_IN3_PA8 \
105 	GD32_PINMUX_AF('A', 8, ANALOG)
106 
107 /* ADC1_IN4 */
108 #define ADC1_IN4_PD0 \
109 	GD32_PINMUX_AF('D', 0, ANALOG)
110 
111 /* ADC1_IN5 */
112 #define ADC1_IN5_PC12 \
113 	GD32_PINMUX_AF('C', 12, ANALOG)
114 
115 /* ADC1_IN6 */
116 #define ADC1_IN6_PC9 \
117 	GD32_PINMUX_AF('C', 9, ANALOG)
118 
119 /* ADC1_IN7 */
120 #define ADC1_IN7_PC8 \
121 	GD32_PINMUX_AF('C', 8, ANALOG)
122 
123 /* ADC1_IN8 */
124 #define ADC1_IN8_PC7 \
125 	GD32_PINMUX_AF('C', 7, ANALOG)
126 
127 /* ANALOG */
128 #define ANALOG_PA0 \
129 	GD32_PINMUX_AF('A', 0, ANALOG)
130 #define ANALOG_PA1 \
131 	GD32_PINMUX_AF('A', 1, ANALOG)
132 #define ANALOG_PA2 \
133 	GD32_PINMUX_AF('A', 2, ANALOG)
134 #define ANALOG_PA3 \
135 	GD32_PINMUX_AF('A', 3, ANALOG)
136 #define ANALOG_PA4 \
137 	GD32_PINMUX_AF('A', 4, ANALOG)
138 #define ANALOG_PA5 \
139 	GD32_PINMUX_AF('A', 5, ANALOG)
140 #define ANALOG_PA6 \
141 	GD32_PINMUX_AF('A', 6, ANALOG)
142 #define ANALOG_PA7 \
143 	GD32_PINMUX_AF('A', 7, ANALOG)
144 #define ANALOG_PA8 \
145 	GD32_PINMUX_AF('A', 8, ANALOG)
146 #define ANALOG_PA9 \
147 	GD32_PINMUX_AF('A', 9, ANALOG)
148 #define ANALOG_PA10 \
149 	GD32_PINMUX_AF('A', 10, ANALOG)
150 #define ANALOG_PA11 \
151 	GD32_PINMUX_AF('A', 11, ANALOG)
152 #define ANALOG_PB1 \
153 	GD32_PINMUX_AF('B', 1, ANALOG)
154 #define ANALOG_PB2 \
155 	GD32_PINMUX_AF('B', 2, ANALOG)
156 #define ANALOG_PB3 \
157 	GD32_PINMUX_AF('B', 3, ANALOG)
158 #define ANALOG_PB4 \
159 	GD32_PINMUX_AF('B', 4, ANALOG)
160 #define ANALOG_PB5 \
161 	GD32_PINMUX_AF('B', 5, ANALOG)
162 #define ANALOG_PB6 \
163 	GD32_PINMUX_AF('B', 6, ANALOG)
164 #define ANALOG_PB7 \
165 	GD32_PINMUX_AF('B', 7, ANALOG)
166 #define ANALOG_PB8 \
167 	GD32_PINMUX_AF('B', 8, ANALOG)
168 #define ANALOG_PB9 \
169 	GD32_PINMUX_AF('B', 9, ANALOG)
170 #define ANALOG_PB13 \
171 	GD32_PINMUX_AF('B', 13, ANALOG)
172 #define ANALOG_PB14 \
173 	GD32_PINMUX_AF('B', 14, ANALOG)
174 #define ANALOG_PB15 \
175 	GD32_PINMUX_AF('B', 15, ANALOG)
176 #define ANALOG_PC0 \
177 	GD32_PINMUX_AF('C', 0, ANALOG)
178 #define ANALOG_PC1 \
179 	GD32_PINMUX_AF('C', 1, ANALOG)
180 #define ANALOG_PC7 \
181 	GD32_PINMUX_AF('C', 7, ANALOG)
182 #define ANALOG_PC8 \
183 	GD32_PINMUX_AF('C', 8, ANALOG)
184 #define ANALOG_PC9 \
185 	GD32_PINMUX_AF('C', 9, ANALOG)
186 #define ANALOG_PC10 \
187 	GD32_PINMUX_AF('C', 10, ANALOG)
188 #define ANALOG_PC11 \
189 	GD32_PINMUX_AF('C', 11, ANALOG)
190 #define ANALOG_PC12 \
191 	GD32_PINMUX_AF('C', 12, ANALOG)
192 #define ANALOG_PC13 \
193 	GD32_PINMUX_AF('C', 13, ANALOG)
194 #define ANALOG_PC15 \
195 	GD32_PINMUX_AF('C', 15, ANALOG)
196 #define ANALOG_PD0 \
197 	GD32_PINMUX_AF('D', 0, ANALOG)
198 #define ANALOG_PD3 \
199 	GD32_PINMUX_AF('D', 3, ANALOG)
200 #define ANALOG_PD4 \
201 	GD32_PINMUX_AF('D', 4, ANALOG)
202 #define ANALOG_PD6 \
203 	GD32_PINMUX_AF('D', 6, ANALOG)
204 #define ANALOG_PD7 \
205 	GD32_PINMUX_AF('D', 7, ANALOG)
206 #define ANALOG_PD8 \
207 	GD32_PINMUX_AF('D', 8, ANALOG)
208 #define ANALOG_PD9 \
209 	GD32_PINMUX_AF('D', 9, ANALOG)
210 #define ANALOG_PD10 \
211 	GD32_PINMUX_AF('D', 10, ANALOG)
212 #define ANALOG_PD11 \
213 	GD32_PINMUX_AF('D', 11, ANALOG)
214 #define ANALOG_PE4 \
215 	GD32_PINMUX_AF('E', 4, ANALOG)
216 #define ANALOG_PE5 \
217 	GD32_PINMUX_AF('E', 5, ANALOG)
218 #define ANALOG_PE6 \
219 	GD32_PINMUX_AF('E', 6, ANALOG)
220 #define ANALOG_PE9 \
221 	GD32_PINMUX_AF('E', 9, ANALOG)
222 #define ANALOG_PE10 \
223 	GD32_PINMUX_AF('E', 10, ANALOG)
224 #define ANALOG_PE11 \
225 	GD32_PINMUX_AF('E', 11, ANALOG)
226 #define ANALOG_PE12 \
227 	GD32_PINMUX_AF('E', 12, ANALOG)
228 #define ANALOG_PE13 \
229 	GD32_PINMUX_AF('E', 13, ANALOG)
230 #define ANALOG_PE14 \
231 	GD32_PINMUX_AF('E', 14, ANALOG)
232 #define ANALOG_PF0 \
233 	GD32_PINMUX_AF('F', 0, ANALOG)
234 #define ANALOG_PF2 \
235 	GD32_PINMUX_AF('F', 2, ANALOG)
236 #define ANALOG_PF5 \
237 	GD32_PINMUX_AF('F', 5, ANALOG)
238 #define ANALOG_PF6 \
239 	GD32_PINMUX_AF('F', 6, ANALOG)
240 #define ANALOG_PF7 \
241 	GD32_PINMUX_AF('F', 7, ANALOG)
242 
243 /* CAN0_RX */
244 #define CAN0_RX_PA4 \
245 	GD32_PINMUX_AF('A', 4, AF6)
246 #define CAN0_RX_PB14 \
247 	GD32_PINMUX_AF('B', 14, AF6)
248 #define CAN0_RX_PF0 \
249 	GD32_PINMUX_AF('F', 0, AF6)
250 
251 /* CAN0_TX */
252 #define CAN0_TX_PA3 \
253 	GD32_PINMUX_AF('A', 3, AF6)
254 #define CAN0_TX_PB13 \
255 	GD32_PINMUX_AF('B', 13, AF6)
256 #define CAN0_TX_PC15 \
257 	GD32_PINMUX_AF('C', 15, AF6)
258 
259 /* CAN1_RX */
260 #define CAN1_RX_PD0 \
261 	GD32_PINMUX_AF('D', 0, AF6)
262 #define CAN1_RX_PD7 \
263 	GD32_PINMUX_AF('D', 7, AF6)
264 
265 /* CAN1_TX */
266 #define CAN1_TX_PC12 \
267 	GD32_PINMUX_AF('C', 12, AF6)
268 #define CAN1_TX_PD6 \
269 	GD32_PINMUX_AF('D', 6, AF6)
270 
271 /* CK_OUT */
272 #define CK_OUT_PC13 \
273 	GD32_PINMUX_AF('C', 13, AF0)
274 
275 /* CK_OUT0 */
276 #define CK_OUT0_PA1 \
277 	GD32_PINMUX_AF('A', 1, AF0)
278 
279 /* CMP_OUT */
280 #define CMP_OUT_PB9 \
281 	GD32_PINMUX_AF('B', 9, AF7)
282 #define CMP_OUT_PF2 \
283 	GD32_PINMUX_AF('F', 2, AF7)
284 
285 /* DAC_OUT */
286 #define DAC_OUT_PA7 \
287 	GD32_PINMUX_AF('A', 7, ANALOG)
288 
289 /* EVENTOUT */
290 #define EVENTOUT_PA0 \
291 	GD32_PINMUX_AF('A', 0, AF9)
292 #define EVENTOUT_PA1 \
293 	GD32_PINMUX_AF('A', 1, AF9)
294 #define EVENTOUT_PA2 \
295 	GD32_PINMUX_AF('A', 2, AF9)
296 #define EVENTOUT_PA3 \
297 	GD32_PINMUX_AF('A', 3, AF9)
298 #define EVENTOUT_PA4 \
299 	GD32_PINMUX_AF('A', 4, AF9)
300 #define EVENTOUT_PA5 \
301 	GD32_PINMUX_AF('A', 5, AF9)
302 #define EVENTOUT_PA7 \
303 	GD32_PINMUX_AF('A', 7, AF9)
304 #define EVENTOUT_PA8 \
305 	GD32_PINMUX_AF('A', 8, AF9)
306 #define EVENTOUT_PA9 \
307 	GD32_PINMUX_AF('A', 9, AF9)
308 #define EVENTOUT_PA10 \
309 	GD32_PINMUX_AF('A', 10, AF9)
310 #define EVENTOUT_PA11 \
311 	GD32_PINMUX_AF('A', 11, AF9)
312 #define EVENTOUT_PB1 \
313 	GD32_PINMUX_AF('B', 1, AF9)
314 #define EVENTOUT_PB2 \
315 	GD32_PINMUX_AF('B', 2, AF9)
316 #define EVENTOUT_PB3 \
317 	GD32_PINMUX_AF('B', 3, AF9)
318 #define EVENTOUT_PB4 \
319 	GD32_PINMUX_AF('B', 4, AF9)
320 #define EVENTOUT_PB5 \
321 	GD32_PINMUX_AF('B', 5, AF9)
322 #define EVENTOUT_PB6 \
323 	GD32_PINMUX_AF('B', 6, AF9)
324 #define EVENTOUT_PB7 \
325 	GD32_PINMUX_AF('B', 7, AF9)
326 #define EVENTOUT_PB8 \
327 	GD32_PINMUX_AF('B', 8, AF9)
328 #define EVENTOUT_PB9 \
329 	GD32_PINMUX_AF('B', 9, AF9)
330 #define EVENTOUT_PB13 \
331 	GD32_PINMUX_AF('B', 13, AF9)
332 #define EVENTOUT_PB14 \
333 	GD32_PINMUX_AF('B', 14, AF9)
334 #define EVENTOUT_PB15 \
335 	GD32_PINMUX_AF('B', 15, AF9)
336 #define EVENTOUT_PC0 \
337 	GD32_PINMUX_AF('C', 0, AF9)
338 #define EVENTOUT_PC1 \
339 	GD32_PINMUX_AF('C', 1, AF9)
340 #define EVENTOUT_PC7 \
341 	GD32_PINMUX_AF('C', 7, AF9)
342 #define EVENTOUT_PC8 \
343 	GD32_PINMUX_AF('C', 8, AF9)
344 #define EVENTOUT_PC9 \
345 	GD32_PINMUX_AF('C', 9, AF9)
346 #define EVENTOUT_PC10 \
347 	GD32_PINMUX_AF('C', 10, AF9)
348 #define EVENTOUT_PC11 \
349 	GD32_PINMUX_AF('C', 11, AF9)
350 #define EVENTOUT_PC12 \
351 	GD32_PINMUX_AF('C', 12, AF9)
352 #define EVENTOUT_PC13 \
353 	GD32_PINMUX_AF('C', 13, AF9)
354 #define EVENTOUT_PC15 \
355 	GD32_PINMUX_AF('C', 15, AF9)
356 #define EVENTOUT_PD0 \
357 	GD32_PINMUX_AF('D', 0, AF9)
358 #define EVENTOUT_PD3 \
359 	GD32_PINMUX_AF('D', 3, AF9)
360 #define EVENTOUT_PD4 \
361 	GD32_PINMUX_AF('D', 4, AF9)
362 #define EVENTOUT_PD6 \
363 	GD32_PINMUX_AF('D', 6, AF9)
364 #define EVENTOUT_PD7 \
365 	GD32_PINMUX_AF('D', 7, AF9)
366 #define EVENTOUT_PD8 \
367 	GD32_PINMUX_AF('D', 8, AF9)
368 #define EVENTOUT_PD9 \
369 	GD32_PINMUX_AF('D', 9, AF9)
370 #define EVENTOUT_PD10 \
371 	GD32_PINMUX_AF('D', 10, AF9)
372 #define EVENTOUT_PD11 \
373 	GD32_PINMUX_AF('D', 11, AF9)
374 #define EVENTOUT_PE4 \
375 	GD32_PINMUX_AF('E', 4, AF9)
376 #define EVENTOUT_PE5 \
377 	GD32_PINMUX_AF('E', 5, AF9)
378 #define EVENTOUT_PE6 \
379 	GD32_PINMUX_AF('E', 6, AF9)
380 #define EVENTOUT_PE9 \
381 	GD32_PINMUX_AF('E', 9, AF9)
382 #define EVENTOUT_PE10 \
383 	GD32_PINMUX_AF('E', 10, AF9)
384 #define EVENTOUT_PE11 \
385 	GD32_PINMUX_AF('E', 11, AF9)
386 #define EVENTOUT_PE12 \
387 	GD32_PINMUX_AF('E', 12, AF9)
388 #define EVENTOUT_PE13 \
389 	GD32_PINMUX_AF('E', 13, AF9)
390 #define EVENTOUT_PE14 \
391 	GD32_PINMUX_AF('E', 14, AF9)
392 #define EVENTOUT_PF0 \
393 	GD32_PINMUX_AF('F', 0, AF9)
394 #define EVENTOUT_PF2 \
395 	GD32_PINMUX_AF('F', 2, AF9)
396 #define EVENTOUT_PF5 \
397 	GD32_PINMUX_AF('F', 5, AF9)
398 #define EVENTOUT_PF6 \
399 	GD32_PINMUX_AF('F', 6, AF9)
400 #define EVENTOUT_PF7 \
401 	GD32_PINMUX_AF('F', 7, AF9)
402 
403 /* I2C0_SCL */
404 #define I2C0_SCL_PA10 \
405 	GD32_PINMUX_AF('A', 10, AF3)
406 #define I2C0_SCL_PC11 \
407 	GD32_PINMUX_AF('C', 11, AF3)
408 #define I2C0_SCL_PF6 \
409 	GD32_PINMUX_AF('F', 6, AF3)
410 
411 /* I2C0_SDA */
412 #define I2C0_SDA_PA11 \
413 	GD32_PINMUX_AF('A', 11, AF3)
414 #define I2C0_SDA_PC10 \
415 	GD32_PINMUX_AF('C', 10, AF3)
416 #define I2C0_SDA_PF7 \
417 	GD32_PINMUX_AF('F', 7, AF3)
418 
419 /* I2C0_SMBA */
420 #define I2C0_SMBA_PB5 \
421 	GD32_PINMUX_AF('B', 5, AF3)
422 
423 /* I2C1_SCL */
424 #define I2C1_SCL_PB7 \
425 	GD32_PINMUX_AF('B', 7, AF5)
426 #define I2C1_SCL_PD6 \
427 	GD32_PINMUX_AF('D', 6, AF5)
428 #define I2C1_SCL_PE10 \
429 	GD32_PINMUX_AF('E', 10, AF5)
430 
431 /* I2C1_SDA */
432 #define I2C1_SDA_PB8 \
433 	GD32_PINMUX_AF('B', 8, AF5)
434 #define I2C1_SDA_PD7 \
435 	GD32_PINMUX_AF('D', 7, AF5)
436 #define I2C1_SDA_PE11 \
437 	GD32_PINMUX_AF('E', 11, AF5)
438 
439 /* I2C1_SMBA */
440 #define I2C1_SMBA_PB9 \
441 	GD32_PINMUX_AF('B', 9, AF5)
442 #define I2C1_SMBA_PD11 \
443 	GD32_PINMUX_AF('D', 11, AF5)
444 #define I2C1_SMBA_PE12 \
445 	GD32_PINMUX_AF('E', 12, AF5)
446 
447 /* I2S1_CK */
448 #define I2S1_CK_PE5 \
449 	GD32_PINMUX_AF('E', 5, AF4)
450 
451 /* I2S1_MCK */
452 #define I2S1_MCK_PC7 \
453 	GD32_PINMUX_AF('C', 7, AF4)
454 #define I2S1_MCK_PE6 \
455 	GD32_PINMUX_AF('E', 6, AF4)
456 
457 /* I2S1_SD */
458 #define I2S1_SD_PA9 \
459 	GD32_PINMUX_AF('A', 9, AF4)
460 #define I2S1_SD_PB6 \
461 	GD32_PINMUX_AF('B', 6, AF5)
462 
463 /* I2S1_WS */
464 #define I2S1_WS_PA8 \
465 	GD32_PINMUX_AF('A', 8, AF4)
466 #define I2S1_WS_PB5 \
467 	GD32_PINMUX_AF('B', 5, AF6)
468 #define I2S1_WS_PD10 \
469 	GD32_PINMUX_AF('D', 10, AF4)
470 
471 /* JTCK */
472 #define JTCK_PB8 \
473 	GD32_PINMUX_AF('B', 8, AF0)
474 
475 /* JTDI */
476 #define JTDI_PB7 \
477 	GD32_PINMUX_AF('B', 7, AF0)
478 
479 /* JTDO */
480 #define JTDO_PB4 \
481 	GD32_PINMUX_AF('B', 4, AF0)
482 
483 /* JTMS */
484 #define JTMS_PB9 \
485 	GD32_PINMUX_AF('B', 9, AF0)
486 
487 /* MFCOM_D0 */
488 #define MFCOM_D0_PB4 \
489 	GD32_PINMUX_AF('B', 4, AF6)
490 #define MFCOM_D0_PE5 \
491 	GD32_PINMUX_AF('E', 5, AF6)
492 
493 /* MFCOM_D1 */
494 #define MFCOM_D1_PB3 \
495 	GD32_PINMUX_AF('B', 3, AF6)
496 #define MFCOM_D1_PE4 \
497 	GD32_PINMUX_AF('E', 4, AF6)
498 
499 /* MFCOM_D2 */
500 #define MFCOM_D2_PC11 \
501 	GD32_PINMUX_AF('C', 11, AF6)
502 
503 /* MFCOM_D3 */
504 #define MFCOM_D3_PC10 \
505 	GD32_PINMUX_AF('C', 10, AF6)
506 
507 /* MFCOM_D4 */
508 #define MFCOM_D4_PA9 \
509 	GD32_PINMUX_AF('A', 9, AF6)
510 #define MFCOM_D4_PA11 \
511 	GD32_PINMUX_AF('A', 11, AF6)
512 #define MFCOM_D4_PC13 \
513 	GD32_PINMUX_AF('C', 13, AF6)
514 
515 /* MFCOM_D5 */
516 #define MFCOM_D5_PA8 \
517 	GD32_PINMUX_AF('A', 8, AF6)
518 #define MFCOM_D5_PA10 \
519 	GD32_PINMUX_AF('A', 10, AF6)
520 #define MFCOM_D5_PE6 \
521 	GD32_PINMUX_AF('E', 6, AF6)
522 
523 /* MFCOM_D6 */
524 #define MFCOM_D6_PA9 \
525 	GD32_PINMUX_AF('A', 9, AF5)
526 #define MFCOM_D6_PF0 \
527 	GD32_PINMUX_AF('F', 0, AF7)
528 
529 /* MFCOM_D7 */
530 #define MFCOM_D7_PA8 \
531 	GD32_PINMUX_AF('A', 8, AF5)
532 #define MFCOM_D7_PC15 \
533 	GD32_PINMUX_AF('C', 15, AF7)
534 
535 /* NJTRST */
536 #define NJTRST_PB3 \
537 	GD32_PINMUX_AF('B', 3, AF0)
538 
539 /* SPI0_IO2 */
540 #define SPI0_IO2_PB3 \
541 	GD32_PINMUX_AF('B', 3, AF4)
542 
543 /* SPI0_IO3 */
544 #define SPI0_IO3_PB4 \
545 	GD32_PINMUX_AF('B', 4, AF4)
546 
547 /* SPI0_MISO */
548 #define SPI0_MISO_PB5 \
549 	GD32_PINMUX_AF('B', 5, AF4)
550 #define SPI0_MISO_PE13 \
551 	GD32_PINMUX_AF('E', 13, AF4)
552 #define SPI0_MISO_PF5 \
553 	GD32_PINMUX_AF('F', 5, AF4)
554 
555 /* SPI0_MOSI */
556 #define SPI0_MOSI_PA2 \
557 	GD32_PINMUX_AF('A', 2, AF4)
558 #define SPI0_MOSI_PB13 \
559 	GD32_PINMUX_AF('B', 13, AF4)
560 #define SPI0_MOSI_PD4 \
561 	GD32_PINMUX_AF('D', 4, AF4)
562 
563 /* SPI0_NSS */
564 #define SPI0_NSS_PA1 \
565 	GD32_PINMUX_AF('A', 1, AF4)
566 #define SPI0_NSS_PB14 \
567 	GD32_PINMUX_AF('B', 14, AF3)
568 #define SPI0_NSS_PD3 \
569 	GD32_PINMUX_AF('D', 3, AF4)
570 
571 /* SPI0_SCK */
572 #define SPI0_SCK_PB6 \
573 	GD32_PINMUX_AF('B', 6, AF4)
574 #define SPI0_SCK_PC0 \
575 	GD32_PINMUX_AF('C', 0, AF4)
576 #define SPI0_SCK_PE14 \
577 	GD32_PINMUX_AF('E', 14, AF4)
578 
579 /* SPI1_MISO */
580 #define SPI1_MISO_PE4 \
581 	GD32_PINMUX_AF('E', 4, AF4)
582 
583 /* SPI1_MOSI */
584 #define SPI1_MOSI_PA9 \
585 	GD32_PINMUX_AF('A', 9, AF4)
586 #define SPI1_MOSI_PB6 \
587 	GD32_PINMUX_AF('B', 6, AF5)
588 
589 /* SPI1_NSS */
590 #define SPI1_NSS_PA8 \
591 	GD32_PINMUX_AF('A', 8, AF4)
592 #define SPI1_NSS_PB5 \
593 	GD32_PINMUX_AF('B', 5, AF5)
594 #define SPI1_NSS_PD10 \
595 	GD32_PINMUX_AF('D', 10, AF4)
596 
597 /* SPI1_SCK */
598 #define SPI1_SCK_PE5 \
599 	GD32_PINMUX_AF('E', 5, AF4)
600 
601 /* SWCLK */
602 #define SWCLK_PB8 \
603 	GD32_PINMUX_AF('B', 8, AF0)
604 
605 /* SWDIO */
606 #define SWDIO_PB9 \
607 	GD32_PINMUX_AF('B', 9, AF0)
608 
609 /* TIMER0_BRKIN0 */
610 #define TIMER0_BRKIN0_PA8 \
611 	GD32_PINMUX_AF('A', 8, AF1)
612 #define TIMER0_BRKIN0_PF2 \
613 	GD32_PINMUX_AF('F', 2, AF1)
614 
615 /* TIMER0_BRKIN1 */
616 #define TIMER0_BRKIN1_PD10 \
617 	GD32_PINMUX_AF('D', 10, AF2)
618 
619 /* TIMER0_BRKIN2 */
620 #define TIMER0_BRKIN2_PD9 \
621 	GD32_PINMUX_AF('D', 9, AF2)
622 
623 /* TIMER0_BRKIN3 */
624 #define TIMER0_BRKIN3_PC9 \
625 	GD32_PINMUX_AF('C', 9, AF1)
626 
627 /* TIMER0_CH0 */
628 #define TIMER0_CH0_PB2 \
629 	GD32_PINMUX_AF('B', 2, AF1)
630 #define TIMER0_CH0_PC0 \
631 	GD32_PINMUX_AF('C', 0, AF1)
632 #define TIMER0_CH0_PC8 \
633 	GD32_PINMUX_AF('C', 8, AF1)
634 
635 /* TIMER0_CH1 */
636 #define TIMER0_CH1_PA4 \
637 	GD32_PINMUX_AF('A', 4, AF1)
638 #define TIMER0_CH1_PE5 \
639 	GD32_PINMUX_AF('E', 5, AF1)
640 
641 /* TIMER0_CH2 */
642 #define TIMER0_CH2_PA2 \
643 	GD32_PINMUX_AF('A', 2, AF1)
644 
645 /* TIMER0_CH3 */
646 #define TIMER0_CH3_PA0 \
647 	GD32_PINMUX_AF('A', 0, AF1)
648 
649 /* TIMER0_MCH0 */
650 #define TIMER0_MCH0_PB1 \
651 	GD32_PINMUX_AF('B', 1, AF1)
652 #define TIMER0_MCH0_PC7 \
653 	GD32_PINMUX_AF('C', 7, AF1)
654 #define TIMER0_MCH0_PF5 \
655 	GD32_PINMUX_AF('F', 5, AF1)
656 
657 /* TIMER0_MCH1 */
658 #define TIMER0_MCH1_PA3 \
659 	GD32_PINMUX_AF('A', 3, AF1)
660 #define TIMER0_MCH1_PE4 \
661 	GD32_PINMUX_AF('E', 4, AF1)
662 
663 /* TIMER0_MCH2 */
664 #define TIMER0_MCH2_PA1 \
665 	GD32_PINMUX_AF('A', 1, AF1)
666 
667 /* TIMER0_MCH3 */
668 #define TIMER0_MCH3_PC1 \
669 	GD32_PINMUX_AF('C', 1, AF1)
670 #define TIMER0_MCH3_PD11 \
671 	GD32_PINMUX_AF('D', 11, AF1)
672 
673 /* TIMER19_BRKIN1 */
674 #define TIMER19_BRKIN1_PA7 \
675 	GD32_PINMUX_AF('A', 7, AF3)
676 
677 /* TIMER19_BRKIN2 */
678 #define TIMER19_BRKIN2_PA6 \
679 	GD32_PINMUX_AF('A', 6, AF2)
680 
681 /* TIMER19_BRKIN3 */
682 #define TIMER19_BRKIN3_PA5 \
683 	GD32_PINMUX_AF('A', 5, AF2)
684 
685 /* TIMER19_CH0 */
686 #define TIMER19_CH0_PB7 \
687 	GD32_PINMUX_AF('B', 7, AF1)
688 #define TIMER19_CH0_PC11 \
689 	GD32_PINMUX_AF('C', 11, AF2)
690 #define TIMER19_CH0_PD6 \
691 	GD32_PINMUX_AF('D', 6, AF2)
692 #define TIMER19_CH0_PE5 \
693 	GD32_PINMUX_AF('E', 5, AF2)
694 
695 /* TIMER19_CH1 */
696 #define TIMER19_CH1_PB7 \
697 	GD32_PINMUX_AF('B', 7, AF2)
698 #define TIMER19_CH1_PC15 \
699 	GD32_PINMUX_AF('C', 15, AF2)
700 #define TIMER19_CH1_PD7 \
701 	GD32_PINMUX_AF('D', 7, AF2)
702 #define TIMER19_CH1_PF0 \
703 	GD32_PINMUX_AF('F', 0, AF1)
704 
705 /* TIMER19_CH2 */
706 #define TIMER19_CH2_PC13 \
707 	GD32_PINMUX_AF('C', 13, AF1)
708 
709 /* TIMER19_MCH0 */
710 #define TIMER19_MCH0_PC11 \
711 	GD32_PINMUX_AF('C', 11, AF1)
712 #define TIMER19_MCH0_PE4 \
713 	GD32_PINMUX_AF('E', 4, AF2)
714 
715 /* TIMER19_MCH1 */
716 #define TIMER19_MCH1_PA7 \
717 	GD32_PINMUX_AF('A', 7, AF1)
718 #define TIMER19_MCH1_PC15 \
719 	GD32_PINMUX_AF('C', 15, AF1)
720 
721 /* TIMER19_MCH2 */
722 #define TIMER19_MCH2_PE6 \
723 	GD32_PINMUX_AF('E', 6, AF2)
724 
725 /* TIMER1_CH0 */
726 #define TIMER1_CH0_PE6 \
727 	GD32_PINMUX_AF('E', 6, AF1)
728 
729 /* TIMER1_CH1 */
730 #define TIMER1_CH1_PA7 \
731 	GD32_PINMUX_AF('A', 7, AF2)
732 
733 /* TIMER1_CH2 */
734 #define TIMER1_CH2_PB14 \
735 	GD32_PINMUX_AF('B', 14, AF1)
736 #define TIMER1_CH2_PD4 \
737 	GD32_PINMUX_AF('D', 4, AF2)
738 
739 /* TIMER1_CH3 */
740 #define TIMER1_CH3_PA3 \
741 	GD32_PINMUX_AF('A', 3, AF2)
742 
743 /* TIMER1_ETI */
744 #define TIMER1_ETI_PE6 \
745 	GD32_PINMUX_AF('E', 6, AF1)
746 
747 /* TIMER20_BRKIN0 */
748 #define TIMER20_BRKIN0_PD11 \
749 	GD32_PINMUX_AF('D', 11, AF2)
750 
751 /* TIMER20_BRKIN1 */
752 #define TIMER20_BRKIN1_PC7 \
753 	GD32_PINMUX_AF('C', 7, AF2)
754 
755 /* TIMER20_BRKIN2 */
756 #define TIMER20_BRKIN2_PC8 \
757 	GD32_PINMUX_AF('C', 8, AF2)
758 
759 /* TIMER20_BRKIN3 */
760 #define TIMER20_BRKIN3_PC9 \
761 	GD32_PINMUX_AF('C', 9, AF2)
762 
763 /* TIMER20_CH0 */
764 #define TIMER20_CH0_PA11 \
765 	GD32_PINMUX_AF('A', 11, AF1)
766 
767 /* TIMER20_CH1 */
768 #define TIMER20_CH1_PD0 \
769 	GD32_PINMUX_AF('D', 0, AF1)
770 
771 /* TIMER20_CH2 */
772 #define TIMER20_CH2_PA9 \
773 	GD32_PINMUX_AF('A', 9, AF1)
774 
775 /* TIMER20_CH3 */
776 #define TIMER20_CH3_PD4 \
777 	GD32_PINMUX_AF('D', 4, AF1)
778 
779 /* TIMER20_MCH0 */
780 #define TIMER20_MCH0_PA10 \
781 	GD32_PINMUX_AF('A', 10, AF1)
782 
783 /* TIMER20_MCH1 */
784 #define TIMER20_MCH1_PC12 \
785 	GD32_PINMUX_AF('C', 12, AF1)
786 
787 /* TIMER20_MCH2 */
788 #define TIMER20_MCH2_PA8 \
789 	GD32_PINMUX_AF('A', 8, AF2)
790 
791 /* TIMER20_MCH3 */
792 #define TIMER20_MCH3_PD3 \
793 	GD32_PINMUX_AF('D', 3, AF1)
794 
795 /* TIMER7_BRKIN0 */
796 #define TIMER7_BRKIN0_PD8 \
797 	GD32_PINMUX_AF('D', 8, AF2)
798 
799 /* TIMER7_BRKIN1 */
800 #define TIMER7_BRKIN1_PB5 \
801 	GD32_PINMUX_AF('B', 5, AF2)
802 #define TIMER7_BRKIN1_PB15 \
803 	GD32_PINMUX_AF('B', 15, AF2)
804 
805 /* TIMER7_BRKIN2 */
806 #define TIMER7_BRKIN2_PB6 \
807 	GD32_PINMUX_AF('B', 6, AF2)
808 #define TIMER7_BRKIN2_PE10 \
809 	GD32_PINMUX_AF('E', 10, AF2)
810 
811 /* TIMER7_BRKIN3 */
812 #define TIMER7_BRKIN3_PE9 \
813 	GD32_PINMUX_AF('E', 9, AF2)
814 
815 /* TIMER7_CH0 */
816 #define TIMER7_CH0_PB8 \
817 	GD32_PINMUX_AF('B', 8, AF1)
818 #define TIMER7_CH0_PC10 \
819 	GD32_PINMUX_AF('C', 10, AF2)
820 #define TIMER7_CH0_PC12 \
821 	GD32_PINMUX_AF('C', 12, AF2)
822 #define TIMER7_CH0_PE13 \
823 	GD32_PINMUX_AF('E', 13, AF2)
824 #define TIMER7_CH0_PE14 \
825 	GD32_PINMUX_AF('E', 14, AF1)
826 
827 /* TIMER7_CH1 */
828 #define TIMER7_CH1_PB8 \
829 	GD32_PINMUX_AF('B', 8, AF2)
830 #define TIMER7_CH1_PD0 \
831 	GD32_PINMUX_AF('D', 0, AF2)
832 #define TIMER7_CH1_PE12 \
833 	GD32_PINMUX_AF('E', 12, AF1)
834 #define TIMER7_CH1_PE14 \
835 	GD32_PINMUX_AF('E', 14, AF2)
836 
837 /* TIMER7_CH2 */
838 #define TIMER7_CH2_PB4 \
839 	GD32_PINMUX_AF('B', 4, AF1)
840 
841 /* TIMER7_CH3 */
842 #define TIMER7_CH3_PB2 \
843 	GD32_PINMUX_AF('B', 2, AF2)
844 #define TIMER7_CH3_PD7 \
845 	GD32_PINMUX_AF('D', 7, AF1)
846 
847 /* TIMER7_MCH0 */
848 #define TIMER7_MCH0_PC10 \
849 	GD32_PINMUX_AF('C', 10, AF1)
850 #define TIMER7_MCH0_PE13 \
851 	GD32_PINMUX_AF('E', 13, AF1)
852 
853 /* TIMER7_MCH1 */
854 #define TIMER7_MCH1_PE11 \
855 	GD32_PINMUX_AF('E', 11, AF1)
856 
857 /* TIMER7_MCH2 */
858 #define TIMER7_MCH2_PB3 \
859 	GD32_PINMUX_AF('B', 3, AF1)
860 
861 /* TIMER7_MCH3 */
862 #define TIMER7_MCH3_PB1 \
863 	GD32_PINMUX_AF('B', 1, AF2)
864 #define TIMER7_MCH3_PD6 \
865 	GD32_PINMUX_AF('D', 6, AF1)
866 
867 /* TIMER_ETI0 */
868 #define TIMER_ETI0_PB13 \
869 	GD32_PINMUX_AF('B', 13, AF0)
870 
871 /* TIMER_ETI1 */
872 #define TIMER_ETI1_PB6 \
873 	GD32_PINMUX_AF('B', 6, AF3)
874 
875 /* TIMER_ETI2 */
876 #define TIMER_ETI2_PC15 \
877 	GD32_PINMUX_AF('C', 15, AF0)
878 
879 /* TIMRE19_BRKIN0 */
880 #define TIMRE19_BRKIN0_PF2 \
881 	GD32_PINMUX_AF('F', 2, AF2)
882 
883 /* TRIGSEL_IN0 */
884 #define TRIGSEL_IN0_PA1 \
885 	GD32_PINMUX_AF('A', 1, AF7)
886 
887 /* TRIGSEL_IN1 */
888 #define TRIGSEL_IN1_PA2 \
889 	GD32_PINMUX_AF('A', 2, AF7)
890 
891 /* TRIGSEL_IN13 */
892 #define TRIGSEL_IN13_PA11 \
893 	GD32_PINMUX_AF('A', 11, AF7)
894 
895 /* TRIGSEL_IN2 */
896 #define TRIGSEL_IN2_PE13 \
897 	GD32_PINMUX_AF('E', 13, AF7)
898 
899 /* TRIGSEL_IN3 */
900 #define TRIGSEL_IN3_PE14 \
901 	GD32_PINMUX_AF('E', 14, AF7)
902 
903 /* TRIGSEL_IN4 */
904 #define TRIGSEL_IN4_PA8 \
905 	GD32_PINMUX_AF('A', 8, AF7)
906 
907 /* TRIGSEL_IN5 */
908 #define TRIGSEL_IN5_PA9 \
909 	GD32_PINMUX_AF('A', 9, AF7)
910 
911 /* TRIGSEL_IN6 */
912 #define TRIGSEL_IN6_PF2 \
913 	GD32_PINMUX_AF('F', 2, AF6)
914 
915 /* TRIGSEL_IN7 */
916 #define TRIGSEL_IN7_PA7 \
917 	GD32_PINMUX_AF('A', 7, AF7)
918 
919 /* TRIGSEL_IN8 */
920 #define TRIGSEL_IN8_PE11 \
921 	GD32_PINMUX_AF('E', 11, AF7)
922 
923 /* TRIGSEL_IN9 */
924 #define TRIGSEL_IN9_PE12 \
925 	GD32_PINMUX_AF('E', 12, AF7)
926 
927 /* TRIGSEL_OUT0 */
928 #define TRIGSEL_OUT0_PC10 \
929 	GD32_PINMUX_AF('C', 10, AF7)
930 
931 /* TRIGSEL_OUT1 */
932 #define TRIGSEL_OUT1_PE5 \
933 	GD32_PINMUX_AF('E', 5, AF7)
934 
935 /* TRIGSEL_OUT2 */
936 #define TRIGSEL_OUT2_PE4 \
937 	GD32_PINMUX_AF('E', 4, AF7)
938 
939 /* TRIGSEL_OUT3 */
940 #define TRIGSEL_OUT3_PC11 \
941 	GD32_PINMUX_AF('C', 11, AF7)
942 
943 /* TRIGSEL_OUT4 */
944 #define TRIGSEL_OUT4_PC13 \
945 	GD32_PINMUX_AF('C', 13, AF7)
946 
947 /* TRIGSEL_OUT5 */
948 #define TRIGSEL_OUT5_PE6 \
949 	GD32_PINMUX_AF('E', 6, AF7)
950 
951 /* USART0_CTS */
952 #define USART0_CTS_PC11 \
953 	GD32_PINMUX_AF('C', 11, AF5)
954 #define USART0_CTS_PD8 \
955 	GD32_PINMUX_AF('D', 8, AF5)
956 
957 /* USART0_DE */
958 #define USART0_DE_PB15 \
959 	GD32_PINMUX_AF('B', 15, AF5)
960 #define USART0_DE_PC10 \
961 	GD32_PINMUX_AF('C', 10, AF5)
962 
963 /* USART0_RTS */
964 #define USART0_RTS_PB15 \
965 	GD32_PINMUX_AF('B', 15, AF5)
966 #define USART0_RTS_PC10 \
967 	GD32_PINMUX_AF('C', 10, AF5)
968 
969 /* USART0_RX */
970 #define USART0_RX_PA4 \
971 	GD32_PINMUX_AF('A', 4, AF5)
972 #define USART0_RX_PA11 \
973 	GD32_PINMUX_AF('A', 11, AF5)
974 #define USART0_RX_PB14 \
975 	GD32_PINMUX_AF('B', 14, AF5)
976 
977 /* USART0_TX */
978 #define USART0_TX_PA3 \
979 	GD32_PINMUX_AF('A', 3, AF5)
980 #define USART0_TX_PA10 \
981 	GD32_PINMUX_AF('A', 10, AF5)
982 #define USART0_TX_PB13 \
983 	GD32_PINMUX_AF('B', 13, AF5)
984 
985 /* USART1_CTS */
986 #define USART1_CTS_PD4 \
987 	GD32_PINMUX_AF('D', 4, AF5)
988 #define USART1_CTS_PD10 \
989 	GD32_PINMUX_AF('D', 10, AF5)
990 #define USART1_CTS_PF5 \
991 	GD32_PINMUX_AF('F', 5, AF5)
992 
993 /* USART1_DE */
994 #define USART1_DE_PD3 \
995 	GD32_PINMUX_AF('D', 3, AF5)
996 #define USART1_DE_PD9 \
997 	GD32_PINMUX_AF('D', 9, AF5)
998 
999 /* USART1_RTS */
1000 #define USART1_RTS_PD3 \
1001 	GD32_PINMUX_AF('D', 3, AF5)
1002 #define USART1_RTS_PD9 \
1003 	GD32_PINMUX_AF('D', 9, AF5)
1004 
1005 /* USART1_RX */
1006 #define USART1_RX_PD0 \
1007 	GD32_PINMUX_AF('D', 0, AF5)
1008 #define USART1_RX_PD8 \
1009 	GD32_PINMUX_AF('D', 8, AF4)
1010 
1011 /* USART1_TX */
1012 #define USART1_TX_PB15 \
1013 	GD32_PINMUX_AF('B', 15, AF4)
1014 #define USART1_TX_PC12 \
1015 	GD32_PINMUX_AF('C', 12, AF5)
1016 
1017 /* USART2_CK */
1018 #define USART2_CK_PA7 \
1019 	GD32_PINMUX_AF('A', 7, AF5)
1020 
1021 /* USART2_CTS */
1022 #define USART2_CTS_PC1 \
1023 	GD32_PINMUX_AF('C', 1, AF5)
1024 
1025 /* USART2_DE */
1026 #define USART2_DE_PF2 \
1027 	GD32_PINMUX_AF('F', 2, AF5)
1028 
1029 /* USART2_RTS */
1030 #define USART2_RTS_PF2 \
1031 	GD32_PINMUX_AF('F', 2, AF5)
1032 
1033 /* USART2_RX */
1034 #define USART2_RX_PA6 \
1035 	GD32_PINMUX_AF('A', 6, AF5)
1036 
1037 /* USART2_TX */
1038 #define USART2_TX_PA5 \
1039 	GD32_PINMUX_AF('A', 5, AF5)
1040