1 /*!
2 \file gd32e50x_timer.c
3 \brief TIMER driver
4
5 \version 2020-03-10, V1.0.0, firmware for GD32E50x
6 \version 2020-08-26, V1.1.0, firmware for GD32E50x
7 \version 2021-03-23, V1.2.0, firmware for GD32E50x
8 */
9
10 /*
11 Copyright (c) 2021, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32e50x_timer.h"
38
39 /* TIMER init parameter mask */
40 #define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */
41 #define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */
42 #define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */
43
44 /*!
45 \brief deinit a TIMER
46 \param[in] timer_periph: TIMERx(x=0..13)
47 \param[out] none
48 \retval none
49 */
timer_deinit(uint32_t timer_periph)50 void timer_deinit(uint32_t timer_periph)
51 {
52 switch(timer_periph){
53 case TIMER0:
54 /* reset TIMER0 */
55 rcu_periph_reset_enable(RCU_TIMER0RST);
56 rcu_periph_reset_disable(RCU_TIMER0RST);
57 break;
58 case TIMER1:
59 /* reset TIMER1 */
60 rcu_periph_reset_enable(RCU_TIMER1RST);
61 rcu_periph_reset_disable(RCU_TIMER1RST);
62 break;
63 case TIMER2:
64 /* reset TIMER2 */
65 rcu_periph_reset_enable(RCU_TIMER2RST);
66 rcu_periph_reset_disable(RCU_TIMER2RST);
67 break;
68 case TIMER3:
69 /* reset TIMER3 */
70 rcu_periph_reset_enable(RCU_TIMER3RST);
71 rcu_periph_reset_disable(RCU_TIMER3RST);
72 break;
73 case TIMER4:
74 /* reset TIMER4 */
75 rcu_periph_reset_enable(RCU_TIMER4RST);
76 rcu_periph_reset_disable(RCU_TIMER4RST);
77 break;
78 case TIMER5:
79 /* reset TIMER5 */
80 rcu_periph_reset_enable(RCU_TIMER5RST);
81 rcu_periph_reset_disable(RCU_TIMER5RST);
82 break;
83 case TIMER6:
84 /* reset TIMER6 */
85 rcu_periph_reset_enable(RCU_TIMER6RST);
86 rcu_periph_reset_disable(RCU_TIMER6RST);
87 break;
88 case TIMER7:
89 /* reset TIMER7 */
90 rcu_periph_reset_enable(RCU_TIMER7RST);
91 rcu_periph_reset_disable(RCU_TIMER7RST);
92 break;
93 #ifndef GD32EPRT
94 case TIMER8:
95 /* reset TIMER8 */
96 rcu_periph_reset_enable(RCU_TIMER8RST);
97 rcu_periph_reset_disable(RCU_TIMER8RST);
98 break;
99 case TIMER9:
100 /* reset TIMER9 */
101 rcu_periph_reset_enable(RCU_TIMER9RST);
102 rcu_periph_reset_disable(RCU_TIMER9RST);
103 break;
104 case TIMER10:
105 /* reset TIMER10 */
106 rcu_periph_reset_enable(RCU_TIMER10RST);
107 rcu_periph_reset_disable(RCU_TIMER10RST);
108 break;
109 case TIMER11:
110 /* reset TIMER11 */
111 rcu_periph_reset_enable(RCU_TIMER11RST);
112 rcu_periph_reset_disable(RCU_TIMER11RST);
113 break;
114 case TIMER12:
115 /* reset TIMER12 */
116 rcu_periph_reset_enable(RCU_TIMER12RST);
117 rcu_periph_reset_disable(RCU_TIMER12RST);
118 break;
119 case TIMER13:
120 /* reset TIMER13 */
121 rcu_periph_reset_enable(RCU_TIMER13RST);
122 rcu_periph_reset_disable(RCU_TIMER13RST);
123 break;
124 #endif /* GD32EPRT */
125 default:
126 break;
127 }
128 }
129
130 /*!
131 \brief initialize TIMER init parameter struct with a default value
132 \param[in] initpara: init parameter struct
133 \param[out] none
134 \retval none
135 */
timer_struct_para_init(timer_parameter_struct * initpara)136 void timer_struct_para_init(timer_parameter_struct* initpara)
137 {
138 /* initialize the init parameter struct member with the default value */
139 initpara->prescaler = 0U;
140 initpara->alignedmode = TIMER_COUNTER_EDGE;
141 initpara->counterdirection = TIMER_COUNTER_UP;
142 initpara->period = 65535U;
143 initpara->clockdivision = TIMER_CKDIV_DIV1;
144 initpara->repetitioncounter = 0U;
145 }
146
147 /*!
148 \brief initialize TIMER counter
149 \param[in] timer_periph: TIMERx(x=0..13)
150 \param[in] initpara: init parameter struct
151 prescaler: prescaler value of the counter clock, 0~65535
152 alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH
153 counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN
154 period: counter auto reload value, 0~65535
155 clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4
156 repetitioncounter: counter repetition value, 0~255
157 \param[out] none
158 \retval none
159 */
gd32_timer_init(uint32_t timer_periph,timer_parameter_struct * initpara)160 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
161 {
162 /* configure the counter prescaler value */
163 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
164
165 /* configure the counter direction and aligned mode */
166 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)
167 || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){
168 TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM));
169 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK);
170 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
171 }
172
173 /* configure the autoreload value */
174 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
175
176 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
177 /* reset the CKDIV bit */
178 TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV);
179 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK);
180 }
181
182 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
183 /* configure the repetition counter value */
184 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
185 }
186
187 /* generate an update event */
188 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
189 }
190
191 /*!
192 \brief enable a TIMER
193 \param[in] timer_periph: TIMERx(x=0..13)
194 \param[out] none
195 \retval none
196 */
timer_enable(uint32_t timer_periph)197 void timer_enable(uint32_t timer_periph)
198 {
199 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
200 }
201
202 /*!
203 \brief disable a TIMER
204 \param[in] timer_periph: TIMERx(x=0..13)
205 \param[out] none
206 \retval none
207 */
timer_disable(uint32_t timer_periph)208 void timer_disable(uint32_t timer_periph)
209 {
210 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
211 }
212
213 /*!
214 \brief enable the auto reload shadow function
215 \param[in] timer_periph: TIMERx(x=0..13)
216 \param[out] none
217 \retval none
218 */
timer_auto_reload_shadow_enable(uint32_t timer_periph)219 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
220 {
221 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
222 }
223
224 /*!
225 \brief disable the auto reload shadow function
226 \param[in] timer_periph: TIMERx(x=0..13)
227 \param[out] none
228 \retval none
229 */
timer_auto_reload_shadow_disable(uint32_t timer_periph)230 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
231 {
232 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
233 }
234
235 /*!
236 \brief enable the update event
237 \param[in] timer_periph: TIMERx(x=0..13)
238 \param[out] none
239 \retval none
240 */
timer_update_event_enable(uint32_t timer_periph)241 void timer_update_event_enable(uint32_t timer_periph)
242 {
243 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
244 }
245
246 /*!
247 \brief disable the update event
248 \param[in] timer_periph: TIMERx(x=0..13)
249 \param[out] none
250 \retval none
251 */
timer_update_event_disable(uint32_t timer_periph)252 void timer_update_event_disable(uint32_t timer_periph)
253 {
254 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
255 }
256
257 /*!
258 \brief set TIMER counter alignment mode
259 \param[in] timer_periph: TIMERx(x=0..4,7)
260 \param[in] aligned:
261 only one parameter can be selected which is shown as below:
262 \arg TIMER_COUNTER_EDGE: edge-aligned mode
263 \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
264 \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
265 \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
266 \param[out] none
267 \retval none
268 */
timer_counter_alignment(uint32_t timer_periph,uint16_t aligned)269 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
270 {
271 TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM);
272 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
273 }
274
275 /*!
276 \brief set TIMER counter up direction
277 \param[in] timer_periph: TIMERx(x=0..4,7)
278 \param[out] none
279 \retval none
280 */
timer_counter_up_direction(uint32_t timer_periph)281 void timer_counter_up_direction(uint32_t timer_periph)
282 {
283 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
284 }
285
286 /*!
287 \brief set TIMER counter down direction
288 \param[in] timer_periph: TIMERx(x=0..4,7)
289 \param[out] none
290 \retval none
291 */
timer_counter_down_direction(uint32_t timer_periph)292 void timer_counter_down_direction(uint32_t timer_periph)
293 {
294 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
295 }
296
297 /*!
298 \brief configure TIMER prescaler
299 \param[in] timer_periph: TIMERx(x=0..13)
300 \param[in] prescaler: prescaler value,0~65535
301 \param[in] pscreload: prescaler reload mode
302 only one parameter can be selected which is shown as below:
303 \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
304 \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
305 \param[out] none
306 \retval none
307 */
timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint32_t pscreload)308 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload)
309 {
310 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
311
312 if(TIMER_PSC_RELOAD_NOW == pscreload){
313 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
314 }
315 }
316
317 /*!
318 \brief configure TIMER repetition register value
319 \param[in] timer_periph: TIMERx(x=0,7)
320 \param[in] repetition: the counter repetition value, 0~255
321 \param[out] none
322 \retval none
323 */
timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition)324 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
325 {
326 TIMER_CREP(timer_periph) = (uint32_t)repetition;
327 }
328
329 /*!
330 \brief configure TIMER autoreload register value
331 \param[in] timer_periph: TIMERx(x=0..13)
332 \param[in] autoreload: the counter auto-reload value,0~65535
333 \param[out] none
334 \retval none
335 */
timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload)336 void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
337 {
338 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
339 }
340
341 /*!
342 \brief configure TIMER counter register value
343 \param[in] timer_periph: TIMERx(x=0..13)
344 \param[in] counter: the counter value,0~65535
345 \param[out] none
346 \retval none
347 */
timer_counter_value_config(uint32_t timer_periph,uint32_t counter)348 void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
349 {
350 TIMER_CNT(timer_periph) = (uint32_t)counter;
351 }
352
353 /*!
354 \brief read TIMER counter value
355 \param[in] timer_periph: TIMERx(x=0..13)
356 \param[out] none
357 \retval counter value
358 */
timer_counter_read(uint32_t timer_periph)359 uint32_t timer_counter_read(uint32_t timer_periph)
360 {
361 uint32_t count_value = 0U;
362 count_value = TIMER_CNT(timer_periph);
363 return (count_value);
364 }
365
366 /*!
367 \brief read TIMER prescaler value
368 \param[in] timer_periph: TIMERx(x=0..13)
369 \param[out] none
370 \retval prescaler register value
371 */
timer_prescaler_read(uint32_t timer_periph)372 uint16_t timer_prescaler_read(uint32_t timer_periph)
373 {
374 uint16_t prescaler_value = 0U;
375 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
376 return (prescaler_value);
377 }
378
379 /*!
380 \brief configure TIMER single pulse mode
381 \param[in] timer_periph: TIMERx(x=0..8,11)
382 \param[in] spmode:
383 only one parameter can be selected which is shown as below:
384 \arg TIMER_SP_MODE_SINGLE: single pulse mode
385 \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
386 \param[out] none
387 \retval none
388 */
timer_single_pulse_mode_config(uint32_t timer_periph,uint32_t spmode)389 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
390 {
391 if(TIMER_SP_MODE_SINGLE == spmode){
392 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
393 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
394 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
395 }else{
396 /* illegal parameters */
397 }
398 }
399
400 /*!
401 \brief configure TIMER update source
402 \param[in] timer_periph: TIMERx(x=0..13)
403 \param[in] update:
404 only one parameter can be selected which is shown as below:
405 \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
406 \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
407 \param[out] none
408 \retval none
409 */
timer_update_source_config(uint32_t timer_periph,uint32_t update)410 void timer_update_source_config(uint32_t timer_periph, uint32_t update)
411 {
412 if(TIMER_UPDATE_SRC_REGULAR == update){
413 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
414 }else if(TIMER_UPDATE_SRC_GLOBAL == update){
415 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
416 }else{
417 /* illegal parameters */
418 }
419 }
420
421 /*!
422 \brief enable the TIMER DMA
423 \param[in] timer_periph: please refer to the following parameters
424 \param[in] dma: specify which DMA to enable
425 only one parameter can be selected which is shown as below:
426 \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7)
427 \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7)
428 \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7)
429 \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7)
430 \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7)
431 \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7)
432 \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7)
433 \param[out] none
434 \retval none
435 */
timer_dma_enable(uint32_t timer_periph,uint16_t dma)436 void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
437 {
438 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
439 }
440
441 /*!
442 \brief disable the TIMER DMA
443 \param[in] timer_periph: please refer to the following parameters
444 \param[in] dma: specify which DMA to enable
445 one or more parameters can be selected which are shown as below:
446 \arg TIMER_DMA_UPD: update DMA ,TIMERx(x=0..7)
447 \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7)
448 \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7)
449 \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7)
450 \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7)
451 \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7)
452 \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7)
453 \param[out] none
454 \retval none
455 */
timer_dma_disable(uint32_t timer_periph,uint16_t dma)456 void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
457 {
458 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
459 }
460
461 /*!
462 \brief channel DMA request source selection
463 \param[in] timer_periph: TIMERx(x=0..4,7)
464 \param[in] dma_request: channel DMA request source selection
465 only one parameter can be selected which is shown as below:
466 \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
467 \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
468 \param[out] none
469 \retval none
470 */
timer_channel_dma_request_source_select(uint32_t timer_periph,uint32_t dma_request)471 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request)
472 {
473 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
474 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
475 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
476 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
477 }else{
478 /* illegal parameters */
479 }
480 }
481
482 /*!
483 \brief configure the TIMER DMA transfer
484 \param[in] timer_periph: please refer to the following parameters
485 \param[in] dma_baseaddr:
486 only one parameter can be selected which is shown as below:
487 \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7)
488 \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7)
489 \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7)
490 \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7)
491 \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7)
492 \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7)
493 \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7)
494 \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7)
495 \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7)
496 \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7)
497 \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7)
498 \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7)
499 \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7)
500 \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7)
501 \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7)
502 \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7)
503 \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7)
504 \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7)
505 \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7)
506 \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7)
507 \param[in] dma_lenth:
508 only one parameter can be selected which is shown as below:
509 \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
510 \param[out] none
511 \retval none
512 */
timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth)513 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
514 {
515 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
516 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
517 }
518
519 /*!
520 \brief software generate events
521 \param[in] timer_periph: please refer to the following parameters
522 \param[in] event: the timer software event generation sources
523 one or more parameters can be selected which are shown as below:
524 \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13)
525 \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13)
526 \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11)
527 \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7)
528 \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7)
529 \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7)
530 \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11)
531 \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7)
532 \param[out] none
533 \retval none
534 */
timer_event_software_generate(uint32_t timer_periph,uint16_t event)535 void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
536 {
537 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
538 }
539
540 /*!
541 \brief initialize TIMER break parameter struct with a default value
542 \param[in] breakpara: TIMER break parameter struct
543 \param[out] none
544 \retval none
545 */
timer_break_struct_para_init(timer_break_parameter_struct * breakpara)546 void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
547 {
548 /* initialize the break parameter struct member with the default value */
549 breakpara->runoffstate = TIMER_ROS_STATE_DISABLE;
550 breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE;
551 breakpara->deadtime = 0U;
552 breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW;
553 breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
554 breakpara->protectmode = TIMER_CCHP_PROT_OFF;
555 breakpara->breakstate = TIMER_BREAK_DISABLE;
556 }
557
558 /*!
559 \brief configure TIMER break function
560 \param[in] timer_periph: TIMERx(x=0,7)
561 \param[in] breakpara: TIMER break parameter struct
562 runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE
563 ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE
564 deadtime: 0~255
565 breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH
566 outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE
567 protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2
568 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
569 \param[out] none
570 \retval none
571 */
timer_break_config(uint32_t timer_periph,timer_break_parameter_struct * breakpara)572 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
573 {
574 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))|
575 ((uint32_t)(breakpara->ideloffstate))|
576 ((uint32_t)(breakpara->deadtime))|
577 ((uint32_t)(breakpara->breakpolarity))|
578 ((uint32_t)(breakpara->outputautostate)) |
579 ((uint32_t)(breakpara->protectmode))|
580 ((uint32_t)(breakpara->breakstate))) ;
581 }
582
583 /*!
584 \brief enable TIMER break function
585 \param[in] timer_periph: TIMERx(x=0,7)
586 \param[out] none
587 \retval none
588 */
timer_break_enable(uint32_t timer_periph)589 void timer_break_enable(uint32_t timer_periph)
590 {
591 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
592 }
593
594 /*!
595 \brief disable TIMER break function
596 \param[in] timer_periph: TIMERx(x=0,7)
597 \param[out] none
598 \retval none
599 */
timer_break_disable(uint32_t timer_periph)600 void timer_break_disable(uint32_t timer_periph)
601 {
602 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
603 }
604
605 /*!
606 \brief enable TIMER output automatic function
607 \param[in] timer_periph: TIMERx(x=0,7)
608 \param[out] none
609 \retval none
610 */
timer_automatic_output_enable(uint32_t timer_periph)611 void timer_automatic_output_enable(uint32_t timer_periph)
612 {
613 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
614 }
615
616 /*!
617 \brief disable TIMER output automatic function
618 \param[in] timer_periph: TIMERx(x=0,7)
619 \param[out] none
620 \retval none
621 */
timer_automatic_output_disable(uint32_t timer_periph)622 void timer_automatic_output_disable(uint32_t timer_periph)
623 {
624 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
625 }
626
627 /*!
628 \brief configure TIMER primary output function
629 \param[in] timer_periph: TIMERx(x=0,7)
630 \param[in] newvalue: ENABLE or DISABLE
631 \param[out] none
632 \retval none
633 */
timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)634 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
635 {
636 if(ENABLE == newvalue){
637 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
638 }else{
639 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
640 }
641 }
642
643 /*!
644 \brief enable or disable channel capture/compare control shadow register
645 \param[in] timer_periph: TIMERx(x=0,7)
646 \param[in] newvalue: ENABLE or DISABLE
647 \param[out] none
648 \retval none
649 */
timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue)650 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
651 {
652 if(ENABLE == newvalue){
653 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
654 }else{
655 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
656 }
657 }
658
659 /*!
660 \brief configure TIMER channel control shadow register update control
661 \param[in] timer_periph: TIMERx(x=0,7)
662 \param[in] ccuctl: channel control shadow register update control
663 only one parameter can be selected which is shown as below:
664 \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
665 \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
666 \param[out] none
667 \retval none
668 */
timer_channel_control_shadow_update_config(uint32_t timer_periph,uint32_t ccuctl)669 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl)
670 {
671 if(TIMER_UPDATECTL_CCU == ccuctl){
672 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
673 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
674 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
675 }else{
676 /* illegal parameters */
677 }
678 }
679
680 /*!
681 \brief initialize TIMER channel output parameter struct with a default value
682 \param[in] ocpara: TIMER channel n output parameter struct
683 \param[out] none
684 \retval none
685 */
timer_channel_output_struct_para_init(timer_oc_parameter_struct * ocpara)686 void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
687 {
688 /* initialize the channel output parameter struct member with the default value */
689 ocpara->outputstate = TIMER_CCX_DISABLE;
690 ocpara->outputnstate = TIMER_CCXN_DISABLE;
691 ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH;
692 ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH;
693 ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW;
694 ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
695 }
696
697 /*!
698 \brief configure TIMER channel output function
699 \param[in] timer_periph: please refer to the following parameters
700 \param[in] channel:
701 only one parameter can be selected which is shown as below:
702 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13))
703 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11))
704 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7))
705 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7))
706 \param[in] ocpara: TIMER channeln output parameter struct
707 outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE
708 outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE
709 ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW
710 ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW
711 ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH
712 ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
713 \param[out] none
714 \retval none
715 */
timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct * ocpara)716 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
717 {
718 switch(channel){
719 /* configure TIMER_CH_0 */
720 case TIMER_CH_0:
721 /* reset the CH0EN bit */
722 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
723 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
724 /* set the CH0EN bit */
725 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
726 /* reset the CH0P bit */
727 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
728 /* set the CH0P bit */
729 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
730
731 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
732 /* reset the CH0NEN bit */
733 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
734 /* set the CH0NEN bit */
735 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
736 /* reset the CH0NP bit */
737 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
738 /* set the CH0NP bit */
739 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
740 /* reset the ISO0 bit */
741 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
742 /* set the ISO0 bit */
743 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
744 /* reset the ISO0N bit */
745 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
746 /* set the ISO0N bit */
747 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
748 }
749 break;
750 /* configure TIMER_CH_1 */
751 case TIMER_CH_1:
752 /* reset the CH1EN bit */
753 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
754 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
755 /* set the CH1EN bit */
756 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U);
757 /* reset the CH1P bit */
758 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
759 /* set the CH1P bit */
760 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
761
762 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
763 /* reset the CH1NEN bit */
764 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
765 /* set the CH1NEN bit */
766 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
767 /* reset the CH1NP bit */
768 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
769 /* set the CH1NP bit */
770 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
771 /* reset the ISO1 bit */
772 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
773 /* set the ISO1 bit */
774 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
775 /* reset the ISO1N bit */
776 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
777 /* set the ISO1N bit */
778 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
779 }
780 break;
781 /* configure TIMER_CH_2 */
782 case TIMER_CH_2:
783 /* reset the CH2EN bit */
784 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
785 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
786 /* set the CH2EN bit */
787 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U);
788 /* reset the CH2P bit */
789 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
790 /* set the CH2P bit */
791 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
792
793 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
794 /* reset the CH2NEN bit */
795 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
796 /* set the CH2NEN bit */
797 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
798 /* reset the CH2NP bit */
799 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
800 /* set the CH2NP bit */
801 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
802 /* reset the ISO2 bit */
803 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
804 /* set the ISO2 bit */
805 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
806 /* reset the ISO2N bit */
807 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
808 /* set the ISO2N bit */
809 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
810 }
811 break;
812 /* configure TIMER_CH_3 */
813 case TIMER_CH_3:
814 /* reset the CH3EN bit */
815 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
816 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
817 /* set the CH3EN bit */
818 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U);
819 /* reset the CH3P bit */
820 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
821 /* set the CH3P bit */
822 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
823
824 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
825 /* reset the ISO3 bit */
826 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
827 /* set the ISO3 bit */
828 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
829 }
830 break;
831 default:
832 break;
833 }
834 }
835
836 /*!
837 \brief configure TIMER channel output compare mode
838 \param[in] timer_periph: please refer to the following parameters
839 \param[in] channel:
840 only one parameter can be selected which is shown as below:
841 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
842 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
843 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
844 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
845 \param[in] ocmode: channel output compare mode
846 only one parameter can be selected which is shown as below:
847 \arg TIMER_OC_MODE_TIMING: timing mode
848 \arg TIMER_OC_MODE_ACTIVE: active mode
849 \arg TIMER_OC_MODE_INACTIVE: inactive mode
850 \arg TIMER_OC_MODE_TOGGLE: toggle mode
851 \arg TIMER_OC_MODE_LOW: force low mode
852 \arg TIMER_OC_MODE_HIGH: force high mode
853 \arg TIMER_OC_MODE_PWM0: PWM0 mode
854 \arg TIMER_OC_MODE_PWM1: PWM1 mode
855 \param[out] none
856 \retval none
857 */
timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode)858 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
859 {
860 switch(channel){
861 /* configure TIMER_CH_0 */
862 case TIMER_CH_0:
863 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
864 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
865 break;
866 /* configure TIMER_CH_1 */
867 case TIMER_CH_1:
868 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
869 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
870 break;
871 /* configure TIMER_CH_2 */
872 case TIMER_CH_2:
873 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
874 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
875 break;
876 /* configure TIMER_CH_3 */
877 case TIMER_CH_3:
878 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
879 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
880 break;
881 default:
882 break;
883 }
884 }
885
886 /*!
887 \brief configure TIMER channel output pulse value
888 \param[in] timer_periph: please refer to the following parameters
889 \param[in] channel:
890 only one parameter can be selected which is shown as below:
891 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
892 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
893 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
894 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
895 \param[in] pulse: channel output pulse value
896 \param[out] none
897 \retval none
898 */
timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse)899 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
900 {
901 switch(channel){
902 /* configure TIMER_CH_0 */
903 case TIMER_CH_0:
904 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
905 break;
906 /* configure TIMER_CH_1 */
907 case TIMER_CH_1:
908 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
909 break;
910 /* configure TIMER_CH_2 */
911 case TIMER_CH_2:
912 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
913 break;
914 /* configure TIMER_CH_3 */
915 case TIMER_CH_3:
916 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
917 break;
918 default:
919 break;
920 }
921 }
922
923 /*!
924 \brief configure TIMER channel output shadow function
925 \param[in] timer_periph: please refer to the following parameters
926 \param[in] channel:
927 only one parameter can be selected which is shown as below:
928 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
929 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
930 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
931 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
932 \param[in] ocshadow: channel output shadow state
933 only one parameter can be selected which is shown as below:
934 \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
935 \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
936 \param[out] none
937 \retval none
938 */
timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow)939 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
940 {
941 switch(channel){
942 /* configure TIMER_CH_0 */
943 case TIMER_CH_0:
944 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
945 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
946 break;
947 /* configure TIMER_CH_1 */
948 case TIMER_CH_1:
949 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
950 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
951 break;
952 /* configure TIMER_CH_2 */
953 case TIMER_CH_2:
954 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
955 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
956 break;
957 /* configure TIMER_CH_3 */
958 case TIMER_CH_3:
959 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
960 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
961 break;
962 default:
963 break;
964 }
965 }
966
967 /*!
968 \brief configure TIMER channel output fast function
969 \param[in] timer_periph: please refer to the following parameters
970 \param[in] channel:
971 only one parameter can be selected which is shown as below:
972 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
973 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
974 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
975 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
976 \param[in] ocfast: channel output fast function
977 only one parameter can be selected which is shown as below:
978 \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
979 \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
980 \param[out] none
981 \retval none
982 */
timer_channel_output_fast_config(uint32_t timer_periph,uint16_t channel,uint16_t ocfast)983 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
984 {
985 switch(channel){
986 /* configure TIMER_CH_0 */
987 case TIMER_CH_0:
988 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
989 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
990 break;
991 /* configure TIMER_CH_1 */
992 case TIMER_CH_1:
993 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
994 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
995 break;
996 /* configure TIMER_CH_2 */
997 case TIMER_CH_2:
998 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
999 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1000 break;
1001 /* configure TIMER_CH_3 */
1002 case TIMER_CH_3:
1003 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1004 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1005 break;
1006 default:
1007 break;
1008 }
1009 }
1010
1011 /*!
1012 \brief configure TIMER channel output clear function
1013 \param[in] timer_periph: TIMERx(x=0..4,7)
1014 \param[in] channel:
1015 only one parameter can be selected which is shown as below:
1016 \arg TIMER_CH_0: TIMER channel0
1017 \arg TIMER_CH_1: TIMER channel1
1018 \arg TIMER_CH_2: TIMER channel2
1019 \arg TIMER_CH_3: TIMER channel3
1020 \param[in] occlear: channel output clear function
1021 only one parameter can be selected which is shown as below:
1022 \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
1023 \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
1024 \param[out] none
1025 \retval none
1026 */
timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear)1027 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
1028 {
1029 switch(channel){
1030 /* configure TIMER_CH_0 */
1031 case TIMER_CH_0:
1032 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1033 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1034 break;
1035 /* configure TIMER_CH_1 */
1036 case TIMER_CH_1:
1037 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1038 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1039 break;
1040 /* configure TIMER_CH_2 */
1041 case TIMER_CH_2:
1042 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1043 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1044 break;
1045 /* configure TIMER_CH_3 */
1046 case TIMER_CH_3:
1047 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1048 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1049 break;
1050 default:
1051 break;
1052 }
1053 }
1054
1055 /*!
1056 \brief configure TIMER channel output polarity
1057 \param[in] timer_periph: please refer to the following parameters
1058 \param[in] channel:
1059 only one parameter can be selected which is shown as below:
1060 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1061 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1062 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1063 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1064 \param[in] ocpolarity: channel output polarity
1065 only one parameter can be selected which is shown as below:
1066 \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
1067 \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
1068 \param[out] none
1069 \retval none
1070 */
timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity)1071 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1072 {
1073 switch(channel){
1074 /* configure TIMER_CH_0 */
1075 case TIMER_CH_0:
1076 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1077 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1078 break;
1079 /* configure TIMER_CH_1 */
1080 case TIMER_CH_1:
1081 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1082 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1083 break;
1084 /* configure TIMER_CH_2 */
1085 case TIMER_CH_2:
1086 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1087 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1088 break;
1089 /* configure TIMER_CH_3 */
1090 case TIMER_CH_3:
1091 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1092 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1093 break;
1094 default:
1095 break;
1096 }
1097 }
1098
1099 /*!
1100 \brief configure TIMER channel complementary output polarity
1101 \param[in] timer_periph: please refer to the following parameters
1102 \param[in] channel:
1103 only one parameter can be selected which is shown as below:
1104 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7..13))
1105 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7,8,11))
1106 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7))
1107 \param[in] ocnpolarity: channel complementary output polarity
1108 only one parameter can be selected which is shown as below:
1109 \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
1110 \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
1111 \param[out] none
1112 \retval none
1113 */
timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity)1114 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1115 {
1116 switch(channel){
1117 /* configure TIMER_CH_0 */
1118 case TIMER_CH_0:
1119 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1120 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1121 break;
1122 /* configure TIMER_CH_1 */
1123 case TIMER_CH_1:
1124 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1125 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1126 break;
1127 /* configure TIMER_CH_2 */
1128 case TIMER_CH_2:
1129 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1130 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1131 break;
1132 default:
1133 break;
1134 }
1135 }
1136
1137 /*!
1138 \brief configure TIMER channel enable state
1139 \param[in] timer_periph: please refer to the following parameters
1140 \param[in] channel:
1141 only one parameter can be selected which is shown as below:
1142 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1143 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1144 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1145 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1146 \param[in] state: TIMER channel enable state
1147 only one parameter can be selected which is shown as below:
1148 \arg TIMER_CCX_ENABLE: channel enable
1149 \arg TIMER_CCX_DISABLE: channel disable
1150 \param[out] none
1151 \retval none
1152 */
timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state)1153 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1154 {
1155 switch(channel){
1156 /* configure TIMER_CH_0 */
1157 case TIMER_CH_0:
1158 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1159 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1160 break;
1161 /* configure TIMER_CH_1 */
1162 case TIMER_CH_1:
1163 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1164 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1165 break;
1166 /* configure TIMER_CH_2 */
1167 case TIMER_CH_2:
1168 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1169 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1170 break;
1171 /* configure TIMER_CH_3 */
1172 case TIMER_CH_3:
1173 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1174 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1175 break;
1176 default:
1177 break;
1178 }
1179 }
1180
1181 /*!
1182 \brief configure TIMER channel complementary output enable state
1183 \param[in] timer_periph: please refer to the following parameters
1184 \param[in] channel:
1185 only one parameter can be selected which is shown as below:
1186 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7))
1187 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7))
1188 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7))
1189 \param[in] ocnstate: TIMER channel complementary output enable state
1190 only one parameter can be selected which is shown as below:
1191 \arg TIMER_CCXN_ENABLE: channel complementary enable
1192 \arg TIMER_CCXN_DISABLE: channel complementary disable
1193 \param[out] none
1194 \retval none
1195 */
timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate)1196 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1197 {
1198 switch(channel){
1199 /* configure TIMER_CH_0 */
1200 case TIMER_CH_0:
1201 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1202 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1203 break;
1204 /* configure TIMER_CH_1 */
1205 case TIMER_CH_1:
1206 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1207 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1208 break;
1209 /* configure TIMER_CH_2 */
1210 case TIMER_CH_2:
1211 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1212 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1213 break;
1214 default:
1215 break;
1216 }
1217 }
1218
1219 /*!
1220 \brief initialize TIMER channel input parameter struct with a default value
1221 \param[in] icpara: TIMER channel intput parameter struct
1222 \param[out] none
1223 \retval none
1224 */
timer_channel_input_struct_para_init(timer_ic_parameter_struct * icpara)1225 void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
1226 {
1227 /* initialize the channel input parameter struct member with the default value */
1228 icpara->icpolarity = TIMER_IC_POLARITY_RISING;
1229 icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
1230 icpara->icprescaler = TIMER_IC_PSC_DIV1;
1231 icpara->icfilter = 0U;
1232 }
1233
1234 /*!
1235 \brief configure TIMER input capture parameter
1236 \param[in] timer_periph: please refer to the following parameters
1237 \param[in] channel:
1238 only one parameter can be selected which is shown as below:
1239 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1240 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1241 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1242 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1243 \param[in] icpara: TIMER channel intput parameter struct
1244 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE
1245 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS
1246 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
1247 icfilter: 0~15
1248 \param[out] none
1249 \retval none
1250 */
timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpara)1251 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara)
1252 {
1253 switch(channel){
1254 /* configure TIMER_CH_0 */
1255 case TIMER_CH_0:
1256 /* reset the CH0EN bit */
1257 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1258
1259 /* reset the CH0P and CH0NP bits */
1260 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1261 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1262 /* reset the CH0MS bit */
1263 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1264 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1265 /* reset the CH0CAPFLT bit */
1266 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1267 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1268
1269 /* set the CH0EN bit */
1270 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1271 break;
1272
1273 /* configure TIMER_CH_1 */
1274 case TIMER_CH_1:
1275 /* reset the CH1EN bit */
1276 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1277
1278 /* reset the CH1P and CH1NP bits */
1279 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1280 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1281 /* reset the CH1MS bit */
1282 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1283 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1284 /* reset the CH1CAPFLT bit */
1285 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1286 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1287
1288 /* set the CH1EN bit */
1289 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1290 break;
1291 /* configure TIMER_CH_2 */
1292 case TIMER_CH_2:
1293 /* reset the CH2EN bit */
1294 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1295
1296 /* reset the CH2P and CH2NP bits */
1297 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP));
1298 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1299
1300 /* reset the CH2MS bit */
1301 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1302 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1303
1304 /* reset the CH2CAPFLT bit */
1305 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1306 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1307
1308 /* set the CH2EN bit */
1309 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1310 break;
1311 /* configure TIMER_CH_3 */
1312 case TIMER_CH_3:
1313 /* reset the CH3EN bit */
1314 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1315
1316 /* reset the CH3P and CH3NP bits */
1317 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP));
1318 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1319
1320 /* reset the CH3MS bit */
1321 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1322 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1323
1324 /* reset the CH3CAPFLT bit */
1325 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1326 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1327
1328 /* set the CH3EN bit */
1329 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1330 break;
1331 default:
1332 break;
1333 }
1334 /* configure TIMER channel input capture prescaler value */
1335 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1336 }
1337
1338 /*!
1339 \brief configure TIMER channel input capture prescaler value
1340 \param[in] timer_periph: please refer to the following parameters
1341 \param[in] channel:
1342 only one parameter can be selected which is shown as below:
1343 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1344 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1345 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1346 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1347 \param[in] prescaler: channel input capture prescaler value
1348 only one parameter can be selected which is shown as below:
1349 \arg TIMER_IC_PSC_DIV1: no prescaler
1350 \arg TIMER_IC_PSC_DIV2: divided by 2
1351 \arg TIMER_IC_PSC_DIV4: divided by 4
1352 \arg TIMER_IC_PSC_DIV8: divided by 8
1353 \param[out] none
1354 \retval none
1355 */
timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler)1356 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1357 {
1358 switch(channel){
1359 /* configure TIMER_CH_0 */
1360 case TIMER_CH_0:
1361 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1362 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1363 break;
1364 /* configure TIMER_CH_1 */
1365 case TIMER_CH_1:
1366 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1367 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1368 break;
1369 /* configure TIMER_CH_2 */
1370 case TIMER_CH_2:
1371 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1372 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1373 break;
1374 /* configure TIMER_CH_3 */
1375 case TIMER_CH_3:
1376 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1377 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1378 break;
1379 default:
1380 break;
1381 }
1382 }
1383
1384 /*!
1385 \brief read TIMER channel capture compare register value
1386 \param[in] timer_periph: please refer to the following parameters
1387 \param[in] channel:
1388 only one parameter can be selected which is shown as below:
1389 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1390 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1391 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1392 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1393 \param[out] none
1394 \retval channel capture compare register value
1395 */
timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel)1396 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1397 {
1398 uint32_t count_value = 0U;
1399
1400 switch(channel){
1401 /* read TIMER channel 0 capture compare register value */
1402 case TIMER_CH_0:
1403 count_value = TIMER_CH0CV(timer_periph);
1404 break;
1405 /* read TIMER channel 1 capture compare register value */
1406 case TIMER_CH_1:
1407 count_value = TIMER_CH1CV(timer_periph);
1408 break;
1409 /* read TIMER channel 2 capture compare register value */
1410 case TIMER_CH_2:
1411 count_value = TIMER_CH2CV(timer_periph);
1412 break;
1413 /* read TIMER channel 3 capture compare register value */
1414 case TIMER_CH_3:
1415 count_value = TIMER_CH3CV(timer_periph);
1416 break;
1417 default:
1418 break;
1419 }
1420 return (count_value);
1421 }
1422
1423 /*!
1424 \brief configure TIMER input pwm capture function
1425 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1426 \param[in] channel:
1427 only one parameter can be selected which is shown as below:
1428 \arg TIMER_CH_0: TIMER channel0
1429 \arg TIMER_CH_1: TIMER channel1
1430 \param[in] icpwm:TIMER channel intput pwm parameter struct
1431 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
1432 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI
1433 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
1434 icfilter: 0~15
1435 \param[out] none
1436 \retval none
1437 */
timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpwm)1438 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
1439 {
1440 uint16_t icpolarity = 0x0U;
1441 uint16_t icselection = 0x0U;
1442
1443 /* Set channel input polarity */
1444 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1445 icpolarity = TIMER_IC_POLARITY_FALLING;
1446 }else{
1447 icpolarity = TIMER_IC_POLARITY_RISING;
1448 }
1449 /* Set channel input mode selection */
1450 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1451 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1452 }else{
1453 icselection = TIMER_IC_SELECTION_DIRECTTI;
1454 }
1455
1456 if(TIMER_CH_0 == channel){
1457 /* reset the CH0EN bit */
1458 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1459 /* reset the CH0P and CH0NP bits */
1460 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1461 /* set the CH0P and CH0NP bits */
1462 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1463 /* reset the CH0MS bit */
1464 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1465 /* set the CH0MS bit */
1466 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1467 /* reset the CH0CAPFLT bit */
1468 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1469 /* set the CH0CAPFLT bit */
1470 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1471 /* set the CH0EN bit */
1472 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1473 /* configure TIMER channel input capture prescaler value */
1474 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1475
1476 /* reset the CH1EN bit */
1477 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1478 /* reset the CH1P and CH1NP bits */
1479 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1480 /* set the CH1P and CH1NP bits */
1481 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
1482 /* reset the CH1MS bit */
1483 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1484 /* set the CH1MS bit */
1485 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1486 /* reset the CH1CAPFLT bit */
1487 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1488 /* set the CH1CAPFLT bit */
1489 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1490 /* set the CH1EN bit */
1491 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1492 /* configure TIMER channel input capture prescaler value */
1493 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1494 }else{
1495 /* reset the CH1EN bit */
1496 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1497 /* reset the CH1P and CH1NP bits */
1498 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1499 /* set the CH1P and CH1NP bits */
1500 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1501 /* reset the CH1MS bit */
1502 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1503 /* set the CH1MS bit */
1504 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1505 /* reset the CH1CAPFLT bit */
1506 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1507 /* set the CH1CAPFLT bit */
1508 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1509 /* set the CH1EN bit */
1510 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1511 /* configure TIMER channel input capture prescaler value */
1512 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1513
1514 /* reset the CH0EN bit */
1515 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1516 /* reset the CH0P and CH0NP bits */
1517 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1518 /* set the CH0P and CH0NP bits */
1519 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1520 /* reset the CH0MS bit */
1521 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1522 /* set the CH0MS bit */
1523 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1524 /* reset the CH0CAPFLT bit */
1525 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1526 /* set the CH0CAPFLT bit */
1527 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1528 /* set the CH0EN bit */
1529 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1530 /* configure TIMER channel input capture prescaler value */
1531 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1532 }
1533 }
1534
1535 /*!
1536 \brief configure TIMER hall sensor mode
1537 \param[in] timer_periph: TIMERx(x=0..4,7)
1538 \param[in] hallmode:
1539 only one parameter can be selected which is shown as below:
1540 \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
1541 \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
1542 \param[out] none
1543 \retval none
1544 */
timer_hall_mode_config(uint32_t timer_periph,uint32_t hallmode)1545 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
1546 {
1547 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1548 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1549 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1550 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1551 }else{
1552 /* illegal parameters */
1553 }
1554 }
1555
1556 /*!
1557 \brief select TIMER input trigger source
1558 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1559 \param[in] intrigger:
1560 only one parameter can be selected which is shown as below:
1561 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
1562 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
1563 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
1564 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
1565 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
1566 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
1567 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
1568 \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(x=0..4,7)
1569 \param[out] none
1570 \retval none
1571 */
timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)1572 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
1573 {
1574 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1575 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1576 }
1577
1578 /*!
1579 \brief select TIMER master mode output trigger source
1580 \param[in] timer_periph: TIMERx(x=0..7)
1581 \param[in] outrigger:
1582 only one parameter can be selected which is shown as below:
1583 \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output
1584 \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output
1585 \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output
1586 \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO
1587 \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output
1588 \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output
1589 \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output
1590 \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output
1591 \param[out] none
1592 \retval none
1593 */
timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger)1594 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
1595 {
1596 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1597 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1598 }
1599
1600 /*!
1601 \brief select TIMER slave mode
1602 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1603 \param[in] slavemode:
1604 only one parameter can be selected which is shown as below:
1605 \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable
1606 \arg TIMER_ENCODER_MODE0: encoder mode 0
1607 \arg TIMER_ENCODER_MODE1: encoder mode 1
1608 \arg TIMER_ENCODER_MODE2: encoder mode 2
1609 \arg TIMER_SLAVE_MODE_RESTART: restart mode
1610 \arg TIMER_SLAVE_MODE_PAUSE: pause mode
1611 \arg TIMER_SLAVE_MODE_EVENT: event mode
1612 \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0
1613 \param[out] none
1614 \retval none
1615 */
1616
timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)1617 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
1618 {
1619 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1620 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1621 }
1622
1623 /*!
1624 \brief configure TIMER master slave mode
1625 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1626 \param[in] masterslave:
1627 only one parameter can be selected which is shown as below:
1628 \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
1629 \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
1630 \param[out] none
1631 \retval none
1632 */
timer_master_slave_mode_config(uint32_t timer_periph,uint32_t masterslave)1633 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
1634 {
1635 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1636 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1637 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1638 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1639 }else{
1640 /* illegal parameters */
1641 }
1642 }
1643
1644 /*!
1645 \brief configure TIMER external trigger input
1646 \param[in] timer_periph: TIMERx(x=0..4,7)
1647 \param[in] extprescaler:
1648 only one parameter can be selected which is shown as below:
1649 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1650 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1651 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1652 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1653 \param[in] extpolarity:
1654 only one parameter can be selected which is shown as below:
1655 \arg TIMER_ETP_FALLING: active low or falling edge active
1656 \arg TIMER_ETP_RISING: active high or rising edge active
1657 \param[in] extfilter: a value between 0 and 15
1658 \param[out] none
1659 \retval none
1660 */
timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1661 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1662 {
1663 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1664 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
1665 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1666 }
1667
1668 /*!
1669 \brief configure TIMER quadrature decoder mode
1670 \param[in] timer_periph: TIMERx(x=0..4,7)
1671 \param[in] decomode:
1672 only one parameter can be selected which is shown as below:
1673 \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
1674 \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
1675 \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
1676 \param[in] ic0polarity:
1677 only one parameter can be selected which is shown as below:
1678 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1679 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1680 \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge
1681 \param[in] ic1polarity:
1682 only one parameter can be selected which is shown as below:
1683 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1684 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1685 \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge
1686 \param[out] none
1687 \retval none
1688 */
timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode,uint16_t ic0polarity,uint16_t ic1polarity)1689 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
1690 {
1691 /* configure the quadrature decoder mode */
1692 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1693 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1694 /* configure input capture selection */
1695 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1696 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1697 /* configure channel input capture polarity */
1698 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1699 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1700 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U));
1701 }
1702
1703 /*!
1704 \brief configure TIMER internal clock mode
1705 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1706 \param[out] none
1707 \retval none
1708 */
timer_internal_clock_config(uint32_t timer_periph)1709 void timer_internal_clock_config(uint32_t timer_periph)
1710 {
1711 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1712 }
1713
1714 /*!
1715 \brief configure TIMER the internal trigger as external clock input
1716 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1717 \param[in] intrigger:
1718 only one parameter can be selected which is shown as below:
1719 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
1720 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
1721 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
1722 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
1723 \param[out] none
1724 \retval none
1725 */
timer_internal_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t intrigger)1726 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
1727 {
1728 timer_input_trigger_source_select(timer_periph, intrigger);
1729 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1730 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1731 }
1732
1733 /*!
1734 \brief configure TIMER the external trigger as external clock input
1735 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1736 \param[in] extrigger:
1737 only one parameter can be selected which is shown as below:
1738 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
1739 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
1740 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
1741 \param[in] extpolarity:
1742 only one parameter can be selected which is shown as below:
1743 \arg TIMER_IC_POLARITY_RISING: active high or rising edge active
1744 \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active
1745 \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge
1746 \param[in] extfilter: a value between 0 and 15
1747 \param[out] none
1748 \retval none
1749 */
timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger,uint16_t extpolarity,uint32_t extfilter)1750 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter)
1751 {
1752 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1753 /* reset the CH1EN bit */
1754 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1755 /* reset the CH1NP bit */
1756 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1757 /* set the CH1NP bit */
1758 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
1759 /* reset the CH1MS bit */
1760 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1761 /* set the CH1MS bit */
1762 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1763 /* reset the CH1CAPFLT bit */
1764 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1765 /* set the CH1CAPFLT bit */
1766 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
1767 /* set the CH1EN bit */
1768 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1769 }else{
1770 /* reset the CH0EN bit */
1771 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1772 /* reset the CH0P and CH0NP bits */
1773 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1774 /* set the CH0P and CH0NP bits */
1775 TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
1776 /* reset the CH0MS bit */
1777 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1778 /* set the CH0MS bit */
1779 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1780 /* reset the CH0CAPFLT bit */
1781 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1782 /* reset the CH0CAPFLT bit */
1783 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
1784 /* set the CH0EN bit */
1785 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1786 }
1787 /* select TIMER input trigger source */
1788 timer_input_trigger_source_select(timer_periph, extrigger);
1789 /* reset the SMC bit */
1790 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1791 /* set the SMC bit */
1792 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1793 }
1794
1795 /*!
1796 \brief configure TIMER the external clock mode0
1797 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1798 \param[in] extprescaler:
1799 only one parameter can be selected which is shown as below:
1800 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1801 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1802 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1803 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1804 \param[in] extpolarity:
1805 only one parameter can be selected which is shown as below:
1806 \arg TIMER_ETP_FALLING: active low or falling edge active
1807 \arg TIMER_ETP_RISING: active high or rising edge active
1808 \param[in] extfilter: a value between 0 and 15
1809 \param[out] none
1810 \retval none
1811 */
timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1812 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1813 {
1814 /* configure TIMER external trigger input */
1815 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1816
1817 /* reset the SMC bit,TRGS bit */
1818 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1819 /* set the SMC bit,TRGS bit */
1820 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1821 }
1822
1823 /*!
1824 \brief configure TIMER the external clock mode1
1825 \param[in] timer_periph: TIMERx(x=0..4,7)
1826 \param[in] extprescaler:
1827 only one parameter can be selected which is shown as below:
1828 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1829 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1830 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1831 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1832 \param[in] extpolarity:
1833 only one parameter can be selected which is shown as below:
1834 \arg TIMER_ETP_FALLING: active low or falling edge active
1835 \arg TIMER_ETP_RISING: active high or rising edge active
1836 \param[in] extfilter: a value between 0 and 15
1837 \param[out] none
1838 \retval none
1839 */
timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1840 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1841 {
1842 /* configure TIMER external trigger input */
1843 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1844
1845 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1846 }
1847
1848 /*!
1849 \brief disable TIMER the external clock mode1
1850 \param[in] timer_periph: TIMERx(x=0..4,7)
1851 \param[out] none
1852 \retval none
1853 */
timer_external_clock_mode1_disable(uint32_t timer_periph)1854 void timer_external_clock_mode1_disable(uint32_t timer_periph)
1855 {
1856 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1857 }
1858
1859 /*!
1860 \brief configure TIMER write CHxVAL register selection
1861 \param[in] timer_periph: TIMERx(x=0..4,7..13)
1862 \param[in] ccsel:
1863 only one parameter can be selected which is shown as below:
1864 \arg TIMER_CHVSEL_DISABLE: no effect
1865 \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored
1866 \param[out] none
1867 \retval none
1868 */
timer_write_chxval_register_config(uint32_t timer_periph,uint16_t ccsel)1869 void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel)
1870 {
1871 if(TIMER_CHVSEL_ENABLE == ccsel){
1872 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
1873 }else if(TIMER_CHVSEL_DISABLE == ccsel){
1874 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
1875 }else{
1876 /* illegal parameters */
1877 }
1878 }
1879
1880 /*!
1881 \brief configure TIMER output value selection
1882 \param[in] timer_periph: TIMERx(x=0,7)
1883 \param[in] outsel:
1884 only one parameter can be selected which is shown as below:
1885 \arg TIMER_OUTSEL_DISABLE: no effect
1886 \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled
1887 \param[out] none
1888 \retval none
1889 */
timer_output_value_selection_config(uint32_t timer_periph,uint16_t outsel)1890 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
1891 {
1892 if(TIMER_OUTSEL_ENABLE == outsel){
1893 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
1894 }else if(TIMER_OUTSEL_DISABLE == outsel){
1895 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
1896 }else{
1897 /* illegal parameters */
1898 }
1899 }
1900 /*!
1901 \brief get TIMER flags
1902 \param[in] timer_periph: please refer to the following parameters
1903 \param[in] flag: the timer interrupt flags
1904 only one parameter can be selected which is shown as below:
1905 \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
1906 \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
1907 \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
1908 \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
1909 \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
1910 \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
1911 \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
1912 \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
1913 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
1914 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
1915 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
1916 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
1917 \param[out] none
1918 \retval FlagStatus: SET or RESET
1919 */
timer_flag_get(uint32_t timer_periph,uint32_t flag)1920 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
1921 {
1922 if(RESET != (TIMER_INTF(timer_periph) & flag)){
1923 return SET;
1924 }else{
1925 return RESET;
1926 }
1927 }
1928
1929 /*!
1930 \brief clear TIMER flags
1931 \param[in] timer_periph: please refer to the following parameters
1932 \param[in] flag: the timer interrupt flags
1933 only one parameter can be selected which is shown as below:
1934 \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
1935 \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
1936 \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
1937 \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
1938 \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
1939 \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
1940 \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
1941 \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
1942 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
1943 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
1944 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
1945 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
1946 \param[out] none
1947 \retval none
1948 */
timer_flag_clear(uint32_t timer_periph,uint32_t flag)1949 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
1950 {
1951 TIMER_INTF(timer_periph) = (~(uint32_t)flag);
1952 }
1953 /*!
1954 \brief enable the TIMER interrupt
1955 \param[in] timer_periph: please refer to the following parameters
1956 \param[in] interrupt: timer interrupt enable source
1957 only one parameter can be selected which is shown as below:
1958 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
1959 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
1960 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
1961 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
1962 \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
1963 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
1964 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
1965 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
1966 \param[out] none
1967 \retval none
1968 */
timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt)1969 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
1970 {
1971 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
1972 }
1973
1974 /*!
1975 \brief disable the TIMER interrupt
1976 \param[in] timer_periph: please refer to the following parameters
1977 \param[in] interrupt: timer interrupt source disable
1978 only one parameter can be selected which is shown as below:
1979 \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..13)
1980 \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..4,7..13)
1981 \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..4,7,8,11)
1982 \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..4,7)
1983 \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..4,7)
1984 \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,7)
1985 \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..4,7,8,11)
1986 \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,7)
1987 \param[out] none
1988 \retval none
1989 */
timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt)1990 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
1991 {
1992 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
1993 }
1994
1995 /*!
1996 \brief get timer interrupt flag
1997 \param[in] timer_periph: please refer to the following parameters
1998 \param[in] int_flag: the timer interrupt bits
1999 only one parameter can be selected which is shown as below:
2000 \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
2001 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
2002 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
2003 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
2004 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
2005 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
2006 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
2007 \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
2008 \param[out] none
2009 \retval FlagStatus: SET or RESET
2010 */
timer_interrupt_flag_get(uint32_t timer_periph,uint32_t int_flag)2011 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag)
2012 {
2013 uint32_t val;
2014 val = (TIMER_DMAINTEN(timer_periph) & int_flag);
2015 if((RESET != (TIMER_INTF(timer_periph) & int_flag) ) && (RESET != val)){
2016 return SET;
2017 }else{
2018 return RESET;
2019 }
2020 }
2021
2022 /*!
2023 \brief clear TIMER interrupt flag
2024 \param[in] timer_periph: please refer to the following parameters
2025 \param[in] int_flag: the timer interrupt bits
2026 only one parameter can be selected which is shown as below:
2027 \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
2028 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
2029 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
2030 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
2031 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
2032 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
2033 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
2034 \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
2035 \param[out] none
2036 \retval none
2037 */
timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t int_flag)2038 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag)
2039 {
2040 TIMER_INTF(timer_periph) = (~(uint32_t)int_flag);
2041 }
2042
