1 /*!
2 \file gd32a50x_timer.c
3 \brief TIMER driver
4
5 \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7
8 /*
9 Copyright (c) 2022, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32a50x_timer.h"
36
37 /* TIMER init parameter mask */
38 #define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */
39 #define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */
40 #define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */
41
42 /*!
43 \brief deinit a TIMER
44 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
45 \param[out] none
46 \retval none
47 */
timer_deinit(uint32_t timer_periph)48 void timer_deinit(uint32_t timer_periph)
49 {
50 switch(timer_periph) {
51 case TIMER0:
52 /* reset TIMER0 */
53 rcu_periph_reset_enable(RCU_TIMER0RST);
54 rcu_periph_reset_disable(RCU_TIMER0RST);
55 break;
56 case TIMER1:
57 /* reset TIMER1 */
58 rcu_periph_reset_enable(RCU_TIMER1RST);
59 rcu_periph_reset_disable(RCU_TIMER1RST);
60 break;
61 case TIMER5:
62 /* reset TIMER5 */
63 rcu_periph_reset_enable(RCU_TIMER5RST);
64 rcu_periph_reset_disable(RCU_TIMER5RST);
65 break;
66 case TIMER6:
67 /* reset TIMER6 */
68 rcu_periph_reset_enable(RCU_TIMER6RST);
69 rcu_periph_reset_disable(RCU_TIMER6RST);
70 break;
71 case TIMER7:
72 /* reset TIMER7 */
73 rcu_periph_reset_enable(RCU_TIMER7RST);
74 rcu_periph_reset_disable(RCU_TIMER7RST);
75 break;
76 case TIMER19:
77 /* reset TIMER19 */
78 rcu_periph_reset_enable(RCU_TIMER19RST);
79 rcu_periph_reset_disable(RCU_TIMER19RST);
80 break;
81 case TIMER20:
82 /* reset TIMER20 */
83 rcu_periph_reset_enable(RCU_TIMER20RST);
84 rcu_periph_reset_disable(RCU_TIMER20RST);
85 break;
86 default:
87 break;
88 }
89 }
90
91 /*!
92 \brief initialize TIMER init parameter struct with a default value
93 \param[in] initpara: init parameter struct
94 \param[out] none
95 \retval none
96 */
timer_struct_para_init(timer_parameter_struct * initpara)97 void timer_struct_para_init(timer_parameter_struct *initpara)
98 {
99 /* initialize the init parameter struct member with the default value */
100 initpara->prescaler = 0U;
101 initpara->alignedmode = TIMER_COUNTER_EDGE;
102 initpara->counterdirection = TIMER_COUNTER_UP;
103 initpara->period = 65535U;
104 initpara->clockdivision = TIMER_CKDIV_DIV1;
105 initpara->repetitioncounter = 0U;
106 }
107
108 /*!
109 \brief initialize TIMER counter
110 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
111 \param[in] initpara: init parameter struct
112 prescaler: prescaler value of the counter clock, 0~65535
113 alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH
114 counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN
115 period: counter auto reload value, 0~65535
116 clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4
117 repetitioncounter: counter repetition value, 0~255
118 \param[out] none
119 \retval none
120 */
gd32_timer_init(uint32_t timer_periph,timer_parameter_struct * initpara)121 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct *initpara)
122 {
123 /* configure the counter prescaler value */
124 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
125
126 /* configure the counter direction and aligned mode */
127 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER7 == timer_periph)
128 || (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) {
129 TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM));
130 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK);
131 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
132 }
133
134 /* configure the autoreload value */
135 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
136
137 /* configure the clock division value */
138 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) {
139 /* reset the CKDIV bit */
140 TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV);
141 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK);
142 }
143
144 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) ||
145 (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) {
146 /* configure the repetition counter value */
147 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
148 }
149
150 /* generate an update event */
151 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
152 }
153
154 /*!
155 \brief enable a TIMER
156 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
157 \param[out] none
158 \retval none
159 */
timer_enable(uint32_t timer_periph)160 void timer_enable(uint32_t timer_periph)
161 {
162 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
163 }
164
165 /*!
166 \brief disable a TIMER
167 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
168 \param[out] none
169 \retval none
170 */
timer_disable(uint32_t timer_periph)171 void timer_disable(uint32_t timer_periph)
172 {
173 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
174 }
175
176 /*!
177 \brief enable the auto reload shadow function
178 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
179 \param[out] none
180 \retval none
181 */
timer_auto_reload_shadow_enable(uint32_t timer_periph)182 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
183 {
184 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
185 }
186
187 /*!
188 \brief disable the auto reload shadow function
189 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
190 \param[out] none
191 \retval none
192 */
timer_auto_reload_shadow_disable(uint32_t timer_periph)193 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
194 {
195 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
196 }
197
198 /*!
199 \brief enable the update event
200 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
201 \param[out] none
202 \retval none
203 */
timer_update_event_enable(uint32_t timer_periph)204 void timer_update_event_enable(uint32_t timer_periph)
205 {
206 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
207 }
208
209 /*!
210 \brief disable the update event
211 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
212 \param[out] none
213 \retval none
214 */
timer_update_event_disable(uint32_t timer_periph)215 void timer_update_event_disable(uint32_t timer_periph)
216 {
217 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
218 }
219
220 /*!
221 \brief set TIMER counter alignment mode
222 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
223 \param[in] aligned: aligned mode
224 only one parameter can be selected which is shown as below:
225 \arg TIMER_COUNTER_EDGE: edge-aligned mode
226 \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
227 \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
228 \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
229 \param[out] none
230 \retval none
231 */
timer_counter_alignment(uint32_t timer_periph,uint16_t aligned)232 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
233 {
234 TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM);
235 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
236 }
237
238 /*!
239 \brief set TIMER counter up direction
240 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
241 \param[out] none
242 \retval none
243 */
timer_counter_up_direction(uint32_t timer_periph)244 void timer_counter_up_direction(uint32_t timer_periph)
245 {
246 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
247 }
248
249 /*!
250 \brief set TIMER counter down direction
251 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
252 \param[out] none
253 \retval none
254 */
timer_counter_down_direction(uint32_t timer_periph)255 void timer_counter_down_direction(uint32_t timer_periph)
256 {
257 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
258 }
259
260 /*!
261 \brief configure TIMER prescaler
262 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
263 \param[in] prescaler: prescaler value, 0~65535
264 \param[in] pscreload: prescaler reload mode
265 only one parameter can be selected which is shown as below:
266 \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
267 \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
268 \param[out] none
269 \retval none
270 */
timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint32_t pscreload)271 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload)
272 {
273 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
274
275 if(TIMER_PSC_RELOAD_NOW == pscreload) {
276 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
277 }
278 }
279
280 /*!
281 \brief configure TIMER repetition register value
282 \param[in] timer_periph: TIMERx(x=0,7,19,20)
283 \param[in] repetition: the counter repetition value, 0~255
284 \param[out] none
285 \retval none
286 */
timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition)287 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
288 {
289 TIMER_CREP(timer_periph) = (uint32_t)repetition;
290 }
291
292 /*!
293 \brief configure TIMER autoreload register value
294 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
295 \param[in] autoreload: the counter auto-reload value, 0~65535
296 \param[out] none
297 \retval none
298 */
timer_autoreload_value_config(uint32_t timer_periph,uint16_t autoreload)299 void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
300 {
301 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
302 }
303
304 /*!
305 \brief configure TIMER counter register value
306 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
307 \param[in] counter: the counter value, 0~65535
308 \param[out] none
309 \retval none
310 */
timer_counter_value_config(uint32_t timer_periph,uint16_t counter)311 void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
312 {
313 TIMER_CNT(timer_periph) = (uint32_t)counter;
314 }
315
316 /*!
317 \brief read TIMER counter value
318 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
319 \param[out] none
320 \retval counter value, 0~65535
321 */
timer_counter_read(uint32_t timer_periph)322 uint32_t timer_counter_read(uint32_t timer_periph)
323 {
324 uint32_t count_value = 0U;
325 count_value = TIMER_CNT(timer_periph);
326 return (count_value);
327 }
328
329 /*!
330 \brief read TIMER prescaler value
331 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
332 \param[out] none
333 \retval prescaler register value, 0~65535
334 */
timer_prescaler_read(uint32_t timer_periph)335 uint16_t timer_prescaler_read(uint32_t timer_periph)
336 {
337 uint16_t prescaler_value = 0U;
338 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
339 return (prescaler_value);
340 }
341
342 /*!
343 \brief configure TIMER single pulse mode
344 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
345 \param[in] spmode: single pulse mode
346 only one parameter can be selected which is shown as below:
347 \arg TIMER_SP_MODE_SINGLE: single pulse mode
348 \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
349 \param[out] none
350 \retval none
351 */
timer_single_pulse_mode_config(uint32_t timer_periph,uint32_t spmode)352 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
353 {
354 if(TIMER_SP_MODE_SINGLE == spmode) {
355 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
356 } else if(TIMER_SP_MODE_REPETITIVE == spmode) {
357 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
358 } else {
359 /* illegal parameters */
360 }
361 }
362
363 /*!
364 \brief configure TIMER update source
365 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
366 \param[in] update: update source
367 only one parameter can be selected which is shown as below:
368 \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,
369 or the slave mode controller trigger
370 \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
371 \param[out] none
372 \retval none
373 */
timer_update_source_config(uint32_t timer_periph,uint32_t update)374 void timer_update_source_config(uint32_t timer_periph, uint32_t update)
375 {
376 if(TIMER_UPDATE_SRC_REGULAR == update) {
377 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
378 } else if(TIMER_UPDATE_SRC_GLOBAL == update) {
379 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
380 } else {
381 /* illegal parameters */
382 }
383 }
384
385 /*!
386 \brief configure channel commutation control shadow register
387 \param[in] timer_periph: TIMERx(x=0,7,19,20)
388 \param[in] newvalue: ENABLE or DISABLE
389 \param[out] none
390 \retval none
391 */
timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue)392 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
393 {
394 if(ENABLE == newvalue) {
395 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
396 } else {
397 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
398 }
399 }
400
401 /*!
402 \brief configure TIMER channel control shadow register update control
403 \param[in] timer_periph: TIMERx(x=0,7,19,20)
404 \param[in] ccuctl: channel control shadow register update control
405 only one parameter can be selected which is shown as below:
406 \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
407 \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
408 \param[out] none
409 \retval none
410 */
timer_channel_control_shadow_update_config(uint32_t timer_periph,uint32_t ccuctl)411 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl)
412 {
413 if(TIMER_UPDATECTL_CCU == ccuctl) {
414 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
415 } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) {
416 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
417 } else {
418 /* illegal parameters */
419 }
420 }
421
422 /*!
423 \brief enable the TIMER DMA
424 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
425 \param[in] dma: specify which DMA to enable
426 one or more parameters can be selected which are shown as below:
427 \arg TIMER_DMA_UPD: update DMA request, TIMERx(x=0,1,5,6,7,19,20)
428 \arg TIMER_DMA_CH0D: channel 0 DMA request , TIMERx(x=0,1,7,19,20)
429 \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,1,7,19,20)
430 \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,1,7,19,20)
431 \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,1,7,19,20)
432 \arg TIMER_DMA_CMTD: channel commutation DMA request, TIMERx(x=0,7,19,20)
433 \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0,1,7,19,20)
434 \arg TIMER_DMA_MCH0D: multi mode channel 0 DMA request, TIMERx(x=0,7,19,20)
435 \arg TIMER_DMA_MCH1D: multi mode channel 1 DMA request, TIMERx(x=0,7,19,20)
436 \arg TIMER_DMA_MCH2D: multi mode channel 2 DMA request, TIMERx(x=0,7,19,20)
437 \arg TIMER_DMA_MCH3D: multi mode channel 3 DMA request, TIMERx(x=0,7,19,20)
438 \param[out] none
439 \retval none
440 */
timer_dma_enable(uint32_t timer_periph,uint32_t dma)441 void timer_dma_enable(uint32_t timer_periph, uint32_t dma)
442 {
443 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
444 }
445
446 /*!
447 \brief disable the TIMER DMA
448 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
449 \param[in] dma: specify which DMA to disbale
450 one or more parameters can be selected which are shown as below:
451 \arg TIMER_DMA_UPD: update DMA request, TIMERx(x=0,1,5,6,7,19,20)
452 \arg TIMER_DMA_CH0D: channel 0 DMA request , TIMERx(x=0,1,7,19,20)
453 \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,1,7,19,20)
454 \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,1,7,19,20)
455 \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,1,7,19,20)
456 \arg TIMER_DMA_CMTD: channel commutation DMA request, TIMERx(x=0,7,19,20)
457 \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0,1,7,19,20)
458 \arg TIMER_DMA_MCH0D: multi mode channel 0 DMA request, TIMERx(x=0,7,19,20)
459 \arg TIMER_DMA_MCH1D: multi mode channel 1 DMA request, TIMERx(x=0,7,19,20)
460 \arg TIMER_DMA_MCH2D: multi mode channel 2 DMA request, TIMERx(x=0,7,19,20)
461 \arg TIMER_DMA_MCH3D: multi mode channel 3 DMA request, TIMERx(x=0,7,19,20)
462 \param[out] none
463 \retval none
464 */
timer_dma_disable(uint32_t timer_periph,uint32_t dma)465 void timer_dma_disable(uint32_t timer_periph, uint32_t dma)
466 {
467 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
468 }
469
470 /*!
471 \brief channel DMA request source selection
472 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
473 \param[in] dma_request: channel DMA request source selection
474 only one parameter can be selected which is shown as below:
475 \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs
476 \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs
477 \param[out] none
478 \retval none
479 */
timer_channel_dma_request_source_select(uint32_t timer_periph,uint32_t dma_request)480 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request)
481 {
482 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) {
483 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
484 } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) {
485 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
486 } else {
487 /* illegal parameters */
488 }
489 }
490
491 /*!
492 \brief configure the TIMER DMA transfer
493 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
494 \param[in] dma_baseaddr: DMA access base address
495 only one parameter can be selected which is shown as below:
496 \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0,1,7,19,20)
497 \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0,1,7,19,20)
498 \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0,1,7,19,20)
499 \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0,1,7,19,20)
500 \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0,1,7,19,20)
501 \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0,1,7,19,20)
502 \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0,1,7,19,20)
503 \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0,1,7,19,20)
504 \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0,1,7,19,20)
505 \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0,1,7,19,20)
506 \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0,1,7,19,20)
507 \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0,1,7,19,20)
508 \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,7,19,20)
509 \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0,1,7,19,20)
510 \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0,1,7,19,20)
511 \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0,1,7,19,20)
512 \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0,1,7,19,20)
513 \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,7,19,20)
514 \arg TIMER_DMACFG_DMATA_MCHCTL0: DMA transfer address is TIMER_MCHCTL0, TIMERx(x=0,7,19,20)
515 \arg TIMER_DMACFG_DMATA_MCHCTL1: DMA transfer address is TIMER_MCHCTL1, TIMERx(x=0,7,19,20)
516 \arg TIMER_DMACFG_DMATA_MCHCTL2: DMA transfer address is TIMER_MCHCTL2, TIMERx(x=0,7,19,20)
517 \arg TIMER_DMACFG_DMATA_MCH0CV: DMA transfer address is TIMER_MCH0CV, TIMERx(x=0,7,19,20)
518 \arg TIMER_DMACFG_DMATA_MCH1CV: DMA transfer address is TIMER_MCH1CV, TIMERx(x=0,7,19,20)
519 \arg TIMER_DMACFG_DMATA_MCH2CV: DMA transfer address is TIMER_MCH2CV, TIMERx(x=0,7,19,20)
520 \arg TIMER_DMACFG_DMATA_MCH3CV: DMA transfer address is TIMER_MCH3CV, TIMERx(x=0,7,19,20)
521 \arg TIMER_DMACFG_DMATA_CH0COMV_ADD: DMA transfer address is TIMER_CH0COMV_ADD, TIMERx(x=0,7,19,20)
522 \arg TIMER_DMACFG_DMATA_CH1COMV_ADD: DMA transfer address is TIMER_CH1COMV_ADD, TIMERx(x=0,7,19,20)
523 \arg TIMER_DMACFG_DMATA_CH2COMV_ADD: DMA transfer address is TIMER_CH2COMV_ADD, TIMERx(x=0,7,19,20)
524 \arg TIMER_DMACFG_DMATA_CH3COMV_ADD: DMA transfer address is TIMER_CH3COMV_ADD, TIMERx(x=0,7,19,20)
525 \arg TIMER_DMACFG_DMATA_CTL2: DMA transfer address is TIMER_CTL2, TIMERx(x=0,7,19,20)
526 \arg TIMER_DMACFG_DMATA_BRKCFG: DMA transfer address is TIMER_BRKCFG, TIMERx(x=0,7,19,20)
527 \arg TIMER_DMACFG_DMATA_FCCHP0: DMA transfer address is TIMER_FCCHP0, TIMERx(x=0,7,19,20)
528 \arg TIMER_DMACFG_DMATA_FCCHP1: DMA transfer address is TIMER_FCCHP1, TIMERx(x=0,7,19,20)
529 \arg TIMER_DMACFG_DMATA_FCCHP2: DMA transfer address is TIMER_FCCHP2, TIMERx(x=0,7,19,20)
530 \arg TIMER_DMACFG_DMATA_FCCHP3: DMA transfer address is TIMER_FCCHP3, TIMERx(x=0,7,19,20)
531 \param[in] dma_lenth: access burst length
532 only one parameter can be selected which is shown as below:
533 \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1~35): DMA transfer x time
534 \param[out] none
535 \retval none
536 */
timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth)537 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
538 {
539 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
540 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
541 }
542
543 /*!
544 \brief software generate events
545 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
546 \param[in] event: the timer software event generation sources
547 one or more parameters can be selected which are shown as below:
548 \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0,1,5,6,7,19,20)
549 \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0,1,7,19,20)
550 \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0,1,7,19,20)
551 \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0,1,7,19,20)
552 \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0,1,7,19,20)
553 \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7,19,20)
554 \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0,1,7,19,20)
555 \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7,19,20)
556 \arg TIMER_EVENT_SRC_MCH0G: multi mode channel 0 capture or compare event generation, TIMERx(x=0,7,19,20)
557 \arg TIMER_EVENT_SRC_MCH1G: multi mode channel 1 capture or compare event generation, TIMERx(x=0,7,19,20)
558 \arg TIMER_EVENT_SRC_MCH2G: multi mode channel 2 capture or compare event generation, TIMERx(x=0,7,19,20)
559 \arg TIMER_EVENT_SRC_MCH3G: multi mode channel 3 capture or compare event generation, TIMERx(x=0,7,19,20)
560 \arg TIMER_EVENT_SRC_CH0COMADDG: channel 0 additional compare event generation, TIMERx(x=0,7,19,20)
561 \arg TIMER_EVENT_SRC_CH1COMADDG: channel 1 additional compare event generation, TIMERx(x=0,7,19,20)
562 \arg TIMER_EVENT_SRC_CH2COMADDG: channel 2 additional compare event generation, TIMERx(x=0,7,19,20)
563 \arg TIMER_EVENT_SRC_CH3COMADDG: channel 3 additional compare event generation, TIMERx(x=0,7,19,20)
564 \param[out] none
565 \retval none
566 */
timer_event_software_generate(uint32_t timer_periph,uint32_t event)567 void timer_event_software_generate(uint32_t timer_periph, uint32_t event)
568 {
569 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
570 }
571
572 /*!
573 \brief initialize TIMER break parameter struct with a default value
574 \param[in] breakpara: TIMER break parameter struct
575 \param[out] none
576 \retval none
577 */
timer_break_struct_para_init(timer_break_parameter_struct * breakpara)578 void timer_break_struct_para_init(timer_break_parameter_struct *breakpara)
579 {
580 /* initialize the break parameter struct member with the default value */
581 breakpara->runoffstate = (uint16_t)TIMER_ROS_STATE_DISABLE;
582 breakpara->ideloffstate = (uint16_t)TIMER_IOS_STATE_DISABLE;
583 breakpara->deadtime = 0U;
584 breakpara->breakpolarity = (uint16_t)TIMER_BREAK_POLARITY_LOW;
585 breakpara->outputautostate = (uint16_t)TIMER_OUTAUTO_DISABLE;
586 breakpara->protectmode = (uint16_t)TIMER_CCHP_PROT_OFF;
587 breakpara->breakstate = (uint16_t)TIMER_BREAK_DISABLE;
588 }
589
590 /*!
591 \brief configure TIMER break function
592 \param[in] timer_periph: TIMERx(x=0,7,19,20)
593 \param[in] breakpara: TIMER break parameter struct
594 runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE
595 ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE
596 deadtime: 0~255
597 breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH
598 outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE
599 protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2
600 breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE
601 \param[out] none
602 \retval none
603 */
timer_break_config(uint32_t timer_periph,timer_break_parameter_struct * breakpara)604 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
605 {
606 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
607 ((uint32_t)(breakpara->ideloffstate)) |
608 ((uint32_t)(breakpara->deadtime)) |
609 ((uint32_t)(breakpara->breakpolarity)) |
610 ((uint32_t)(breakpara->outputautostate)) |
611 ((uint32_t)(breakpara->protectmode)) |
612 ((uint32_t)(breakpara->breakstate)));
613 }
614
615 /*!
616 \brief enable TIMER break function
617 \param[in] timer_periph: TIMERx(x=0,7,19,20)
618 \param[out] none
619 \retval none
620 */
timer_break_enable(uint32_t timer_periph)621 void timer_break_enable(uint32_t timer_periph)
622 {
623 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
624 }
625
626 /*!
627 \brief disable TIMER break function
628 \param[in] timer_periph: TIMERx(x=0,7,19,20)
629 \param[out] none
630 \retval none
631 */
timer_break_disable(uint32_t timer_periph)632 void timer_break_disable(uint32_t timer_periph)
633 {
634 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
635 }
636
637 /*!
638 \brief enable TIMER output automatic function
639 \param[in] timer_periph: TIMERx(x=0,7,19,20)
640 \param[out] none
641 \retval none
642 */
timer_automatic_output_enable(uint32_t timer_periph)643 void timer_automatic_output_enable(uint32_t timer_periph)
644 {
645 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
646 }
647
648 /*!
649 \brief disable TIMER output automatic function
650 \param[in] timer_periph: TIMERx(x=0,7,19,20)
651 \param[out] none
652 \retval none
653 */
timer_automatic_output_disable(uint32_t timer_periph)654 void timer_automatic_output_disable(uint32_t timer_periph)
655 {
656 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
657 }
658
659 /*!
660 \brief configure TIMER primary output function
661 \param[in] timer_periph: TIMERx(x=0,7,19,20)
662 \param[in] newvalue: ENABLE or DISABLE
663 \param[out] none
664 \retval none
665 */
timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)666 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
667 {
668 if(ENABLE == newvalue) {
669 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
670 } else {
671 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
672 }
673 }
674
675 /*!
676 \brief initialize TIMER channel output parameter struct with a default value
677 \param[in] ocpara: TIMER channel n output parameter struct
678 \param[out] none
679 \retval none
680 */
timer_channel_output_struct_para_init(timer_oc_parameter_struct * ocpara)681 void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara)
682 {
683 /* initialize the channel output parameter struct member with the default value */
684 ocpara->outputstate = TIMER_CCX_DISABLE;
685 ocpara->outputnstate = TIMER_CCXN_DISABLE;
686 ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH;
687 ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH;
688 ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW;
689 ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
690 }
691
692 /*!
693 \brief configure TIMER channel output function
694 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
695 \param[in] channel: TIMER channel
696 only one parameter can be selected which is shown as below:
697 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
698 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
699 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
700 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
701 \param[in] ocpara: TIMER channel output parameter struct
702 outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE
703 outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE
704 ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW
705 ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW
706 ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH
707 ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH
708 \param[out] none
709 \retval none
710 */
timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct * ocpara)711 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
712 {
713 switch(channel) {
714 /* configure TIMER_CH_0 */
715 case TIMER_CH_0:
716 /* reset the CH0EN bit */
717 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
718 /* set the CH0EN bit */
719 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
720 /* reset the CH0P bit */
721 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
722 /* set the CH0P bit */
723 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
724
725 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) ||
726 (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) {
727 /* reset the MCH0EN bit */
728 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN);
729 /* set the MCH0EN bit */
730 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
731
732 /* reset the MCH0P bit */
733 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0P);
734 /* set the MCH0P bit */
735 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
736
737 /* reset the ISO0 bit */
738 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
739 /* set the ISO0 bit */
740 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
741
742 /* reset the ISO0N bit */
743 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
744 /* set the ISO0N bit */
745 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
746 }
747 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
748 break;
749 /* configure TIMER_CH_1 */
750 case TIMER_CH_1:
751 /* reset the CH1EN bit */
752 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
753 /* set the CH1EN bit */
754 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U);
755 /* reset the CH1P bit */
756 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
757 /* set the CH1P bit */
758 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
759
760 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) ||
761 (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) {
762 /* reset the MCH1EN bit */
763 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN);
764 /* set the MCH1EN bit */
765 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
766 /* reset the MCH1P bit */
767 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1P);
768 /* set the MCH1P bit */
769 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
770 /* reset the ISO1 bit */
771 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
772 /* set the ISO1 bit */
773 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
774 /* reset the ISO1N bit */
775 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
776 /* set the ISO1N bit */
777 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
778 }
779 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
780 break;
781 /* configure TIMER_CH_2 */
782 case TIMER_CH_2:
783 /* reset the CH2EN bit */
784 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
785 /* set the CH2EN bit */
786 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U);
787 /* reset the CH2P bit */
788 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
789 /* set the CH2P bit */
790 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
791
792 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) ||
793 (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) {
794 /* reset the MCH2EN bit */
795 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN);
796 /* set the MCH2EN bit */
797 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
798 /* reset the MCH2P bit */
799 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2P);
800 /* set the MCH2P bit */
801 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
802 /* reset the ISO2 bit */
803 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
804 /* set the ISO2 bit */
805 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
806 /* reset the ISO2N bit */
807 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
808 /* set the ISO2N bit */
809 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
810 }
811 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
812 break;
813 /* configure TIMER_CH_3 */
814 case TIMER_CH_3:
815 /* reset the CH3EN bit */
816 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
817 /* set the CH3EN bit */
818 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U);
819 /* reset the CH3P bit */
820 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
821 /* set the CH3P bit */
822 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
823
824 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) ||
825 (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) {
826 /* reset the MCH3EN bit */
827 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN);
828 /* set the MCH3EN bit */
829 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 12U);
830 /* reset the MCH3P bit */
831 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3P);
832 /* set the MCH3P bit */
833 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 12U);
834 /* reset the ISO3 bit */
835 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
836 /* set the ISO3 bit */
837 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
838 /* reset the ISO3N bit */
839 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3N);
840 /* set the ISO3N bit */
841 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 6U);
842 }
843 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
844 break;
845 default:
846 break;
847 }
848 }
849
850 /*!
851 \brief configure TIMER channel output compare mode
852 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
853 \param[in] channel: TIMER channel
854 only one parameter can be selected which is shown as below:
855 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
856 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
857 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
858 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
859 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
860 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
861 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
862 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
863 \param[in] ocmode: channel output compare mode
864 only one parameter can be selected which is shown as below:
865 \arg TIMER_OC_MODE_TIMING: timing mode
866 \arg TIMER_OC_MODE_ACTIVE: active mode
867 \arg TIMER_OC_MODE_INACTIVE: inactive mode
868 \arg TIMER_OC_MODE_TOGGLE: toggle mode
869 \arg TIMER_OC_MODE_LOW: force low mode
870 \arg TIMER_OC_MODE_HIGH: force high mode
871 \arg TIMER_OC_MODE_PWM0: PWM mode 0
872 \arg TIMER_OC_MODE_PWM1: PWM mode 1
873 \param[out] none
874 \retval none
875 */
timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode)876 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
877 {
878 switch(channel) {
879 /* configure TIMER_CH_0 */
880 case TIMER_CH_0:
881 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
882 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
883 break;
884 /* configure TIMER_CH_1 */
885 case TIMER_CH_1:
886 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
887 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
888 break;
889 /* configure TIMER_CH_2 */
890 case TIMER_CH_2:
891 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
892 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
893 break;
894 /* configure TIMER_CH_3 */
895 case TIMER_CH_3:
896 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
897 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
898 break;
899 /* configure TIMER_MCH_0 */
900 case TIMER_MCH_0:
901 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0COMCTL);
902 TIMER_MCHCTL0(timer_periph) |= (uint32_t)ocmode;
903 break;
904 /* configure TIMER_MCH_1 */
905 case TIMER_MCH_1:
906 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1COMCTL);
907 TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
908 break;
909 /* configure TIMER_MCH_2 */
910 case TIMER_MCH_2:
911 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2COMCTL);
912 TIMER_MCHCTL1(timer_periph) |= (uint32_t)ocmode;
913 break;
914 /* configure TIMER_MCH_3 */
915 case TIMER_MCH_3:
916 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3COMCTL);
917 TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
918 break;
919 default:
920 break;
921 }
922 }
923
924 /*!
925 \brief configure TIMER channel output pulse value
926 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
927 \param[in] channel: TIMER channel
928 only one parameter can be selected which is shown as below:
929 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
930 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
931 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
932 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
933 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
934 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
935 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
936 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
937 \param[in] pulse: channel output pulse value
938 \param[out] none
939 \retval none
940 */
timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse)941 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
942 {
943 switch(channel) {
944 /* configure TIMER_CH_0 */
945 case TIMER_CH_0:
946 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
947 break;
948 /* configure TIMER_CH_1 */
949 case TIMER_CH_1:
950 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
951 break;
952 /* configure TIMER_CH_2 */
953 case TIMER_CH_2:
954 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
955 break;
956 /* configure TIMER_CH_3 */
957 case TIMER_CH_3:
958 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
959 break;
960 /* configure TIMER_MCH_0 */
961 case TIMER_MCH_0:
962 TIMER_MCH0CV(timer_periph) = (uint32_t)pulse;
963 break;
964 /* configure TIMER_MCH_1 */
965 case TIMER_MCH_1:
966 TIMER_MCH1CV(timer_periph) = (uint32_t)pulse;
967 break;
968 /* configure TIMER_MCH_2 */
969 case TIMER_MCH_2:
970 TIMER_MCH2CV(timer_periph) = (uint32_t)pulse;
971 break;
972 /* configure TIMER_MCH_3 */
973 case TIMER_MCH_3:
974 TIMER_MCH3CV(timer_periph) = (uint32_t)pulse;
975 break;
976 default:
977 break;
978 }
979 }
980
981 /*!
982 \brief configure TIMER channel output shadow function
983 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
984 \param[in] channel: TIMER channel
985 only one parameter can be selected which is shown as below:
986 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
987 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
988 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
989 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
990 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
991 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
992 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
993 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
994 \param[in] ocshadow: channel output compare shadow
995 only one parameter can be selected which is shown as below:
996 \arg TIMER_OC_SHADOW_ENABLE: channel output compare shadow enable
997 \arg TIMER_OC_SHADOW_DISABLE: channel output compare shadow disable
998 \arg TIMER_OMC_SHADOW_ENABLE: multi mode channel output compare shadow enable
999 \arg TIMER_OMC_SHADOW_DISABLE: multi mode channel output compare shadow disable
1000 \param[out] none
1001 \retval none
1002 */
timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow)1003 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
1004 {
1005 switch(channel) {
1006 /* configure TIMER_CH_0 */
1007 case TIMER_CH_0:
1008 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
1009 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
1010 break;
1011 /* configure TIMER_CH_1 */
1012 case TIMER_CH_1:
1013 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
1014 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
1015 break;
1016 /* configure TIMER_CH_2 */
1017 case TIMER_CH_2:
1018 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
1019 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
1020 break;
1021 /* configure TIMER_CH_3 */
1022 case TIMER_CH_3:
1023 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
1024 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
1025 break;
1026 /* configure TIMER_MCH_0 */
1027 case TIMER_MCH_0:
1028 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0COMSEN);
1029 TIMER_MCHCTL0(timer_periph) |= (uint32_t)ocshadow;
1030 break;
1031 /* configure TIMER_MCH_1 */
1032 case TIMER_MCH_1:
1033 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1COMSEN);
1034 TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
1035 break;
1036 /* configure TIMER_MCH_2 */
1037 case TIMER_MCH_2:
1038 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2COMSEN);
1039 TIMER_MCHCTL1(timer_periph) |= (uint32_t)ocshadow;
1040 break;
1041 /* configure TIMER_MCH_3 */
1042 case TIMER_MCH_3:
1043 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3COMSEN);
1044 TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
1045 break;
1046 default:
1047 break;
1048 }
1049 }
1050
1051 /*!
1052 \brief configure TIMER channel output clear function
1053 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1054 \param[in] channel: TIMER channel
1055 only one parameter can be selected which is shown as below:
1056 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
1057 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
1058 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
1059 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
1060 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
1061 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
1062 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
1063 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
1064 \param[in] occlear: channel output clear function
1065 only one parameter can be selected which is shown as below:
1066 \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
1067 \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
1068 \arg TIMER_OMC_CLEAR_ENABLE: multi mode channel output clear function enable
1069 \arg TIMER_OMC_CLEAR_DISABLE: multi mode channel output clear function disable
1070 \param[out] none
1071 \retval none
1072 */
timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear)1073 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
1074 {
1075 switch(channel) {
1076 /* configure TIMER_CH_0 */
1077 case TIMER_CH_0:
1078 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1079 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1080 break;
1081 /* configure TIMER_CH_1 */
1082 case TIMER_CH_1:
1083 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1084 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1085 break;
1086 /* configure TIMER_CH_2 */
1087 case TIMER_CH_2:
1088 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1089 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1090 break;
1091 /* configure TIMER_CH_3 */
1092 case TIMER_CH_3:
1093 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1094 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1095 break;
1096 /* configure TIMER_MCH_0 */
1097 case TIMER_MCH_0:
1098 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0COMCEN);
1099 TIMER_MCHCTL0(timer_periph) |= (uint32_t)occlear;
1100 break;
1101 /* configure TIMER_MCH_1 */
1102 case TIMER_MCH_1:
1103 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1COMCEN);
1104 TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1105 break;
1106 /* configure TIMER_MCH_2 */
1107 case TIMER_MCH_2:
1108 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2COMCEN);
1109 TIMER_MCHCTL1(timer_periph) |= (uint32_t)occlear;
1110 break;
1111 /* configure TIMER_MCH_3 */
1112 case TIMER_MCH_3:
1113 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3COMCEN);
1114 TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1115 break;
1116 default:
1117 break;
1118 }
1119 }
1120
1121 /*!
1122 \brief configure TIMER channel output polarity
1123 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1124 \param[in] channel: TIMER channel
1125 only one parameter can be selected which is shown as below:
1126 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
1127 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
1128 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
1129 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
1130 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
1131 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
1132 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
1133 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
1134 \param[in] ocpolarity: channel output polarity
1135 only one parameter can be selected which is shown as below:
1136 \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
1137 \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
1138 \arg TIMER_OMC_POLARITY_HIGH: multi mode channel output polarity is high
1139 \arg TIMER_OMC_POLARITY_LOW: multi mode channel output polarity is low
1140 \param[out] none
1141 \retval none
1142 */
timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity)1143 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1144 {
1145 switch(channel) {
1146 /* configure TIMER_CH_0 */
1147 case TIMER_CH_0:
1148 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1149 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1150 break;
1151 /* configure TIMER_CH_1 */
1152 case TIMER_CH_1:
1153 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1154 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1155 break;
1156 /* configure TIMER_CH_2 */
1157 case TIMER_CH_2:
1158 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1159 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1160 break;
1161 /* configure TIMER_CH_3 */
1162 case TIMER_CH_3:
1163 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1164 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1165 break;
1166 /* configure TIMER_MCH_0 */
1167 case TIMER_MCH_0:
1168 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH0FP);
1169 TIMER_MCHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1170 break;
1171 /* configure TIMER_MCH_1 */
1172 case TIMER_MCH_1:
1173 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH1FP);
1174 TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 2U);
1175 break;
1176 /* configure TIMER_MCH_2 */
1177 case TIMER_MCH_2:
1178 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH2FP);
1179 TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1180 break;
1181 /* configure TIMER_MCH_3 */
1182 case TIMER_MCH_3:
1183 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH3FP);
1184 TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 6U);
1185 break;
1186 default:
1187 break;
1188 }
1189 }
1190
1191 /*!
1192 \brief configure TIMER channel complementary output polarity
1193 \param[in] timer_periph: TIMERx(x=0,7,19,20)
1194 \param[in] channel: TIMER channel
1195 only one parameter can be selected which is shown as below:
1196 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,7,19,20))
1197 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,7,19,20))
1198 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,7,19,20))
1199 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,7,19,20))
1200 \param[in] ocnpolarity: channel complementary output polarity
1201 only one parameter can be selected which is shown as below:
1202 \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
1203 \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
1204 \param[out] none
1205 \retval none
1206 */
timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity)1207 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1208 {
1209 switch(channel) {
1210 /* configure TIMER_CH_0 */
1211 case TIMER_CH_0:
1212 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0P);
1213 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1214 break;
1215 /* configure TIMER_CH_1 */
1216 case TIMER_CH_1:
1217 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1P);
1218 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1219 break;
1220 /* configure TIMER_CH_2 */
1221 case TIMER_CH_2:
1222 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2P);
1223 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1224 break;
1225 /* configure TIMER_CH_3 */
1226 case TIMER_CH_3:
1227 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3P);
1228 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U);
1229 break;
1230 default:
1231 break;
1232 }
1233 }
1234
1235 /*!
1236 \brief configure TIMER channel enable state
1237 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1238 \param[in] channel: TIMER channel
1239 only one parameter can be selected which is shown as below:
1240 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
1241 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
1242 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
1243 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
1244 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
1245 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
1246 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
1247 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
1248 \param[in] state: TIMER channel enable state
1249 only one parameter can be selected which is shown as below:
1250 \arg TIMER_CCX_ENABLE: channel enable
1251 \arg TIMER_CCX_DISABLE: channel disable
1252 \arg TIMER_MCCX_ENABLE: multi mode channel enable
1253 \arg TIMER_MCCX_DISABLE: multi mode channel disable
1254 \param[out] none
1255 \retval none
1256 */
timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state)1257 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1258 {
1259 switch(channel) {
1260 /* configure TIMER_CH_0 */
1261 case TIMER_CH_0:
1262 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1263 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1264 break;
1265 /* configure TIMER_CH_1 */
1266 case TIMER_CH_1:
1267 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1268 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1269 break;
1270 /* configure TIMER_CH_2 */
1271 case TIMER_CH_2:
1272 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1273 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1274 break;
1275 /* configure TIMER_CH_3 */
1276 case TIMER_CH_3:
1277 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1278 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1279 break;
1280 /* configure TIMER_MCH_0 */
1281 case TIMER_MCH_0:
1282 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN);
1283 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state);
1284 break;
1285 /* configure TIMER_MCH_1 */
1286 case TIMER_MCH_1:
1287 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN);
1288 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(state << 4U));
1289 break;
1290 /* configure TIMER_MCH_2 */
1291 case TIMER_MCH_2:
1292 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN);
1293 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(state << 8U));
1294 break;
1295 /* configure TIMER_MCH_3 */
1296 case TIMER_MCH_3:
1297 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN);
1298 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(state << 12U));
1299 break;
1300 default:
1301 break;
1302 }
1303 }
1304
1305 /*!
1306 \brief configure TIMER channel complementary output enable state
1307 \param[in] timer_periph: TIMERx(x=0,7,19,20)
1308 \param[in] channel: TIMER channel
1309 only one parameter can be selected which is shown as below:
1310 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,7,19,20))
1311 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,7,19,20))
1312 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,7,19,20))
1313 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,7,19,20))
1314 \param[in] ocnstate: TIMER channel complementary output enable state
1315 only one parameter can be selected which is shown as below:
1316 \arg TIMER_CCXN_ENABLE: channel complementary enable
1317 \arg TIMER_CCXN_DISABLE: channel complementary disable
1318 \param[out] none
1319 \retval none
1320 */
timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate)1321 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1322 {
1323 switch(channel) {
1324 /* configure TIMER_CH_0 */
1325 case TIMER_CH_0:
1326 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN);
1327 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1328 break;
1329 /* configure TIMER_CH_1 */
1330 case TIMER_CH_1:
1331 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN);
1332 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1333 break;
1334 /* configure TIMER_CH_2 */
1335 case TIMER_CH_2:
1336 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN);
1337 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1338 break;
1339 /* configure TIMER_CH_3 */
1340 case TIMER_CH_3:
1341 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN);
1342 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 12U);
1343 break;
1344 default:
1345 break;
1346 }
1347 }
1348
1349 /*!
1350 \brief initialize TIMER channel input parameter struct with a default value
1351 \param[in] icpara: TIMER channel input parameter struct
1352 \param[out] none
1353 \retval none
1354 */
timer_channel_input_struct_para_init(timer_ic_parameter_struct * icpara)1355 void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara)
1356 {
1357 /* initialize the channel input parameter struct member with the default value */
1358 icpara->icpolarity = TIMER_IC_POLARITY_RISING;
1359 icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
1360 icpara->icprescaler = TIMER_IC_PSC_DIV1;
1361 icpara->icfilter = 0U;
1362 }
1363
1364 /*!
1365 \brief configure TIMER input capture parameter
1366 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1367 \param[in] channel: TIMER channel
1368 only one parameter can be selected which is shown as below:
1369 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
1370 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
1371 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
1372 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
1373 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
1374 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
1375 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
1376 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
1377 \param[in] icpara: TIMER channel input parameter struct
1378 icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, TIMER_IC_POLARITY_BOTH_EDGE
1379 icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, TIMER_IC_SELECTION_ITS, TIMER_IC_SELECTION_PAIR
1380 icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, TIMER_IC_PSC_DIV8
1381 icfilter: 0~15
1382 \param[out] none
1383 \retval none
1384 */
timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpara)1385 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
1386 {
1387 switch(channel) {
1388 /* configure TIMER_CH_0 */
1389 case TIMER_CH_0:
1390 /* reset the CH0EN bit */
1391 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1392
1393 /* reset the CH0P and MCH0P bits */
1394 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P));
1395 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1396
1397 /* reset the CH0MS bit */
1398 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1399 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1400 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 28U);
1401 } else {
1402 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1403 }
1404
1405 /* reset the CH0CAPFLT bit */
1406 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1407 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1408
1409 /* set the CH0EN bit */
1410 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1411 break;
1412
1413 /* configure TIMER_CH_1 */
1414 case TIMER_CH_1:
1415 /* reset the CH1EN bit */
1416 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1417
1418 /* reset the CH1P and MCH1P bits */
1419 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P));
1420 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1421
1422 /* reset the CH1MS bit */
1423 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1424 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1425 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 29U);
1426 } else {
1427 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1428 }
1429 /* reset the CH1CAPFLT bit */
1430 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1431 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1432
1433 /* set the CH1EN bit */
1434 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1435 break;
1436 /* configure TIMER_CH_2 */
1437 case TIMER_CH_2:
1438 /* reset the CH2EN bit */
1439 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1440
1441 /* reset the CH2P and MCH2P bits */
1442 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_MCH2P));
1443 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1444
1445 /* reset the CH2MS bit */
1446 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1447 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1448 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 28U);
1449 } else {
1450 TIMER_CHCTL1(timer_periph) |= (uint32_t)(icpara->icselection);
1451 }
1452
1453 /* reset the CH2CAPFLT bit */
1454 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1455 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1456
1457 /* set the CH2EN bit */
1458 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1459 break;
1460 /* configure TIMER_CH_3 */
1461 case TIMER_CH_3:
1462 /* reset the CH3EN bit */
1463 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1464
1465 /* reset the CH3P bits */
1466 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P | TIMER_CHCTL2_MCH3P));
1467 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1468
1469 /* reset the CH3MS bit */
1470 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1471 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1472 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 29U);
1473 } else {
1474 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1475 }
1476
1477 /* reset the CH3CAPFLT bit */
1478 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1479 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1480
1481 /* set the CH3EN bit */
1482 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1483 break;
1484
1485 /* configure TIMER_MCH_0 */
1486 case TIMER_MCH_0:
1487 /* reset the MCH0EN bit */
1488 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN);
1489
1490 /* reset the MCH0FP bits */
1491 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH0FP));
1492 switch(icpara->icpolarity) {
1493 case TIMER_IC_POLARITY_RISING:
1494 TIMER_MCHCTL2(timer_periph) |= TIMER_IMC_POLARITY_RISING;
1495 break;
1496 case TIMER_IC_POLARITY_FALLING:
1497 TIMER_MCHCTL2(timer_periph) |= TIMER_IMC_POLARITY_FALLING;
1498 break;
1499 case TIMER_IC_POLARITY_BOTH_EDGE:
1500 TIMER_MCHCTL2(timer_periph) |= TIMER_IMC_POLARITY_BOTH_EDGE;
1501 break;
1502 default:
1503 break;
1504 }
1505
1506 /* reset the MCH0MS bit */
1507 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0MS);
1508 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1509 TIMER_MCHCTL0(timer_periph) |= ((uint32_t)icpara->icselection << 28U);
1510 } else {
1511 TIMER_MCHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1512 }
1513
1514 /* reset the MCH0CAPFLT bit */
1515 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0CAPFLT);
1516 TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1517
1518 /* set the MCH0EN bit */
1519 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH0EN;
1520 break;
1521
1522 /* configure TIMER_MCH_1 */
1523 case TIMER_MCH_1:
1524 /* reset the MCH1EN bit */
1525 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN);
1526
1527 /* reset the MCH1FP bits */
1528 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH1FP));
1529 switch(icpara->icpolarity) {
1530 case TIMER_IC_POLARITY_RISING:
1531 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_RISING << 2U);
1532 break;
1533 case TIMER_IC_POLARITY_FALLING:
1534 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_FALLING << 2U);
1535 break;
1536 case TIMER_IC_POLARITY_BOTH_EDGE:
1537 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_BOTH_EDGE << 2U);
1538 break;
1539 default:
1540 break;
1541 }
1542 /* reset the MCH1MS bit */
1543 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1MS);
1544 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1545 TIMER_MCHCTL0(timer_periph) |= ((uint32_t)icpara->icselection << 29U);
1546 } else {
1547 TIMER_MCHCTL0(timer_periph) |= ((uint32_t)(icpara->icselection) << 8U);
1548 }
1549
1550 /* reset the MCH1CAPFLT bit */
1551 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1CAPFLT);
1552 TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1553
1554 /* set the MCH1EN bit */
1555 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH1EN;
1556 break;
1557 /* configure TIMER_MCH_2 */
1558 case TIMER_MCH_2:
1559 /* reset the MCH2EN bit */
1560 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN);
1561
1562 /* reset the MCH2FP bits */
1563 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH2FP));
1564 switch(icpara->icpolarity) {
1565 case TIMER_IC_POLARITY_RISING:
1566 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_RISING << 4U);
1567 break;
1568 case TIMER_IC_POLARITY_FALLING:
1569 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_FALLING << 4U);
1570 break;
1571 case TIMER_IC_POLARITY_BOTH_EDGE:
1572 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_BOTH_EDGE << 4U);
1573 break;
1574 default:
1575 break;
1576 }
1577 /* reset the MCH2MS bit */
1578 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2MS);
1579 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1580 TIMER_MCHCTL1(timer_periph) |= ((uint32_t)icpara->icselection << 28U);
1581 } else {
1582 TIMER_MCHCTL1(timer_periph) |= ((uint32_t)(icpara->icselection));
1583 }
1584
1585 /* reset the MCH2CAPFLT bit */
1586 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2CAPFLT);
1587 TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1588
1589 /* set the MCH2EN bit */
1590 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH2EN;
1591 break;
1592 /* configure TIMER_MCH_3 */
1593 case TIMER_MCH_3:
1594 /* reset the MCH3EN bit */
1595 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN);
1596
1597 /* reset the MCH3FP bits */
1598 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH3FP));
1599 switch(icpara->icpolarity) {
1600 case TIMER_IC_POLARITY_RISING:
1601 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_RISING << 6U);
1602 break;
1603 case TIMER_IC_POLARITY_FALLING:
1604 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_FALLING << 6U);
1605 break;
1606 case TIMER_IC_POLARITY_BOTH_EDGE:
1607 TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_BOTH_EDGE << 6U);
1608 break;
1609 default:
1610 break;
1611 }
1612 /* reset the MCH3MS bit */
1613 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3MS);
1614 if(TIMER_IC_SELECTION_PAIR == icpara->icselection) {
1615 TIMER_MCHCTL1(timer_periph) |= ((uint32_t)icpara->icselection << 29U);
1616 } else {
1617 TIMER_MCHCTL1(timer_periph) |= ((uint32_t)(icpara->icselection) << 8U);
1618 }
1619
1620 /* reset the MCH3CAPFLT bit */
1621 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3CAPFLT);
1622 TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1623
1624 /* set the MCH3EN bit */
1625 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH3EN;
1626 break;
1627 default:
1628 break;
1629 }
1630 /* configure TIMER channel input capture prescaler value */
1631 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1632 }
1633
1634 /*!
1635 \brief configure TIMER channel input capture prescaler value
1636 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1637 \param[in] channel: TIMER channel
1638 only one parameter can be selected which is shown as below:
1639 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
1640 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
1641 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
1642 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
1643 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
1644 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
1645 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
1646 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
1647 \param[in] prescaler: channel input capture prescaler value
1648 only one parameter can be selected which is shown as below:
1649 \arg TIMER_IC_PSC_DIV1: no prescaler
1650 \arg TIMER_IC_PSC_DIV2: divided by 2
1651 \arg TIMER_IC_PSC_DIV4: divided by 4
1652 \arg TIMER_IC_PSC_DIV8: divided by 8
1653 \param[out] none
1654 \retval none
1655 */
timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler)1656 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1657 {
1658 switch(channel) {
1659 /* configure TIMER_CH_0 */
1660 case TIMER_CH_0:
1661 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1662 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1663 break;
1664 /* configure TIMER_CH_1 */
1665 case TIMER_CH_1:
1666 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1667 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1668 break;
1669 /* configure TIMER_CH_2 */
1670 case TIMER_CH_2:
1671 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1672 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1673 break;
1674 /* configure TIMER_CH_3 */
1675 case TIMER_CH_3:
1676 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1677 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1678 break;
1679 /* configure TIMER_MCH_0 */
1680 case TIMER_MCH_0:
1681 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0CAPPSC);
1682 TIMER_MCHCTL0(timer_periph) |= (uint32_t)prescaler;
1683 break;
1684 /* configure TIMER_MCH_1 */
1685 case TIMER_MCH_1:
1686 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1CAPPSC);
1687 TIMER_MCHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1688 break;
1689 /* configure TIMER_MCH_2 */
1690 case TIMER_MCH_2:
1691 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2CAPPSC);
1692 TIMER_MCHCTL1(timer_periph) |= (uint32_t)prescaler;
1693 break;
1694 /* configure TIMER_MCH_3 */
1695 case TIMER_MCH_3:
1696 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3CAPPSC);
1697 TIMER_MCHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1698 break;
1699 default:
1700 break;
1701 }
1702 }
1703
1704 /*!
1705 \brief read TIMER channel capture compare register value
1706 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1707 \param[in] channel: TIMER channel
1708 only one parameter can be selected which is shown as below:
1709 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
1710 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
1711 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
1712 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
1713 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
1714 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
1715 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
1716 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
1717 \param[out] none
1718 \retval channel capture compare register value(0~65535)
1719 */
timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel)1720 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1721 {
1722 uint32_t count_value = 0U;
1723
1724 switch(channel) {
1725 case TIMER_CH_0:
1726 /* read TIMER_CH_0 capture compare register value */
1727 count_value = TIMER_CH0CV(timer_periph);
1728 break;
1729 case TIMER_CH_1:
1730 /* read TIMER_CH_1 capture compare register value */
1731 count_value = TIMER_CH1CV(timer_periph);
1732 break;
1733 case TIMER_CH_2:
1734 /* read TIMER_CH_2 capture compare register value */
1735 count_value = TIMER_CH2CV(timer_periph);
1736 break;
1737 case TIMER_CH_3:
1738 /* read TIMER_CH_3 capture compare register value */
1739 count_value = TIMER_CH3CV(timer_periph);
1740 break;
1741 case TIMER_MCH_0:
1742 /* read TIMER_MCH_0 capture compare register value */
1743 count_value = TIMER_MCH0CV(timer_periph);
1744 break;
1745 case TIMER_MCH_1:
1746 /* read TIMER_MCH_1 capture compare register value */
1747 count_value = TIMER_MCH1CV(timer_periph);
1748 break;
1749 case TIMER_MCH_2:
1750 /* read TIMER_MCH_2 capture compare register value */
1751 count_value = TIMER_MCH2CV(timer_periph);
1752 break;
1753 case TIMER_MCH_3:
1754 /* read TIMER_MCH_3 capture compare register value */
1755 count_value = TIMER_MCH3CV(timer_periph);
1756 break;
1757 default:
1758 break;
1759 }
1760 return (count_value);
1761 }
1762
1763 /*!
1764 \brief configure TIMER input pwm capture function
1765 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1766 \param[in] channel: TIMER channel
1767 only one parameter can be selected which is shown as below:
1768 \arg TIMER_CH_0: TIMER channel 0
1769 \arg TIMER_CH_1: TIMER channel 1
1770 \param[in] icpwm: TIMER channel input pwm parameter struct
1771 icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING
1772 icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI
1773 icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, TIMER_IC_PSC_DIV8
1774 icfilter: 0~15
1775 \param[out] none
1776 \retval none
1777 */
timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpwm)1778 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
1779 {
1780 uint16_t icpolarity = 0U;
1781 uint16_t icselection = 0U;
1782
1783 /* set channel input polarity */
1784 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) {
1785 icpolarity = TIMER_IC_POLARITY_FALLING;
1786 } else {
1787 icpolarity = TIMER_IC_POLARITY_RISING;
1788 }
1789 /* set channel input mode selection */
1790 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) {
1791 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1792 } else {
1793 icselection = TIMER_IC_SELECTION_DIRECTTI;
1794 }
1795
1796 if(TIMER_CH_0 == channel) {
1797 /* reset the CH0EN bit */
1798 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1799 /* reset the CH0P and MCH0P bits */
1800 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P));
1801 /* set the CH0P and MCH0P bits */
1802 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1803 /* reset the CH0MS bit */
1804 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1805 /* set the CH0MS bit */
1806 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1807 /* reset the CH0CAPFLT bit */
1808 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1809 /* set the CH0CAPFLT bit */
1810 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1811 /* set the CH0EN bit */
1812 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1813 /* configure TIMER channel input capture prescaler value */
1814 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1815
1816 /* reset the CH1EN bit */
1817 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1818 /* reset the CH1P and MCH1P bits */
1819 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P));
1820 /* set the CH1P and MCH1P bits */
1821 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
1822 /* reset the CH1MS bit */
1823 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1824 /* set the CH1MS bit */
1825 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1826 /* reset the CH1CAPFLT bit */
1827 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1828 /* set the CH1CAPFLT bit */
1829 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1830 /* set the CH1EN bit */
1831 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1832 /* configure TIMER channel input capture prescaler value */
1833 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1834 } else {
1835 /* reset the CH1EN bit */
1836 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1837 /* reset the CH1P and MCH1P bits */
1838 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P));
1839 /* set the CH1P and MCH1P bits */
1840 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1841 /* reset the CH1MS bit */
1842 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1843 /* set the CH1MS bit */
1844 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1845 /* reset the CH1CAPFLT bit */
1846 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1847 /* set the CH1CAPFLT bit */
1848 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1849 /* set the CH1EN bit */
1850 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1851 /* configure TIMER channel input capture prescaler value */
1852 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1853
1854 /* reset the CH0EN bit */
1855 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1856 /* reset the CH0P and MCH0P bits */
1857 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P));
1858 /* set the CH0P and MCH0P bits */
1859 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1860 /* reset the CH0MS bit */
1861 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1862 /* set the CH0MS bit */
1863 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1864 /* reset the CH0CAPFLT bit */
1865 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1866 /* set the CH0CAPFLT bit */
1867 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1868 /* set the CH0EN bit */
1869 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1870 /* configure TIMER channel input capture prescaler value */
1871 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1872 }
1873 }
1874
1875 /*!
1876 \brief configure TIMER hall sensor mode
1877 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
1878 \param[in] hallmode:
1879 only one parameter can be selected which is shown as below:
1880 \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
1881 \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
1882 \param[out] none
1883 \retval none
1884 */
timer_hall_mode_config(uint32_t timer_periph,uint32_t hallmode)1885 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
1886 {
1887 if(TIMER_HALLINTERFACE_ENABLE == hallmode) {
1888 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1889 } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) {
1890 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1891 } else {
1892 /* illegal parameters */
1893 }
1894 }
1895
1896 /*!
1897 \brief initialize TIMER multi mode channel output parameter struct
1898 \param[in] omcpara: TIMER multi mode channel output parameter struct
1899 \param[out] none
1900 \retval none
1901 */
timer_multi_mode_channel_output_parameter_struct_init(timer_omc_parameter_struct * omcpara)1902 void timer_multi_mode_channel_output_parameter_struct_init(timer_omc_parameter_struct *omcpara)
1903 {
1904 /* initialize the multi mode channel output parameter struct with the default value */
1905 omcpara->outputmode = TIMER_MCH_MODE_COMPLEMENTARY;
1906 omcpara->outputstate = TIMER_MCCX_DISABLE;
1907 omcpara->ocpolarity = TIMER_OMC_POLARITY_LOW;
1908 }
1909
1910 /*!
1911 \brief configure TIMER multi mode channel output function
1912 \param[in] timer_periph: TIMERx(x=0,7,19,20)
1913 \param[in] channel: TIMER channel
1914 only one parameter can be selected which is shown as below:
1915 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
1916 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
1917 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
1918 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
1919 \param[in] omcpara: TIMER multi mode channel output parameter struct
1920 outputmode: TIMER_MCH_MODE_INDEPENDENTLY, TIMER_MCH_MODE_MIRRORED, TIMER_MCH_MODE_COMPLEMENTARY
1921 outputstate: TIMER_MCCX_ENABLE, TIMER_MCCX_DISABLE
1922 ocpolarity: TIMER_OMC_POLARITY_HIGH, TIMER_OMC_POLARITY_LOW
1923 \param[out] none
1924 \retval none
1925 */
timer_multi_mode_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_omc_parameter_struct * omcpara)1926 void timer_multi_mode_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_omc_parameter_struct *omcpara)
1927 {
1928 switch(channel) {
1929 /* configure TIMER_MCH_0 */
1930 case TIMER_MCH_0:
1931 TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 20U));
1932 TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 20U);
1933 /* reset the MCH0EN bit */
1934 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN);
1935 /* set the MCH0EN bit */
1936 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate));
1937
1938 /* reset the MCH0FP bit */
1939 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH0FP);
1940 /* set the MCH0FP bit */
1941 TIMER_MCHCTL2(timer_periph) |= (uint32_t)omcpara->ocpolarity;
1942
1943 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0MS);
1944 break;
1945 /* configure TIMER_MCH_1 */
1946 case TIMER_MCH_1:
1947 TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 22U));
1948 TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 22U);
1949 /* reset the MCH1EN bit */
1950 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN);
1951 /* set the MCH1EN bit */
1952 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate) << 4U);
1953
1954 /* reset the MCH1FP bit */
1955 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH1FP);
1956 /* set the MCH1FP bit */
1957 TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->ocpolarity) << 2U);
1958
1959 TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1MS);
1960 break;
1961
1962 /* configure TIMER_MCH_2 */
1963 case TIMER_MCH_2:
1964 TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 24U));
1965 TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 24U);
1966 /* reset the MCH2EN bit */
1967 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN);
1968 /* set the MCH2EN bit */
1969 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate) << 8U);
1970
1971 /* reset the MCH2FP bit */
1972 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH2FP);
1973 /* set the MCH2FP bit */
1974 TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->ocpolarity) << 4U);
1975
1976 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2MS);
1977 break;
1978
1979 /* configure TIMER_MCH_3 */
1980 case TIMER_MCH_3:
1981 TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 26U));
1982 TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 26U);
1983 /* reset the MCH3EN bit */
1984 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN);
1985 /* set the MCH3EN bit */
1986 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate) << 12U);
1987
1988 /* reset the MCH3FP bit */
1989 TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH3FP);
1990 /* set the MCH3FP bit */
1991 TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->ocpolarity) << 6U);
1992
1993 TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3MS);
1994
1995 break;
1996 default:
1997 break;
1998 }
1999 }
2000
2001 /*!
2002 \brief multi mode channel mode select
2003 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2004 \param[in] channel: TIMER channel
2005 only one parameter can be selected which is shown as below:
2006 \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20))
2007 \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20))
2008 \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20))
2009 \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20))
2010 \param[in] multi_mode_sel: multi mode channel mode selection
2011 only one parameter can be selected which is shown as below:
2012 \arg TIMER_MCH_MODE_INDEPENDENTLY: multi mode channel work in independently mode
2013 \arg TIMER_MCH_MODE_MIRRORED: multi mode channel work in mirrored output mode
2014 \arg TIMER_MCH_MODE_COMPLEMENTARY: multi mode channel work in complementary output mode
2015 \param[out] none
2016 \retval none
2017 */
timer_multi_mode_channel_mode_config(uint32_t timer_periph,uint32_t channel,uint32_t multi_mode_sel)2018 void timer_multi_mode_channel_mode_config(uint32_t timer_periph, uint32_t channel, uint32_t multi_mode_sel)
2019 {
2020 uint32_t reg = TIMER_CTL2(timer_periph);
2021 switch(channel) {
2022 /* configure TIMER_MCH_0 */
2023 case TIMER_MCH_0:
2024 reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 20U));
2025 reg |= (uint32_t)(multi_mode_sel << 20U);
2026 break;
2027 /* configure TIMER_MCH_1 */
2028 case TIMER_MCH_1:
2029 reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 22U));
2030 reg |= (uint32_t)(multi_mode_sel << 22U);
2031 break;
2032 /* configure TIMER_MCH_2 */
2033 case TIMER_MCH_2:
2034 reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 24U));
2035 reg |= (uint32_t)(multi_mode_sel << 24U);
2036 break;
2037 /* configure TIMER_MCH_3 */
2038 case TIMER_MCH_3:
2039 reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 26U));
2040 reg |= (uint32_t)(multi_mode_sel << 26U);
2041 break;
2042 default:
2043 break;
2044 }
2045 TIMER_CTL2(timer_periph) = reg;
2046 }
2047
2048
2049 /*!
2050 \brief select TIMER input trigger source
2051 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2052 \param[in] intrigger: input trigger source
2053 only one parameter can be selected which is shown as below:
2054 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,1,7,19,20))
2055 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,1,7,19,20))
2056 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,1,7,19,20))
2057 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0,1,7,19,20))
2058 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0,1,7,19,20))
2059 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered channel 0 input(TIMERx(x=0,1,7,19,20))
2060 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered channel 1 input(TIMERx(x=0,1,7,19,20))
2061 \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0,1,7,19,20))
2062 \arg TIMER_SMCFG_TRGSEL_CI2FE2: filtered channel 2 input(TIMERx(x=0,7,19,20))
2063 \arg TIMER_SMCFG_TRGSEL_CI3FE3: filtered channel 3 input(TIMERx(x=0,7,19,20))
2064 \arg TIMER_SMCFG_TRGSEL_MCI0FEM0: filtered multi mode channel 0 input(TIMERx(x=0,7,19,20))
2065 \arg TIMER_SMCFG_TRGSEL_MCI1FEM1: filtered multi mode channel 1 input(TIMERx(x=0,7,19,20))
2066 \arg TIMER_SMCFG_TRGSEL_MCI2FEM2: filtered multi mode channel 2 input(TIMERx(x=0,7,19,20))
2067 \arg TIMER_SMCFG_TRGSEL_MCI3FEM3: filtered multi mode channel 3 input(TIMERx(x=0,7,19,20))
2068 \param[out] none
2069 \retval none
2070 */
timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)2071 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
2072 {
2073 uint32_t reg;
2074
2075 reg = TIMER_SMCFG(timer_periph);
2076 reg &= (~(uint32_t)TIMER_SMCFG_TRGS);
2077 reg |= (uint32_t)intrigger;
2078 TIMER_SMCFG(timer_periph) = reg;
2079 }
2080
2081 /*!
2082 \brief select TIMER master mode output trigger source
2083 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
2084 \param[in] outrigger: trigger output source
2085 only one parameter can be selected which is shown as below:
2086 \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0,1,5,6,7,19,20))
2087 \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal as trigger output(TIMERx(x=0,1,5,6,7,19,20))
2088 \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0,1,5,6,7,19,20))
2089 \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0,1,7,19,20))
2090 \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0,1,7,19,20))
2091 \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0,1,7,19,20))
2092 \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0,1,7,19,20))
2093 \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0,1,7,19,20))
2094 \param[out] none
2095 \retval none
2096 */
timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger)2097 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
2098 {
2099 uint32_t reg;
2100
2101 reg = TIMER_CTL1(timer_periph);
2102 reg &= (~(uint32_t)TIMER_CTL1_MMC);
2103 reg |= (uint32_t)outrigger;
2104 TIMER_CTL1(timer_periph) = reg;
2105 }
2106
2107 /*!
2108 \brief select TIMER slave mode
2109 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2110 \param[in] slavemode: slave mode
2111 only one parameter can be selected which is shown as below:
2112 \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable
2113 \arg TIMER_ENCODER_MODE0: encoder mode 0
2114 \arg TIMER_ENCODER_MODE1: encoder mode 1
2115 \arg TIMER_ENCODER_MODE2: encoder mode 2
2116 \arg TIMER_SLAVE_MODE_RESTART: restart mode
2117 \arg TIMER_SLAVE_MODE_PAUSE: pause mode
2118 \arg TIMER_SLAVE_MODE_EVENT: event mode
2119 \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0
2120 \param[out] none
2121 \retval none
2122 */
2123
timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)2124 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
2125 {
2126 uint32_t reg;
2127
2128 reg = TIMER_SMCFG(timer_periph);
2129 reg &= (~(uint32_t)TIMER_SMCFG_SMC);
2130 reg |= (uint32_t)slavemode;
2131 TIMER_SMCFG(timer_periph) = reg;
2132 }
2133
2134 /*!
2135 \brief configure TIMER master slave mode
2136 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2137 \param[in] masterslave: master slave mode
2138 only one parameter can be selected which is shown as below:
2139 \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
2140 \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
2141 \param[out] none
2142 \retval none
2143 */
timer_master_slave_mode_config(uint32_t timer_periph,uint32_t masterslave)2144 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
2145 {
2146 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) {
2147 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
2148 } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) {
2149 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
2150 } else {
2151 /* illegal parameters */
2152 }
2153 }
2154
2155 /*!
2156 \brief configure TIMER external trigger input
2157 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2158 \param[in] extprescaler: external trigger prescaler
2159 only one parameter can be selected which is shown as below:
2160 \arg TIMER_EXT_TRI_PSC_OFF: no divided
2161 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
2162 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
2163 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
2164 \param[in] extpolarity: external trigger polarity
2165 only one parameter can be selected which is shown as below:
2166 \arg TIMER_ETP_FALLING: active low or falling edge active
2167 \arg TIMER_ETP_RISING: active high or rising edge active
2168 \param[in] extfilter: a value between 0 and 15
2169 \param[out] none
2170 \retval none
2171 */
timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)2172 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
2173 {
2174 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
2175 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
2176 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
2177 }
2178
2179 /*!
2180 \brief configure TIMER quadrature decoder mode
2181 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2182 \param[in] decomode: quadrature decoder mode
2183 only one parameter can be selected which is shown as below:
2184 \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
2185 \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
2186 \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
2187 \param[in] ic0polarity: input capture polarity
2188 only one parameter can be selected which is shown as below:
2189 \arg TIMER_IC_POLARITY_RISING: capture rising edge
2190 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
2191 \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge
2192 \param[in] ic1polarity: input capture polarity
2193 only one parameter can be selected which is shown as below:
2194 \arg TIMER_IC_POLARITY_RISING: capture rising edge
2195 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
2196 \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge
2197 \param[out] none
2198 \retval none
2199 */
timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode,uint16_t ic0polarity,uint16_t ic1polarity)2200 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
2201 {
2202 /* configure the quadrature decoder mode */
2203 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
2204 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
2205 /* configure input capture selection */
2206 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS)));
2207 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
2208 /* configure channel input capture polarity */
2209 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P));
2210 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P));
2211 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U));
2212 }
2213
2214 /*!
2215 \brief configure TIMER internal clock mode
2216 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2217 \param[out] none
2218 \retval none
2219 */
timer_internal_clock_config(uint32_t timer_periph)2220 void timer_internal_clock_config(uint32_t timer_periph)
2221 {
2222 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
2223 }
2224
2225 /*!
2226 \brief configure TIMER the internal trigger as external clock input
2227 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2228 \param[in] intrigger: internal trigger selection
2229 only one parameter can be selected which is shown as below:
2230 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
2231 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
2232 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
2233 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
2234 \param[out] none
2235 \retval none
2236 */
timer_internal_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t intrigger)2237 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
2238 {
2239 timer_input_trigger_source_select(timer_periph, intrigger);
2240 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
2241 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
2242 }
2243
2244 /*!
2245 \brief configure TIMER the external trigger as external clock input
2246 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2247 \param[in] extrigger: external trigger selection
2248 only one parameter can be selected which is shown as below:
2249 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
2250 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered channel 0 input
2251 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered channel 1 input
2252 \param[in] extpolarity: external input capture polarity
2253 only one parameter can be selected which is shown as below:
2254 \arg TIMER_IC_POLARITY_RISING: active high or rising edge active
2255 \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active
2256 \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge
2257 \param[in] extfilter: a value between 0 and 15
2258 \param[out] none
2259 \retval none
2260 */
timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger,uint16_t extpolarity,uint32_t extfilter)2261 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter)
2262 {
2263 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) {
2264 /* reset the CH1EN bit */
2265 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
2266 /* reset the CH1P and MCH1P bits */
2267 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P));
2268 /* set the CH1P and MCH1P bits */
2269 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
2270 /* reset the CH1MS bit */
2271 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
2272 /* set the CH1MS bit */
2273 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
2274 /* reset the CH1CAPFLT bit */
2275 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
2276 /* set the CH1CAPFLT bit */
2277 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
2278 /* set the CH1EN bit */
2279 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
2280 } else {
2281 /* reset the CH0EN bit */
2282 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
2283 /* reset the CH0P and MCH0P bits */
2284 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P));
2285 /* set the CH0P and MCH0P bits */
2286 TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
2287 /* reset the CH0MS bit */
2288 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
2289 /* set the CH0MS bit */
2290 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
2291 /* reset the CH0CAPFLT bit */
2292 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
2293 /* reset the CH0CAPFLT bit */
2294 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
2295 /* set the CH0EN bit */
2296 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
2297 }
2298 /* select TIMER input trigger source */
2299 timer_input_trigger_source_select(timer_periph, extrigger);
2300 /* reset the SMC bit */
2301 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
2302 /* set the SMC bit */
2303 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
2304 }
2305
2306 /*!
2307 \brief configure TIMER the external clock mode0
2308 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2309 \param[in] extprescaler: external trigger prescaler
2310 only one parameter can be selected which is shown as below:
2311 \arg TIMER_EXT_TRI_PSC_OFF: no divided
2312 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
2313 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
2314 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
2315 \param[in] extpolarity: external input capture polarity
2316 only one parameter can be selected which is shown as below:
2317 \arg TIMER_ETP_FALLING: active low or falling edge active
2318 \arg TIMER_ETP_RISING: active high or rising edge active
2319 \param[in] extfilter: a value between 0 and 15
2320 \param[out] none
2321 \retval none
2322 */
timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)2323 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
2324 {
2325 /* configure TIMER external trigger input */
2326 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
2327 /* reset the SMC bit,TRGS bit */
2328 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
2329 /* set the SMC bit,TRGS bit */
2330 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
2331 }
2332
2333 /*!
2334 \brief configure TIMER the external clock mode1
2335 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2336 \param[in] extprescaler: external trigger prescaler
2337 only one parameter can be selected which is shown as below:
2338 \arg TIMER_EXT_TRI_PSC_OFF: no divided
2339 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
2340 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
2341 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
2342 \param[in] extpolarity: external input capture polarity
2343 only one parameter can be selected which is shown as below:
2344 \arg TIMER_ETP_FALLING: active low or falling edge active
2345 \arg TIMER_ETP_RISING: active high or rising edge active
2346 \param[in] extfilter: a value between 0 and 15
2347 \param[out] none
2348 \retval none
2349 */
timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)2350 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
2351 {
2352 /* configure TIMER external trigger input */
2353 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
2354 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
2355 }
2356
2357 /*!
2358 \brief disable TIMER the external clock mode1
2359 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2360 \param[out] none
2361 \retval none
2362 */
timer_external_clock_mode1_disable(uint32_t timer_periph)2363 void timer_external_clock_mode1_disable(uint32_t timer_periph)
2364 {
2365 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
2366 }
2367
2368 /*!
2369 \brief configure TIMER channel input remap function
2370 \param[in] timer_periph: TIMERx(x=1)
2371 \param[in] remap: TIMER channel input remap
2372 only one parameter can be selected which is shown as below:
2373 \arg TIMER1_CI0_RMP_GPIO: TIMER1 channel 0 input remap to GPIO pin
2374 \arg TIMER1_CI0_RMP_LXTAL: TIMER1 channel 0 input remap to LXTAL
2375 \arg TIMER1_CI0_RMP_HXTAL: TIMER1 channel 0 input remap to HXTAL/128
2376 \arg TIMER1_CI0_RMP_CKOUT0SEL: TIMER1 channel 0 input remap to CKOUT0SEL
2377 \param[out] none
2378 \retval none
2379 */
timer_channel_remap_config(uint32_t timer_periph,uint32_t remap)2380 void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap)
2381 {
2382 TIMER_IRMP(timer_periph) = (uint32_t)remap;
2383 }
2384
2385 /*!
2386 \brief configure TIMER write CHxVAL register selection
2387 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2388 \param[in] ccsel: write CHxVAL register selection
2389 only one parameter can be selected which is shown as below:
2390 \arg TIMER_CHVSEL_DISABLE: no effect
2391 \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored
2392 \param[out] none
2393 \retval none
2394 */
timer_write_chxval_register_config(uint32_t timer_periph,uint16_t ccsel)2395 void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel)
2396 {
2397 if(TIMER_CHVSEL_ENABLE == ccsel) {
2398 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
2399 } else if(TIMER_CHVSEL_DISABLE == ccsel) {
2400 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
2401 } else {
2402 /* illegal parameters */
2403 }
2404 }
2405
2406 /*!
2407 \brief configure TIMER output value selection
2408 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2409 \param[in] outsel: output value selection
2410 only one parameter can be selected which is shown as below:
2411 \arg TIMER_OUTSEL_DISABLE: no effect
2412 \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled
2413 \param[out] none
2414 \retval none
2415 */
timer_output_value_selection_config(uint32_t timer_periph,uint16_t outsel)2416 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
2417 {
2418 if(TIMER_OUTSEL_ENABLE == outsel) {
2419 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
2420 } else if(TIMER_OUTSEL_DISABLE == outsel) {
2421 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
2422 } else {
2423 /* illegal parameters */
2424 }
2425 }
2426
2427 /*!
2428 \brief configure TIMER output match pulse selection
2429 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2430 \param[in] channel: TIMER channel
2431 only one parameter can be selected which is shown as below:
2432 \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20)
2433 \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20)
2434 \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20)
2435 \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20)
2436 \param[in] pulsesel: output match pulse selection
2437 only one parameter can be selected which is shown as below:
2438 \arg TIMER_PULSE_OUTPUT_NORMAL: channel output normal
2439 \arg TIMER_PULSE_OUTPUT_CNT_UP: pulse output only when counting up
2440 \arg TIMER_PULSE_OUTPUT_CNT_DOWN: pulse output only when counting down
2441 \arg TIMER_PULSE_OUTPUT_CNT_BOTH: pulse output when counting up or down
2442 \param[out] none
2443 \retval none
2444 */
timer_output_match_pulse_select(uint32_t timer_periph,uint32_t channel,uint16_t pulsesel)2445 void timer_output_match_pulse_select(uint32_t timer_periph, uint32_t channel, uint16_t pulsesel)
2446 {
2447 uint32_t reg;
2448 reg = TIMER_CTL2(timer_periph);
2449
2450 switch(channel) {
2451 /* configure TIMER_CH_0 */
2452 case TIMER_CH_0:
2453 reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 8U));
2454 reg |= (uint32_t)((uint32_t)pulsesel << 8U);
2455 break;
2456 /* configure TIMER_CH_1 */
2457 case TIMER_CH_1:
2458 reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 10U));
2459 reg |= (uint32_t)((uint32_t)pulsesel << 10U);
2460 break;
2461 /* configure TIMER_CH_2 */
2462 case TIMER_CH_2:
2463 reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 12U));
2464 reg |= (uint32_t)((uint32_t)pulsesel << 12U);
2465 break;
2466 /* configure TIMER_CH_3 */
2467 case TIMER_CH_3:
2468 reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 14U));
2469 reg |= (uint32_t)((uint32_t)pulsesel << 14U);
2470 break;
2471 default:
2472 break;
2473 }
2474 TIMER_CTL2(timer_periph) = reg;
2475 }
2476
2477 /*!
2478 \brief configure the TIMER composite PWM mode
2479 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2480 \param[in] channel: TIMER channel
2481 only one parameter can be selected which is shown as below:
2482 \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20)
2483 \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20)
2484 \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20)
2485 \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20)
2486 \param[in] newvalue: ENABLE or DISABLE
2487 \param[out] none
2488 \retval none
2489 */
timer_channel_composite_pwm_mode_config(uint32_t timer_periph,uint32_t channel,ControlStatus newvalue)2490 void timer_channel_composite_pwm_mode_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue)
2491 {
2492 if(ENABLE == newvalue) {
2493 TIMER_CTL2(timer_periph) |= (uint32_t)(TIMER_CTL2_CH0CPWMEN << channel);
2494 } else {
2495 TIMER_CTL2(timer_periph) &= (~(uint32_t)(TIMER_CTL2_CH0CPWMEN << channel));
2496 }
2497 }
2498
2499 /*!
2500 \brief configure the TIMER composite PWM mode output pulse value
2501 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2502 \param[in] channel: TIMER channel
2503 only one parameter can be selected which is shown as below:
2504 \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20)
2505 \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20)
2506 \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20)
2507 \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20)
2508 \param[in] pulse: channel compare value, 0~65535
2509 \param[in] add_pulse: channel additional compare value, 0~65535
2510 \param[out] none
2511 \retval none
2512 */
timer_channel_composite_pwm_mode_output_pulse_value_config(uint32_t timer_periph,uint32_t channel,uint32_t pulse,uint32_t add_pulse)2513 void timer_channel_composite_pwm_mode_output_pulse_value_config(uint32_t timer_periph, uint32_t channel, uint32_t pulse, uint32_t add_pulse)
2514 {
2515 switch(channel) {
2516 /* configure TIMER_CH_0 */
2517 case TIMER_CH_0:
2518 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
2519 TIMER_CH0COMV_ADD(timer_periph) = (uint32_t)add_pulse;
2520 break;
2521 /* configure TIMER_CH_1 */
2522 case TIMER_CH_1:
2523 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
2524 TIMER_CH1COMV_ADD(timer_periph) = (uint32_t)add_pulse;
2525 break;
2526 /* configure TIMER_CH_2 */
2527 case TIMER_CH_2:
2528 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
2529 TIMER_CH2COMV_ADD(timer_periph) = (uint32_t)add_pulse;
2530 break;
2531 /* configure TIMER_CH_3 */
2532 case TIMER_CH_3:
2533 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
2534 TIMER_CH3COMV_ADD(timer_periph) = (uint32_t)add_pulse;
2535 break;
2536 default:
2537 break;
2538 }
2539 }
2540
2541
2542 /*!
2543 \brief configure TIMER channel additional compare value
2544 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2545 \param[in] channel: TIMER channel
2546 only one parameter can be selected which is shown as below:
2547 \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20)
2548 \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20)
2549 \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20)
2550 \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20)
2551 \param[in] value: channel additional compare value, 0~65535
2552 \param[out] none
2553 \retval none
2554 */
timer_channel_additional_compare_value_config(uint32_t timer_periph,uint16_t channel,uint32_t value)2555 void timer_channel_additional_compare_value_config(uint32_t timer_periph, uint16_t channel, uint32_t value)
2556 {
2557 switch(channel) {
2558 /* configure TIMER_CH_0 */
2559 case TIMER_CH_0:
2560 TIMER_CH0COMV_ADD(timer_periph) = (uint32_t)value;
2561 break;
2562 /* configure TIMER_CH_1 */
2563 case TIMER_CH_1:
2564 TIMER_CH1COMV_ADD(timer_periph) = (uint32_t)value;
2565 break;
2566 /* configure TIMER_CH_2 */
2567 case TIMER_CH_2:
2568 TIMER_CH2COMV_ADD(timer_periph) = (uint32_t)value;
2569 break;
2570 /* configure TIMER_CH_3 */
2571 case TIMER_CH_3:
2572 TIMER_CH3COMV_ADD(timer_periph) = (uint32_t)value;
2573 break;
2574 default:
2575 break;
2576 }
2577 }
2578
2579 /*!
2580 \brief configure TIMER channel additional output shadow function
2581 \param[in] timer_periph: TIMERx(x=0,1,7,19,20)
2582 \param[in] channel: TIMER channel
2583 only one parameter can be selected which is shown as below:
2584 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20))
2585 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20))
2586 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20))
2587 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20))
2588 \param[in] aocshadow: channel additional output compare shadow
2589 only one parameter can be selected which is shown as below:
2590 \arg TIMER_ADD_SHADOW_ENABLE: channel additional output compare shadow enable
2591 \arg TIMER_ADD_SHADOW_DISABLE: channel additional output compare shadow disable
2592 \param[out] none
2593 \retval none
2594 */
timer_channel_additional_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t aocshadow)2595 void timer_channel_additional_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t aocshadow)
2596 {
2597 switch(channel) {
2598 /* configure TIMER_CH_0 */
2599 case TIMER_CH_0:
2600 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMADDSEN);
2601 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 28U);
2602 break;
2603 /* configure TIMER_CH_1 */
2604 case TIMER_CH_1:
2605 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMADDSEN);
2606 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 29U);
2607 break;
2608 /* configure TIMER_CH_2 */
2609 case TIMER_CH_2:
2610 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMADDSEN);
2611 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 28U);
2612 break;
2613 /* configure TIMER_CH_3 */
2614 case TIMER_CH_3:
2615 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMADDSEN);
2616 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 29U);
2617 break;
2618 default:
2619 break;
2620 }
2621 }
2622
2623 /*!
2624 \brief initialize TIMER break external input parameter struct with a default value
2625 \param[in] breakinpara: TIMER break external input parameter struct
2626 \param[out] none
2627 \retval none
2628 */
timer_break_external_input_struct_para_init(timer_break_ext_input_struct * breakinpara)2629 void timer_break_external_input_struct_para_init(timer_break_ext_input_struct *breakinpara)
2630 {
2631 /* initialize the break parameter struct member with the default value */
2632 breakinpara->filter = 0U;
2633 breakinpara->enable = TIMER_IOS_STATE_DISABLE;
2634 breakinpara->polarity = TIMER_BRKIN_POLARITY_LOW;
2635 }
2636
2637 /*!
2638 \brief configure break external input
2639 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2640 \param[in] break_input: break external input
2641 only one parameter can be selected which is shown as below:
2642 \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0
2643 \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1
2644 \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2
2645 \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3
2646 \param[in] breakinpara: break external input parameter struct
2647 filter:: 0~15
2648 enable: ENABLE or DISABLE
2649 polarity: TIMER_BRKIN_POLARITY_HIGH, TIMER_BRKIN_POLARITY_LOW
2650 \param[out] none
2651 \retval none
2652 */
timer_break_external_input_config(uint32_t timer_periph,uint32_t break_input,timer_break_ext_input_struct * breakinpara)2653 void timer_break_external_input_config(uint32_t timer_periph, uint32_t break_input, timer_break_ext_input_struct *breakinpara)
2654 {
2655 uint32_t reg = 0U;
2656 reg = TIMER_BRKCFG(timer_periph);
2657 reg &= (~(uint32_t)((0x03000000U << (break_input << 1U) | ((uint32_t)0x0000000FU << (break_input << 2U)))));
2658
2659 reg |= ((breakinpara->filter << (break_input << 2U)) |
2660 (breakinpara->enable << ((break_input << 1U) + 24U)) |
2661 (breakinpara->polarity << ((break_input << 1U) + 25U)));
2662
2663 TIMER_BRKCFG(timer_periph) = reg;
2664 }
2665
2666 /*!
2667 \brief break external input enable
2668 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2669 \param[in] break_input: break external input
2670 only one parameter can be selected which is shown as below:
2671 \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0
2672 \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1
2673 \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2
2674 \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3
2675 \param[out] none
2676 \retval none
2677 */
timer_break_external_input_enable(uint32_t timer_periph,uint32_t break_input)2678 void timer_break_external_input_enable(uint32_t timer_periph, uint32_t break_input)
2679 {
2680 TIMER_BRKCFG(timer_periph) |= (uint32_t)(TIMER_BRKCFG_BRK0EN << (break_input << 1U));
2681 }
2682
2683 /*!
2684 \brief break external input disable
2685 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2686 \param[in] break_input: break external input
2687 only one parameter can be selected which is shown as below:
2688 \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0
2689 \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1
2690 \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2
2691 \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3
2692 \param[out] none
2693 \retval none
2694 */
timer_break_external_input_disable(uint32_t timer_periph,uint32_t break_input)2695 void timer_break_external_input_disable(uint32_t timer_periph, uint32_t break_input)
2696 {
2697 TIMER_BRKCFG(timer_periph) &= (~(uint32_t)(TIMER_BRKCFG_BRK0EN << (break_input << 1U)));
2698 }
2699
2700 /*!
2701 \brief configure TIMER break external input polarity
2702 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2703 \param[in] break_input: break external input
2704 only one parameter can be selected which is shown as below:
2705 \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0(TIMERx(x=0,7,19,20)
2706 \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1(TIMERx(x=0,7,19,20)
2707 \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2(TIMERx(x=0,7,19,20)
2708 \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3(TIMERx(x=0,7,19,20)
2709 \param[in] polarity: break external input polarity
2710 only one parameter can be selected which is shown as below:
2711 \arg TIMER_BRKIN_POLARITY_HIGH: break external input polarity is high
2712 \arg TIMER_BRKIN_POLARITY_LOW: break external input polarity is low
2713 \param[out] none
2714 \retval none
2715 */
timer_break_external_input_polarity_config(uint32_t timer_periph,uint32_t break_input,uint32_t polarity)2716 void timer_break_external_input_polarity_config(uint32_t timer_periph, uint32_t break_input, uint32_t polarity)
2717 {
2718 if(polarity == TIMER_BRKIN_POLARITY_HIGH) {
2719 TIMER_BRKCFG(timer_periph) |= (uint32_t)(TIMER_BRKCFG_BRK0P << (break_input << 1U));
2720 } else {
2721 TIMER_BRKCFG(timer_periph) &= (~(uint32_t)(TIMER_BRKCFG_BRK0P << (break_input << 1U)));
2722 }
2723 }
2724
2725 /*!
2726 \brief configure the TIMER channel break function
2727 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2728 \param[in] channel: TIMER channel
2729 only one parameter can be selected which is shown as below:
2730 \arg TIMER_CH_0: TIMER channel 0
2731 \arg TIMER_CH_1: TIMER channel 1
2732 \arg TIMER_CH_2: TIMER channel 2
2733 \arg TIMER_CH_3: TIMER channel 3
2734 \param[in] newvalue: ENABLE or DISABLE
2735 \param[out] none
2736 \retval none
2737 */
timer_channel_break_control_config(uint32_t timer_periph,uint32_t channel,ControlStatus newvalue)2738 void timer_channel_break_control_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue)
2739 {
2740 if(ENABLE == newvalue) {
2741 TIMER_CTL2(timer_periph) |= (uint32_t)(TIMER_CTL2_BRKENCH0 << channel);
2742 } else {
2743 TIMER_CTL2(timer_periph) &= (~(uint32_t)(TIMER_CTL2_BRKENCH0 << channel));
2744 }
2745 }
2746
2747 /*!
2748 \brief configure the TIMER channel free dead time function
2749 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2750 \param[in] channel: TIMER channel
2751 only one parameter can be selected which is shown as below:
2752 \arg TIMER_CH_0: TIMER channel 0
2753 \arg TIMER_CH_1: TIMER channel 1
2754 \arg TIMER_CH_2: TIMER channel 2
2755 \arg TIMER_CH_3: TIMER channel 3
2756 \param[in] newvalue: ENABLE or DISABLE
2757 \param[out] none
2758 \retval none
2759 */
timer_channel_dead_time_config(uint32_t timer_periph,uint32_t channel,ControlStatus newvalue)2760 void timer_channel_dead_time_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue)
2761 {
2762 if(ENABLE == newvalue) {
2763 TIMER_CTL2(timer_periph) |= (uint32_t)(TIMER_CTL2_DTIENCH0 << channel);
2764 } else {
2765 TIMER_CTL2(timer_periph) &= (~(uint32_t)(TIMER_CTL2_DTIENCH0 << channel));
2766 }
2767 }
2768
2769 /*!
2770 \brief initialize TIMER channel free complementary parameter struct with a default value
2771 \param[in] none
2772 \param[out] freecompara: TIMER channel free complementary parameter struct
2773 \retval none
2774 */
timer_free_complementary_struct_para_init(timer_free_complementary_parameter_struct * freecompara)2775 void timer_free_complementary_struct_para_init(timer_free_complementary_parameter_struct *freecompara)
2776 {
2777 /* initialize the channel free complementary parameter struct member with the default value */
2778 freecompara->freecomstate = TIMER_FCCHP_STATE_DISABLE;
2779 freecompara->runoffstate = TIMER_ROS_STATE_DISABLE;
2780 freecompara->ideloffstate = TIMER_IOS_STATE_DISABLE;
2781 freecompara->deadtime = 0U;
2782 }
2783
2784 /*!
2785 \brief configure channel free complementary protection
2786 \param[in] timer_periph: TIMERx(x=0,7,19,20)
2787 \param[in] channel: TIMER channel
2788 only one parameter can be selected which is shown as below:
2789 \arg TIMER_CH_0: TIMER channel 0
2790 \arg TIMER_CH_1: TIMER channel 1
2791 \arg TIMER_CH_2: TIMER channel 2
2792 \arg TIMER_CH_3: TIMER channel 3
2793 \param[in] fcpara: TIMER channel free complementary parameter struct
2794 freecomstate: TIMER_FCCHP_STATE_ENABLE, TIMER_FCCHP_STATE_DISABLE
2795 runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE
2796 ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE
2797 deadtime: 0~255
2798 \param[out] none
2799 \retval none
2800 */
timer_channel_free_complementary_config(uint32_t timer_periph,uint16_t channel,timer_free_complementary_parameter_struct * fcpara)2801 void timer_channel_free_complementary_config(uint32_t timer_periph, uint16_t channel, timer_free_complementary_parameter_struct *fcpara)
2802 {
2803 switch(channel) {
2804 case TIMER_CH_0:
2805 TIMER_FCCHP0(timer_periph) &= (~(uint32_t)(TIMER_FCCHP0_DTCFG | TIMER_FCCHP0_IOS | TIMER_FCCHP0_ROS | TIMER_FCCHP0_FCCHP0EN));
2806 TIMER_FCCHP0(timer_periph) |= fcpara->deadtime;
2807 TIMER_FCCHP0(timer_periph) |= fcpara->ideloffstate;
2808 TIMER_FCCHP0(timer_periph) |= fcpara->runoffstate;
2809 TIMER_FCCHP0(timer_periph) |= fcpara->freecomstate;
2810 break;
2811 case TIMER_CH_1:
2812 TIMER_FCCHP1(timer_periph) &= (~(uint32_t)(TIMER_FCCHP1_DTCFG | TIMER_FCCHP1_IOS | TIMER_FCCHP1_ROS | TIMER_FCCHP1_FCCHP1EN));
2813 TIMER_FCCHP1(timer_periph) |= fcpara->deadtime;
2814 TIMER_FCCHP1(timer_periph) |= fcpara->ideloffstate;
2815 TIMER_FCCHP1(timer_periph) |= fcpara->runoffstate;
2816 TIMER_FCCHP1(timer_periph) |= fcpara->freecomstate;
2817 break;
2818 case TIMER_CH_2:
2819 TIMER_FCCHP2(timer_periph) &= (~(uint32_t)(TIMER_FCCHP2_DTCFG | TIMER_FCCHP2_IOS | TIMER_FCCHP2_ROS | TIMER_FCCHP2_FCCHP2EN));
2820 TIMER_FCCHP2(timer_periph) |= fcpara->deadtime;
2821 TIMER_FCCHP2(timer_periph) |= fcpara->ideloffstate;
2822 TIMER_FCCHP2(timer_periph) |= fcpara->runoffstate;
2823 TIMER_FCCHP2(timer_periph) |= fcpara->freecomstate;
2824 break;
2825 case TIMER_CH_3:
2826 TIMER_FCCHP3(timer_periph) &= (~(uint32_t)(TIMER_FCCHP3_DTCFG | TIMER_FCCHP3_IOS | TIMER_FCCHP3_ROS | TIMER_FCCHP3_FCCHP3EN));
2827 TIMER_FCCHP3(timer_periph) |= fcpara->deadtime;
2828 TIMER_FCCHP3(timer_periph) |= fcpara->ideloffstate;
2829 TIMER_FCCHP3(timer_periph) |= fcpara->runoffstate;
2830 TIMER_FCCHP3(timer_periph) |= fcpara->freecomstate;
2831 break;
2832 default:
2833 break;
2834 }
2835 }
2836
2837 /*!
2838 \brief get TIMER flags
2839 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
2840 \param[in] flag: the TIMER flags
2841 only one parameter can be selected which is shown as below:
2842 \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,1,5,6,7,19,20)
2843 \arg TIMER_FLAG_CH0: channel 0 capture or compare flag, TIMERx(x=0,1,7,19,20)
2844 \arg TIMER_FLAG_CH1: channel 1 capture or compare flag, TIMERx(x=0,1,7,19,20)
2845 \arg TIMER_FLAG_CH2: channel 2 capture or compare flag, TIMERx(x=0,1,7,19,20)
2846 \arg TIMER_FLAG_CH3: channel 3 capture or compare flag, TIMERx(x=0,1,7,19,20)
2847 \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0,7,19,20)
2848 \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,1,7,19,20)
2849 \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0,7,19,20)
2850 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,1,7,19,20)
2851 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,1,7,19,20)
2852 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,1,7,19,20)
2853 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,1,7,19,20)
2854 \arg TIMER_FLAG_MCH0: multi mode channel 0 capture or compare flag, TIMERx(x=0,7,19,20)
2855 \arg TIMER_FLAG_MCH1: multi mode channel 1 capture or compare flag, TIMERx(x=0,7,19,20)
2856 \arg TIMER_FLAG_MCH2: multi mode channel 2 capture or compare flag, TIMERx(x=0,7,19,20)
2857 \arg TIMER_FLAG_MCH3: multi mode channel 3 capture or compare flag, TIMERx(x=0,7,19,20)
2858 \arg TIMER_FLAG_MCH0O: multi mode channel 0 overcapture flag, TIMERx(x=0,7,19,20)
2859 \arg TIMER_FLAG_MCH1O: multi mode channel 1 overcapture flag, TIMERx(x=0,7,19,20)
2860 \arg TIMER_FLAG_MCH2O: multi mode channel 2 overcapture flag, TIMERx(x=0,7,19,20)
2861 \arg TIMER_FLAG_MCH3O: multi mode channel 3 overcapture flag, TIMERx(x=0,7,19,20)
2862 \arg TIMER_FLAG_CH0COMADD: channel 0 additional compare flag, TIMERx(x=0,7,19,20)
2863 \arg TIMER_FLAG_CH1COMADD: channel 1 additional compare flag, TIMERx(x=0,7,19,20)
2864 \arg TIMER_FLAG_CH2COMADD: channel 2 additional compare flag, TIMERx(x=0,7,19,20)
2865 \arg TIMER_FLAG_CH3COMADD: channel 3 additional compare flag, TIMERx(x=0,7,19,20)
2866 \param[out] none
2867 \retval FlagStatus: SET or RESET
2868 */
timer_flag_get(uint32_t timer_periph,uint32_t flag)2869 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
2870 {
2871 if((uint32_t)RESET != (TIMER_INTF(timer_periph) & flag)) {
2872 return SET;
2873 } else {
2874 return RESET;
2875 }
2876 }
2877
2878 /*!
2879 \brief clear TIMER flags
2880 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
2881 \param[in] flag: the TIMER flags
2882 one or more parameters can be selected which are shown as below:
2883 \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,1,5,6,7,19,20)
2884 \arg TIMER_FLAG_CH0: channel 0 capture or compare flag, TIMERx(x=0,1,7,19,20)
2885 \arg TIMER_FLAG_CH1: channel 1 capture or compare flag, TIMERx(x=0,1,7,19,20)
2886 \arg TIMER_FLAG_CH2: channel 2 capture or compare flag, TIMERx(x=0,1,7,19,20)
2887 \arg TIMER_FLAG_CH3: channel 3 capture or compare flag, TIMERx(x=0,1,7,19,20)
2888 \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0,7,19,20)
2889 \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,1,7,19,20)
2890 \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0,7,19,20)
2891 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,1,7,19,20)
2892 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,1,7,19,20)
2893 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,1,7,19,20)
2894 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,1,7,19,20)
2895 \arg TIMER_FLAG_MCH0: multi mode channel 0 capture or compare flag, TIMERx(x=0,7,19,20)
2896 \arg TIMER_FLAG_MCH1: multi mode channel 1 capture or compare flag, TIMERx(x=0,7,19,20)
2897 \arg TIMER_FLAG_MCH2: multi mode channel 2 capture or compare flag, TIMERx(x=0,7,19,20)
2898 \arg TIMER_FLAG_MCH3: multi mode channel 3 capture or compare flag, TIMERx(x=0,7,19,20)
2899 \arg TIMER_FLAG_MCH0O: multi mode channel 0 overcapture flag, TIMERx(x=0,7,19,20)
2900 \arg TIMER_FLAG_MCH1O: multi mode channel 1 overcapture flag, TIMERx(x=0,7,19,20)
2901 \arg TIMER_FLAG_MCH2O: multi mode channel 2 overcapture flag, TIMERx(x=0,7,19,20)
2902 \arg TIMER_FLAG_MCH3O: multi mode channel 3 overcapture flag, TIMERx(x=0,7,19,20)
2903 \arg TIMER_FLAG_CH0COMADD: channel 0 additional compare flag, TIMERx(x=0,7,19,20)
2904 \arg TIMER_FLAG_CH1COMADD: channel 1 additional compare flag, TIMERx(x=0,7,19,20)
2905 \arg TIMER_FLAG_CH2COMADD: channel 2 additional compare flag, TIMERx(x=0,7,19,20)
2906 \arg TIMER_FLAG_CH3COMADD: channel 3 additional compare flag, TIMERx(x=0,7,19,20)
2907 \param[out] none
2908 \retval none
2909 */
timer_flag_clear(uint32_t timer_periph,uint32_t flag)2910 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
2911 {
2912 TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
2913 }
2914
2915 /*!
2916 \brief enable the TIMER interrupt
2917 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
2918 \param[in] interrupt: timer interrupt source
2919 one or more parameters can be selected which are shown as below:
2920 \arg TIMER_INT_UP: update interrupt, TIMERx(x=0,1,5,6,7,19,20)
2921 \arg TIMER_INT_CH0: channel 0 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2922 \arg TIMER_INT_CH1: channel 1 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2923 \arg TIMER_INT_CH2: channel 2 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2924 \arg TIMER_INT_CH3: channel 3 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2925 \arg TIMER_INT_CMT: commutation interrupt, TIMERx(x=0,7,19,20)
2926 \arg TIMER_INT_TRG: trigger interrupt, TIMERx(x=0,1,7,19,20)
2927 \arg TIMER_INT_BRK: break interrupt, TIMERx(x=0,7,19,20)
2928 \arg TIMER_INT_MCH0: multi mode channel 0 capture or compare interrupt, TIMERx(x=0,7,19,20)
2929 \arg TIMER_INT_MCH1: multi mode channel 1 capture or compare interrupt, TIMERx(x=0,7,19,20)
2930 \arg TIMER_INT_MCH2: multi mode channel 2 capture or compare interrupt, TIMERx(x=0,7,19,20)
2931 \arg TIMER_INT_MCH3: multi mode channel 3 capture or compare interrupt, TIMERx(x=0,7,19,20)
2932 \arg TIMER_INT_CH0COMADD: channel 0 additional compare interrupt, TIMERx(x=0,7,19,20)
2933 \arg TIMER_INT_CH1COMADD: channel 1 additional compare interrupt, TIMERx(x=0,7,19,20)
2934 \arg TIMER_INT_CH2COMADD: channel 2 additional compare interrupt, TIMERx(x=0,7,19,20)
2935 \arg TIMER_INT_CH3COMADD: channel 3 additional compare interrupt, TIMERx(x=0,7,19,20)
2936 \param[out] none
2937 \retval none
2938 */
timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt)2939 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
2940 {
2941 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
2942 }
2943
2944 /*!
2945 \brief disable the TIMER interrupt
2946 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
2947 \param[in] interrupt: timer interrupt source
2948 one or more parameters can be selected which are shown as below:
2949 \arg TIMER_INT_UP: update interrupt, TIMERx(x=0,1,5,6,7,19,20)
2950 \arg TIMER_INT_CH0: channel 0 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2951 \arg TIMER_INT_CH1: channel 1 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2952 \arg TIMER_INT_CH2: channel 2 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2953 \arg TIMER_INT_CH3: channel 3 capture or compare interrupt, TIMERx(x=0,1,7,19,20)
2954 \arg TIMER_INT_CMT: commutation interrupt, TIMERx(x=0,7,19,20)
2955 \arg TIMER_INT_TRG: trigger interrupt, TIMERx(x=0,1,7,19,20)
2956 \arg TIMER_INT_BRK: break interrupt, TIMERx(x=0,7,19,20)
2957 \arg TIMER_INT_MCH0: multi mode channel 0 capture or compare interrupt, TIMERx(x=0,7,19,20)
2958 \arg TIMER_INT_MCH1: multi mode channel 1 capture or compare interrupt, TIMERx(x=0,7,19,20)
2959 \arg TIMER_INT_MCH2: multi mode channel 2 capture or compare interrupt, TIMERx(x=0,7,19,20)
2960 \arg TIMER_INT_MCH3: multi mode channel 3 capture or compare interrupt, TIMERx(x=0,7,19,20)
2961 \arg TIMER_INT_CH0COMADD: channel 0 additional compare interrupt, TIMERx(x=0,7,19,20)
2962 \arg TIMER_INT_CH1COMADD: channel 1 additional compare interrupt, TIMERx(x=0,7,19,20)
2963 \arg TIMER_INT_CH2COMADD: channel 2 additional compare interrupt, TIMERx(x=0,7,19,20)
2964 \arg TIMER_INT_CH3COMADD: channel 3 additional compare interrupt, TIMERx(x=0,7,19,20)
2965 \param[out] none
2966 \retval none
2967 */
timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt)2968 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
2969 {
2970 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
2971 }
2972
2973 /*!
2974 \brief get timer interrupt flags
2975 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
2976 \param[in] int_flag: the timer interrupt flags
2977 only one parameter can be selected which is shown as below:
2978 \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,1,5,6,7,19,20)
2979 \arg TIMER_INT_FLAG_CH0: channel 0 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
2980 \arg TIMER_INT_FLAG_CH1: channel 1 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
2981 \arg TIMER_INT_FLAG_CH2: channel 2 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
2982 \arg TIMER_INT_FLAG_CH3: channel 3 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
2983 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,7,19,20)
2984 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,1,7,19,20)
2985 \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,7,19,20)
2986 \arg TIMER_INT_FLAG_MCH0: multi mode channel 0 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
2987 \arg TIMER_INT_FLAG_MCH1: multi mode channel 1 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
2988 \arg TIMER_INT_FLAG_MCH2: multi mode channel 2 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
2989 \arg TIMER_INT_FLAG_MCH3: multi mode channel 3 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
2990 \arg TIMER_INT_FLAG_CH0COMADD: channel 0 additional compare interrupt flag, TIMERx(x=0,7,19,20)
2991 \arg TIMER_INT_FLAG_CH1COMADD: channel 1 additional compare interrupt flag, TIMERx(x=0,7,19,20)
2992 \arg TIMER_INT_FLAG_CH2COMADD: channel 2 additional compare interrupt flag, TIMERx(x=0,7,19,20)
2993 \arg TIMER_INT_FLAG_CH3COMADD: channel 3 additional compare interrupt flag, TIMERx(x=0,7,19,20)
2994 \param[out] none
2995 \retval FlagStatus: SET or RESET
2996 */
timer_interrupt_flag_get(uint32_t timer_periph,uint32_t int_flag)2997 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag)
2998 {
2999 uint32_t val;
3000 val = (TIMER_DMAINTEN(timer_periph) & int_flag);
3001 if(((uint32_t)RESET != (TIMER_INTF(timer_periph) & int_flag)) && ((uint32_t)RESET != val)) {
3002 return SET;
3003 } else {
3004 return RESET;
3005 }
3006 }
3007
3008 /*!
3009 \brief clear TIMER interrupt flags
3010 \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20)
3011 \param[in] int_flag: the timer interrupt flags
3012 one or more parameters can be selected which are shown as below:
3013 \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,1,5,6,7,19,20)
3014 \arg TIMER_INT_FLAG_CH0: channel 0 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
3015 \arg TIMER_INT_FLAG_CH1: channel 1 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
3016 \arg TIMER_INT_FLAG_CH2: channel 2 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
3017 \arg TIMER_INT_FLAG_CH3: channel 3 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20)
3018 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,7,19,20)
3019 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,1,7,19,20)
3020 \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,7,19,20)
3021 \arg TIMER_INT_FLAG_MCH0: multi mode channel 0 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
3022 \arg TIMER_INT_FLAG_MCH1: multi mode channel 1 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
3023 \arg TIMER_INT_FLAG_MCH2: multi mode channel 2 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
3024 \arg TIMER_INT_FLAG_MCH3: multi mode channel 3 capture or compare interrupt flag, TIMERx(x=0,7,19,20)
3025 \arg TIMER_INT_FLAG_CH0COMADD: channel 0 additional compare interrupt flag, TIMERx(x=0,7,19,20)
3026 \arg TIMER_INT_FLAG_CH1COMADD: channel 1 additional compare interrupt flag, TIMERx(x=0,7,19,20)
3027 \arg TIMER_INT_FLAG_CH2COMADD: channel 2 additional compare interrupt flag, TIMERx(x=0,7,19,20)
3028 \arg TIMER_INT_FLAG_CH3COMADD: channel 3 additional compare interrupt flag, TIMERx(x=0,7,19,20)
3029 \param[out] none
3030 \retval none
3031 */
timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t int_flag)3032 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag)
3033 {
3034 TIMER_INTF(timer_periph) &= (~(uint32_t)int_flag);
3035 }
3036
