1 /* 2 * SPDX-FileCopyrightText: Copyright 2019-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Licensed under the Apache License, Version 2.0 (the License); you may 6 * not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 13 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef PMU_ETHOSU_H 19 #define PMU_ETHOSU_H 20 21 /***************************************************************************** 22 * Includes 23 *****************************************************************************/ 24 #include <stdint.h> 25 26 #include "ethosu_driver.h" 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /***************************************************************************** 33 * Defines 34 *****************************************************************************/ 35 #ifdef ETHOSU85 36 #define ETHOSU_PMU_NCOUNTERS 8 37 #else 38 #define ETHOSU_PMU_NCOUNTERS 4 39 #endif 40 41 #define ETHOSU_PMU_CNT1_Msk (1UL << 0) 42 #define ETHOSU_PMU_CNT2_Msk (1UL << 1) 43 #define ETHOSU_PMU_CNT3_Msk (1UL << 2) 44 #define ETHOSU_PMU_CNT4_Msk (1UL << 3) 45 #ifdef ETHOSU85 46 #define ETHOSU_PMU_CNT5_Msk (1UL << 4) 47 #define ETHOSU_PMU_CNT6_Msk (1UL << 5) 48 #define ETHOSU_PMU_CNT7_Msk (1UL << 6) 49 #define ETHOSU_PMU_CNT8_Msk (1UL << 7) 50 #endif 51 52 #define ETHOSU_PMU_CCNT_Msk (1UL << 31) 53 54 /***************************************************************************** 55 * Types 56 *****************************************************************************/ 57 58 /** \brief HW Supported ETHOSU PMU Events 59 * 60 * Note: These values are symbolic. Actual HW-values may change. I.e. always use API 61 * to set/get actual event-type value. 62 * */ 63 #if defined(ETHOSU55) || defined(ETHOSU65) 64 enum ethosu_pmu_event_type 65 { 66 ETHOSU_PMU_NO_EVENT = 0, 67 ETHOSU_PMU_CYCLE, 68 ETHOSU_PMU_NPU_IDLE, 69 ETHOSU_PMU_CC_STALLED_ON_BLOCKDEP, 70 ETHOSU_PMU_CC_STALLED_ON_SHRAM_RECONFIG, 71 ETHOSU_PMU_NPU_ACTIVE, 72 ETHOSU_PMU_MAC_ACTIVE, 73 ETHOSU_PMU_MAC_ACTIVE_8BIT, 74 ETHOSU_PMU_MAC_ACTIVE_16BIT, 75 ETHOSU_PMU_MAC_DPU_ACTIVE, 76 ETHOSU_PMU_MAC_STALLED_BY_WD_ACC, 77 ETHOSU_PMU_MAC_STALLED_BY_WD, 78 ETHOSU_PMU_MAC_STALLED_BY_ACC, 79 ETHOSU_PMU_MAC_STALLED_BY_IB, 80 ETHOSU_PMU_MAC_ACTIVE_32BIT, 81 ETHOSU_PMU_MAC_STALLED_BY_INT_W, 82 ETHOSU_PMU_MAC_STALLED_BY_INT_ACC, 83 ETHOSU_PMU_AO_ACTIVE, 84 ETHOSU_PMU_AO_ACTIVE_8BIT, 85 ETHOSU_PMU_AO_ACTIVE_16BIT, 86 ETHOSU_PMU_AO_STALLED_BY_OFMP_OB, 87 ETHOSU_PMU_AO_STALLED_BY_OFMP, 88 ETHOSU_PMU_AO_STALLED_BY_OB, 89 ETHOSU_PMU_AO_STALLED_BY_ACC_IB, 90 ETHOSU_PMU_AO_STALLED_BY_ACC, 91 ETHOSU_PMU_AO_STALLED_BY_IB, 92 ETHOSU_PMU_WD_ACTIVE, 93 ETHOSU_PMU_WD_STALLED, 94 ETHOSU_PMU_WD_STALLED_BY_WS, 95 ETHOSU_PMU_WD_STALLED_BY_WD_BUF, 96 ETHOSU_PMU_WD_PARSE_ACTIVE, 97 ETHOSU_PMU_WD_PARSE_STALLED, 98 ETHOSU_PMU_WD_PARSE_STALLED_IN, 99 ETHOSU_PMU_WD_PARSE_STALLED_OUT, 100 ETHOSU_PMU_WD_TRANS_WS, 101 ETHOSU_PMU_WD_TRANS_WB, 102 ETHOSU_PMU_WD_TRANS_DW0, 103 ETHOSU_PMU_WD_TRANS_DW1, 104 ETHOSU_PMU_AXI0_RD_TRANS_ACCEPTED, 105 ETHOSU_PMU_AXI0_RD_TRANS_COMPLETED, 106 ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED, 107 ETHOSU_PMU_AXI0_RD_TRAN_REQ_STALLED, 108 ETHOSU_PMU_AXI0_WR_TRANS_ACCEPTED, 109 ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_M, 110 ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_S, 111 ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN, 112 ETHOSU_PMU_AXI0_WR_TRAN_REQ_STALLED, 113 ETHOSU_PMU_AXI0_WR_DATA_BEAT_STALLED, 114 ETHOSU_PMU_AXI0_ENABLED_CYCLES, 115 ETHOSU_PMU_AXI0_RD_STALL_LIMIT, 116 ETHOSU_PMU_AXI0_WR_STALL_LIMIT, 117 ETHOSU_PMU_AXI_LATENCY_ANY, 118 ETHOSU_PMU_AXI_LATENCY_32, 119 ETHOSU_PMU_AXI_LATENCY_64, 120 ETHOSU_PMU_AXI_LATENCY_128, 121 ETHOSU_PMU_AXI_LATENCY_256, 122 ETHOSU_PMU_AXI_LATENCY_512, 123 ETHOSU_PMU_AXI_LATENCY_1024, 124 ETHOSU_PMU_ECC_DMA, 125 ETHOSU_PMU_ECC_SB0, 126 ETHOSU_PMU_AXI1_RD_TRANS_ACCEPTED, 127 ETHOSU_PMU_AXI1_RD_TRANS_COMPLETED, 128 ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED, 129 ETHOSU_PMU_AXI1_RD_TRAN_REQ_STALLED, 130 ETHOSU_PMU_AXI1_WR_TRANS_ACCEPTED, 131 ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_M, 132 ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_S, 133 ETHOSU_PMU_AXI1_WR_DATA_BEAT_WRITTEN, 134 ETHOSU_PMU_AXI1_WR_TRAN_REQ_STALLED, 135 ETHOSU_PMU_AXI1_WR_DATA_BEAT_STALLED, 136 ETHOSU_PMU_AXI1_ENABLED_CYCLES, 137 ETHOSU_PMU_AXI1_RD_STALL_LIMIT, 138 ETHOSU_PMU_AXI1_WR_STALL_LIMIT, 139 ETHOSU_PMU_ECC_SB1, 140 141 ETHOSU_PMU_SENTINEL // End-marker (not event) 142 }; 143 #elif defined(ETHOSU85) 144 enum ethosu_pmu_event_type 145 { 146 ETHOSU_PMU_NO_EVENT = 0, 147 ETHOSU_PMU_CYCLE, 148 ETHOSU_PMU_NPU_IDLE, 149 ETHOSU_PMU_CC_STALLED_ON_BLOCKDEP, 150 ETHOSU_PMU_NPU_ACTIVE, 151 ETHOSU_PMU_MAC_ACTIVE, 152 ETHOSU_PMU_MAC_DPU_ACTIVE, 153 ETHOSU_PMU_MAC_STALLED_BY_W_OR_ACC, 154 ETHOSU_PMU_MAC_STALLED_BY_W, 155 ETHOSU_PMU_MAC_STALLED_BY_ACC, 156 ETHOSU_PMU_MAC_STALLED_BY_IB, 157 ETHOSU_PMU_AO_ACTIVE, 158 ETHOSU_PMU_AO_STALLED_BY_BS_OR_OB, 159 ETHOSU_PMU_AO_STALLED_BY_BS, 160 ETHOSU_PMU_AO_STALLED_BY_OB, 161 ETHOSU_PMU_AO_STALLED_BY_AB_OR_CB, 162 ETHOSU_PMU_AO_STALLED_BY_AB, 163 ETHOSU_PMU_AO_STALLED_BY_CB, 164 ETHOSU_PMU_WD_ACTIVE, 165 ETHOSU_PMU_WD_STALLED, 166 ETHOSU_PMU_WD_STALLED_BY_WD_BUF, 167 ETHOSU_PMU_WD_STALLED_BY_WS_FC, 168 ETHOSU_PMU_WD_STALLED_BY_WS_TC, 169 ETHOSU_PMU_WD_TRANS_WBLK, 170 ETHOSU_PMU_WD_TRANS_WS_FC, 171 ETHOSU_PMU_WD_TRANS_WS_TC, 172 ETHOSU_PMU_WD_STALLED_BY_WS_SC0, 173 ETHOSU_PMU_WD_STALLED_BY_WS_SC1, 174 ETHOSU_PMU_WD_STALLED_BY_WS_SC2, 175 ETHOSU_PMU_WD_STALLED_BY_WS_SC3, 176 ETHOSU_PMU_WD_PARSE_ACTIVE_SC0, 177 ETHOSU_PMU_WD_PARSE_ACTIVE_SC1, 178 ETHOSU_PMU_WD_PARSE_ACTIVE_SC2, 179 ETHOSU_PMU_WD_PARSE_ACTIVE_SC3, 180 ETHOSU_PMU_WD_PARSE_STALL_SC0, 181 ETHOSU_PMU_WD_PARSE_STALL_SC1, 182 ETHOSU_PMU_WD_PARSE_STALL_SC2, 183 ETHOSU_PMU_WD_PARSE_STALL_SC3, 184 ETHOSU_PMU_WD_PARSE_STALL_IN_SC0, 185 ETHOSU_PMU_WD_PARSE_STALL_IN_SC1, 186 ETHOSU_PMU_WD_PARSE_STALL_IN_SC2, 187 ETHOSU_PMU_WD_PARSE_STALL_IN_SC3, 188 ETHOSU_PMU_WD_PARSE_STALL_OUT_SC0, 189 ETHOSU_PMU_WD_PARSE_STALL_OUT_SC1, 190 ETHOSU_PMU_WD_PARSE_STALL_OUT_SC2, 191 ETHOSU_PMU_WD_PARSE_STALL_OUT_SC3, 192 ETHOSU_PMU_WD_TRANS_WS_SC0, 193 ETHOSU_PMU_WD_TRANS_WS_SC1, 194 ETHOSU_PMU_WD_TRANS_WS_SC2, 195 ETHOSU_PMU_WD_TRANS_WS_SC3, 196 ETHOSU_PMU_WD_TRANS_WB0, 197 ETHOSU_PMU_WD_TRANS_WB1, 198 ETHOSU_PMU_WD_TRANS_WB2, 199 ETHOSU_PMU_WD_TRANS_WB3, 200 ETHOSU_PMU_SRAM_RD_TRANS_ACCEPTED, 201 ETHOSU_PMU_SRAM_RD_TRANS_COMPLETED, 202 ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED, 203 ETHOSU_PMU_SRAM_RD_TRAN_REQ_STALLED, 204 ETHOSU_PMU_SRAM_WR_TRANS_ACCEPTED, 205 ETHOSU_PMU_SRAM_WR_TRANS_COMPLETED_M, 206 ETHOSU_PMU_SRAM_WR_TRANS_COMPLETED_S, 207 ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN, 208 ETHOSU_PMU_SRAM_WR_TRAN_REQ_STALLED, 209 ETHOSU_PMU_SRAM_WR_DATA_BEAT_STALLED, 210 ETHOSU_PMU_SRAM_ENABLED_CYCLES, 211 ETHOSU_PMU_SRAM_RD_STALL_LIMIT, 212 ETHOSU_PMU_SRAM_WR_STALL_LIMIT, 213 ETHOSU_PMU_AXI_LATENCY_ANY, 214 ETHOSU_PMU_AXI_LATENCY_32, 215 ETHOSU_PMU_AXI_LATENCY_64, 216 ETHOSU_PMU_AXI_LATENCY_128, 217 ETHOSU_PMU_AXI_LATENCY_256, 218 ETHOSU_PMU_AXI_LATENCY_512, 219 ETHOSU_PMU_AXI_LATENCY_1024, 220 ETHOSU_PMU_ECC_DMA, 221 ETHOSU_PMU_ECC_MAC_IB, 222 ETHOSU_PMU_ECC_MAC_AB, 223 ETHOSU_PMU_ECC_AO_CB, 224 ETHOSU_PMU_ECC_AO_OB, 225 ETHOSU_PMU_ECC_AO_LUT, 226 ETHOSU_PMU_EXT_RD_TRANS_ACCEPTED, 227 ETHOSU_PMU_EXT_RD_TRANS_COMPLETED, 228 ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED, 229 ETHOSU_PMU_EXT_RD_TRAN_REQ_STALLED, 230 ETHOSU_PMU_EXT_WR_TRANS_ACCEPTED, 231 ETHOSU_PMU_EXT_WR_TRANS_COMPLETED_M, 232 ETHOSU_PMU_EXT_WR_TRANS_COMPLETED_S, 233 ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN, 234 ETHOSU_PMU_EXT_WR_TRAN_REQ_STALLED, 235 ETHOSU_PMU_EXT_WR_DATA_BEAT_STALLED, 236 ETHOSU_PMU_EXT_ENABLED_CYCLES, 237 ETHOSU_PMU_EXT_RD_STALL_LIMIT, 238 ETHOSU_PMU_EXT_WR_STALL_LIMIT, 239 ETHOSU_PMU_SRAM0_RD_TRANS_ACCEPTED, 240 ETHOSU_PMU_SRAM0_RD_TRANS_COMPLETED, 241 ETHOSU_PMU_SRAM0_RD_DATA_BEAT_RECEIVED, 242 ETHOSU_PMU_SRAM0_RD_TRAN_REQ_STALLED, 243 ETHOSU_PMU_SRAM0_WR_TRANS_ACCEPTED, 244 ETHOSU_PMU_SRAM0_WR_TRANS_COMPLETED_M, 245 ETHOSU_PMU_SRAM0_WR_TRANS_COMPLETED_S, 246 ETHOSU_PMU_SRAM0_WR_DATA_BEAT_WRITTEN, 247 ETHOSU_PMU_SRAM0_WR_TRAN_REQ_STALLED, 248 ETHOSU_PMU_SRAM0_WR_DATA_BEAT_STALLED, 249 ETHOSU_PMU_SRAM0_ENABLED_CYCLES, 250 ETHOSU_PMU_SRAM0_RD_STALL_LIMIT, 251 ETHOSU_PMU_SRAM0_WR_STALL_LIMIT, 252 ETHOSU_PMU_SRAM1_RD_TRANS_ACCEPTED, 253 ETHOSU_PMU_SRAM1_RD_TRANS_COMPLETED, 254 ETHOSU_PMU_SRAM1_RD_DATA_BEAT_RECEIVED, 255 ETHOSU_PMU_SRAM1_RD_TRAN_REQ_STALLED, 256 ETHOSU_PMU_SRAM1_WR_TRANS_ACCEPTED, 257 ETHOSU_PMU_SRAM1_WR_TRANS_COMPLETED_M, 258 ETHOSU_PMU_SRAM1_WR_TRANS_COMPLETED_S, 259 ETHOSU_PMU_SRAM1_WR_DATA_BEAT_WRITTEN, 260 ETHOSU_PMU_SRAM1_WR_TRAN_REQ_STALLED, 261 ETHOSU_PMU_SRAM1_WR_DATA_BEAT_STALLED, 262 ETHOSU_PMU_SRAM1_ENABLED_CYCLES, 263 ETHOSU_PMU_SRAM1_RD_STALL_LIMIT, 264 ETHOSU_PMU_SRAM1_WR_STALL_LIMIT, 265 ETHOSU_PMU_SRAM2_RD_TRANS_ACCEPTED, 266 ETHOSU_PMU_SRAM2_RD_TRANS_COMPLETED, 267 ETHOSU_PMU_SRAM2_RD_DATA_BEAT_RECEIVED, 268 ETHOSU_PMU_SRAM2_RD_TRAN_REQ_STALLED, 269 ETHOSU_PMU_SRAM2_WR_TRANS_ACCEPTED, 270 ETHOSU_PMU_SRAM2_WR_TRANS_COMPLETED_M, 271 ETHOSU_PMU_SRAM2_WR_TRANS_COMPLETED_S, 272 ETHOSU_PMU_SRAM2_WR_DATA_BEAT_WRITTEN, 273 ETHOSU_PMU_SRAM2_WR_TRAN_REQ_STALLED, 274 ETHOSU_PMU_SRAM2_WR_DATA_BEAT_STALLED, 275 ETHOSU_PMU_SRAM2_ENABLED_CYCLES, 276 ETHOSU_PMU_SRAM2_RD_STALL_LIMIT, 277 ETHOSU_PMU_SRAM2_WR_STALL_LIMIT, 278 ETHOSU_PMU_SRAM3_RD_TRANS_ACCEPTED, 279 ETHOSU_PMU_SRAM3_RD_TRANS_COMPLETED, 280 ETHOSU_PMU_SRAM3_RD_DATA_BEAT_RECEIVED, 281 ETHOSU_PMU_SRAM3_RD_TRAN_REQ_STALLED, 282 ETHOSU_PMU_SRAM3_WR_TRANS_ACCEPTED, 283 ETHOSU_PMU_SRAM3_WR_TRANS_COMPLETED_M, 284 ETHOSU_PMU_SRAM3_WR_TRANS_COMPLETED_S, 285 ETHOSU_PMU_SRAM3_WR_DATA_BEAT_WRITTEN, 286 ETHOSU_PMU_SRAM3_WR_TRAN_REQ_STALLED, 287 ETHOSU_PMU_SRAM3_WR_DATA_BEAT_STALLED, 288 ETHOSU_PMU_SRAM3_ENABLED_CYCLES, 289 ETHOSU_PMU_SRAM3_RD_STALL_LIMIT, 290 ETHOSU_PMU_SRAM3_WR_STALL_LIMIT, 291 ETHOSU_PMU_EXT0_RD_TRANS_ACCEPTED, 292 ETHOSU_PMU_EXT0_RD_TRANS_COMPLETED, 293 ETHOSU_PMU_EXT0_RD_DATA_BEAT_RECEIVED, 294 ETHOSU_PMU_EXT0_RD_TRAN_REQ_STALLED, 295 ETHOSU_PMU_EXT0_WR_TRANS_ACCEPTED, 296 ETHOSU_PMU_EXT0_WR_TRANS_COMPLETED_M, 297 ETHOSU_PMU_EXT0_WR_TRANS_COMPLETED_S, 298 ETHOSU_PMU_EXT0_WR_DATA_BEAT_WRITTEN, 299 ETHOSU_PMU_EXT0_WR_TRAN_REQ_STALLED, 300 ETHOSU_PMU_EXT0_WR_DATA_BEAT_STALLED, 301 ETHOSU_PMU_EXT0_ENABLED_CYCLES, 302 ETHOSU_PMU_EXT0_RD_STALL_LIMIT, 303 ETHOSU_PMU_EXT0_WR_STALL_LIMIT, 304 ETHOSU_PMU_EXT1_RD_TRANS_ACCEPTED, 305 ETHOSU_PMU_EXT1_RD_TRANS_COMPLETED, 306 ETHOSU_PMU_EXT1_RD_DATA_BEAT_RECEIVED, 307 ETHOSU_PMU_EXT1_RD_TRAN_REQ_STALLED, 308 ETHOSU_PMU_EXT1_WR_TRANS_ACCEPTED, 309 ETHOSU_PMU_EXT1_WR_TRANS_COMPLETED_M, 310 ETHOSU_PMU_EXT1_WR_TRANS_COMPLETED_S, 311 ETHOSU_PMU_EXT1_WR_DATA_BEAT_WRITTEN, 312 ETHOSU_PMU_EXT1_WR_TRAN_REQ_STALLED, 313 ETHOSU_PMU_EXT1_WR_DATA_BEAT_STALLED, 314 ETHOSU_PMU_EXT1_ENABLED_CYCLES, 315 ETHOSU_PMU_EXT1_RD_STALL_LIMIT, 316 ETHOSU_PMU_EXT1_WR_STALL_LIMIT, 317 318 ETHOSU_PMU_SENTINEL // End-marker (not event) 319 }; 320 #else 321 #error No NPU target defined 322 #endif 323 324 /***************************************************************************** 325 * Functions 326 *****************************************************************************/ 327 328 /** 329 * \brief Enable the PMU 330 */ 331 void ETHOSU_PMU_Enable(struct ethosu_driver *drv); 332 333 /** 334 * \brief Disable the PMU 335 */ 336 void ETHOSU_PMU_Disable(struct ethosu_driver *drv); 337 338 /** 339 * \brief Set event to count for PMU eventer counter 340 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure 341 * \param [in] type Event to count 342 */ 343 void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type); 344 345 /** 346 * \brief Get number of PMU event counters 347 * \return Number of event counters 348 */ 349 uint32_t ETHOSU_PMU_Get_NumEventCounters(void); 350 351 /** 352 * \brief Get event to count for PMU eventer counter 353 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure 354 * \return type Event to count 355 */ 356 enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num); 357 358 /** 359 * \brief Reset cycle counter 360 */ 361 void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv); 362 363 /** 364 * \brief Reset all event counters 365 */ 366 void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv); 367 368 /** 369 * \brief Enable counters 370 * \param [in] mask Counters to enable 371 * \note Enables one or more of the following: 372 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 373 * - cycle counter (bit 31) 374 */ 375 void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask); 376 377 /** 378 * \brief Disable counters 379 * \param [in] mask Counters to disable 380 * \note Disables one or more of the following: 381 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 382 * - cycle counter (bit 31) 383 */ 384 void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask); 385 386 /** 387 * \brief Determine counters activation 388 * 389 * \return Event count 390 * \param [in] mask Counters to enable 391 * \return a bitmask where bit-set means: 392 * - event counters activated (bit 0-ETHOSU_PMU_NCOUNTERS) 393 * - cycle counter activate (bit 31) 394 * \note ETHOSU specific. Usage breaks CMSIS complience 395 */ 396 uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv); 397 398 /** 399 * \brief Read cycle counter (64 bit) 400 * \return Cycle count 401 * \note Two HW 32-bit registers that can increment independently in-between reads. 402 * To work-around raciness yet still avoid turning 403 * off the event both are read as one value twice. If the latter read 404 * is not greater than the former, it means overflow of LSW without 405 * incrementing MSW has occurred, in which case the former value is used. 406 */ 407 uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv); 408 409 /** 410 * \brief Set cycle counter (64 bit) 411 * \param [in] val Conter value 412 * \note Two HW 32-bit registers that can increment independently in-between reads. 413 * To work-around raciness, counter is temporary disabled if enabled. 414 * \note ETHOSU specific. Usage breaks CMSIS complience 415 */ 416 void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val); 417 418 /** 419 * \brief Read event counter 420 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) 421 * \return Event count 422 */ 423 uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num); 424 425 /** 426 * \brief Set event counter value 427 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) 428 * \param [in] val Conter value 429 * \note ETHOSU specific. Usage breaks CMSIS complience 430 */ 431 void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val); 432 433 /** 434 * \brief Read counter overflow status 435 * \return Counter overflow status bits for the following: 436 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)) 437 * - cycle counter (bit 31) 438 */ 439 uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv); 440 441 /** 442 * \brief Clear counter overflow status 443 * \param [in] mask Counter overflow status bits to clear 444 * \note Clears overflow status bits for one or more of the following: 445 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 446 * - cycle counter (bit 31) 447 */ 448 void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask); 449 450 /** 451 * \brief Enable counter overflow interrupt request 452 * \param [in] mask Counter overflow interrupt request bits to set 453 * \note Sets overflow interrupt request bits for one or more of the following: 454 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 455 * - cycle counter (bit 31) 456 */ 457 void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask); 458 459 /** 460 * \brief Disable counter overflow interrupt request 461 * \param [in] mask Counter overflow interrupt request bits to clear 462 * \note Clears overflow interrupt request bits for one or more of the following: 463 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 464 * - cycle counter (bit 31) 465 */ 466 void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask); 467 468 /** 469 * \brief Get counters overflow interrupt request stiinings 470 * \return mask Counter overflow interrupt request bits 471 * \note Sets overflow interrupt request bits for one or more of the following: 472 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 473 * - cycle counter (bit 31) 474 * \note ETHOSU specific. Usage breaks CMSIS compliance 475 */ 476 uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv); 477 478 /** 479 * \brief Software increment event counter 480 * \param [in] mask Counters to increment 481 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 482 * - cycle counter (bit 31) 483 * \note Software increment bits for one or more event counters. 484 */ 485 void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask); 486 487 /** 488 * \brief Set start event number for the cycle counter 489 * \param [in] start_event Event to trigger start of the cycle counter 490 * \note Sets the event number that starts the cycle counter. 491 */ 492 void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event); 493 494 /** 495 * \brief Set stop event number for the cycle counter 496 * \param [in] stop_event Event number 497 * \note Sets the event number that stops the cycle counter. 498 */ 499 void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event); 500 501 /** 502 * \brief Read qread register 503 */ 504 uint32_t ETHOSU_PMU_Get_QREAD(struct ethosu_driver *drv); 505 506 /** 507 * \brief Read status register 508 */ 509 uint32_t ETHOSU_PMU_Get_STATUS(struct ethosu_driver *drv); 510 511 #ifdef __cplusplus 512 } 513 #endif 514 515 #endif /* PMU_ETHOSU_H */ 516
