1 /* 2 * SPDX-FileCopyrightText: Copyright 2019-2022 Arm Limited and/or its affiliates <open-source-office@arm.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef PMU_ETHOSU_H 20 #define PMU_ETHOSU_H 21 22 /***************************************************************************** 23 * Includes 24 *****************************************************************************/ 25 26 #include <stdint.h> 27 28 #include "ethosu_driver.h" 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /***************************************************************************** 35 * Defines 36 *****************************************************************************/ 37 38 #define ETHOSU_PMU_NCOUNTERS 4 39 40 #define ETHOSU_PMU_CNT1_Msk (1UL << 0) 41 #define ETHOSU_PMU_CNT2_Msk (1UL << 1) 42 #define ETHOSU_PMU_CNT3_Msk (1UL << 2) 43 #define ETHOSU_PMU_CNT4_Msk (1UL << 3) 44 #define ETHOSU_PMU_CCNT_Msk (1UL << 31) 45 46 /***************************************************************************** 47 * Types 48 *****************************************************************************/ 49 50 /** \brief HW Supported ETHOSU PMU Events 51 * 52 * Note: These values are symbolic. Actual HW-values may change. I.e. always use API 53 * to set/get actual event-type value. 54 * */ 55 enum ethosu_pmu_event_type 56 { 57 ETHOSU_PMU_NO_EVENT = 0, 58 ETHOSU_PMU_CYCLE, 59 ETHOSU_PMU_NPU_IDLE, 60 ETHOSU_PMU_CC_STALLED_ON_BLOCKDEP, 61 ETHOSU_PMU_CC_STALLED_ON_SHRAM_RECONFIG, 62 ETHOSU_PMU_NPU_ACTIVE, 63 ETHOSU_PMU_MAC_ACTIVE, 64 ETHOSU_PMU_MAC_ACTIVE_8BIT, 65 ETHOSU_PMU_MAC_ACTIVE_16BIT, 66 ETHOSU_PMU_MAC_DPU_ACTIVE, 67 ETHOSU_PMU_MAC_STALLED_BY_WD_ACC, 68 ETHOSU_PMU_MAC_STALLED_BY_WD, 69 ETHOSU_PMU_MAC_STALLED_BY_ACC, 70 ETHOSU_PMU_MAC_STALLED_BY_IB, 71 ETHOSU_PMU_MAC_ACTIVE_32BIT, 72 ETHOSU_PMU_MAC_STALLED_BY_INT_W, 73 ETHOSU_PMU_MAC_STALLED_BY_INT_ACC, 74 ETHOSU_PMU_AO_ACTIVE, 75 ETHOSU_PMU_AO_ACTIVE_8BIT, 76 ETHOSU_PMU_AO_ACTIVE_16BIT, 77 ETHOSU_PMU_AO_STALLED_BY_OFMP_OB, 78 ETHOSU_PMU_AO_STALLED_BY_OFMP, 79 ETHOSU_PMU_AO_STALLED_BY_OB, 80 ETHOSU_PMU_AO_STALLED_BY_ACC_IB, 81 ETHOSU_PMU_AO_STALLED_BY_ACC, 82 ETHOSU_PMU_AO_STALLED_BY_IB, 83 ETHOSU_PMU_WD_ACTIVE, 84 ETHOSU_PMU_WD_STALLED, 85 ETHOSU_PMU_WD_STALLED_BY_WS, 86 ETHOSU_PMU_WD_STALLED_BY_WD_BUF, 87 ETHOSU_PMU_WD_PARSE_ACTIVE, 88 ETHOSU_PMU_WD_PARSE_STALLED, 89 ETHOSU_PMU_WD_PARSE_STALLED_IN, 90 ETHOSU_PMU_WD_PARSE_STALLED_OUT, 91 ETHOSU_PMU_WD_TRANS_WS, 92 ETHOSU_PMU_WD_TRANS_WB, 93 ETHOSU_PMU_WD_TRANS_DW0, 94 ETHOSU_PMU_WD_TRANS_DW1, 95 ETHOSU_PMU_AXI0_RD_TRANS_ACCEPTED, 96 ETHOSU_PMU_AXI0_RD_TRANS_COMPLETED, 97 ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED, 98 ETHOSU_PMU_AXI0_RD_TRAN_REQ_STALLED, 99 ETHOSU_PMU_AXI0_WR_TRANS_ACCEPTED, 100 ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_M, 101 ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_S, 102 ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN, 103 ETHOSU_PMU_AXI0_WR_TRAN_REQ_STALLED, 104 ETHOSU_PMU_AXI0_WR_DATA_BEAT_STALLED, 105 ETHOSU_PMU_AXI0_ENABLED_CYCLES, 106 ETHOSU_PMU_AXI0_RD_STALL_LIMIT, 107 ETHOSU_PMU_AXI0_WR_STALL_LIMIT, 108 ETHOSU_PMU_AXI_LATENCY_ANY, 109 ETHOSU_PMU_AXI_LATENCY_32, 110 ETHOSU_PMU_AXI_LATENCY_64, 111 ETHOSU_PMU_AXI_LATENCY_128, 112 ETHOSU_PMU_AXI_LATENCY_256, 113 ETHOSU_PMU_AXI_LATENCY_512, 114 ETHOSU_PMU_AXI_LATENCY_1024, 115 ETHOSU_PMU_ECC_DMA, 116 ETHOSU_PMU_ECC_SB0, 117 ETHOSU_PMU_AXI1_RD_TRANS_ACCEPTED, 118 ETHOSU_PMU_AXI1_RD_TRANS_COMPLETED, 119 ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED, 120 ETHOSU_PMU_AXI1_RD_TRAN_REQ_STALLED, 121 ETHOSU_PMU_AXI1_WR_TRANS_ACCEPTED, 122 ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_M, 123 ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_S, 124 ETHOSU_PMU_AXI1_WR_DATA_BEAT_WRITTEN, 125 ETHOSU_PMU_AXI1_WR_TRAN_REQ_STALLED, 126 ETHOSU_PMU_AXI1_WR_DATA_BEAT_STALLED, 127 ETHOSU_PMU_AXI1_ENABLED_CYCLES, 128 ETHOSU_PMU_AXI1_RD_STALL_LIMIT, 129 ETHOSU_PMU_AXI1_WR_STALL_LIMIT, 130 ETHOSU_PMU_ECC_SB1, 131 132 ETHOSU_PMU_SENTINEL // End-marker (not event) 133 }; 134 135 /***************************************************************************** 136 * Functions 137 *****************************************************************************/ 138 139 /** 140 * \brief Enable the PMU 141 */ 142 void ETHOSU_PMU_Enable(struct ethosu_driver *drv); 143 144 /** 145 * \brief Disable the PMU 146 */ 147 void ETHOSU_PMU_Disable(struct ethosu_driver *drv); 148 149 /** 150 * \brief Set event to count for PMU eventer counter 151 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure 152 * \param [in] type Event to count 153 */ 154 void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type); 155 156 /** 157 * \brief Get number of PMU event counters 158 * \return Number of event counters 159 */ 160 uint32_t ETHOSU_PMU_Get_NumEventCounters(void); 161 162 /** 163 * \brief Get event to count for PMU eventer counter 164 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure 165 * \return type Event to count 166 */ 167 enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num); 168 169 /** 170 * \brief Reset cycle counter 171 */ 172 void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv); 173 174 /** 175 * \brief Reset all event counters 176 */ 177 void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv); 178 179 /** 180 * \brief Enable counters 181 * \param [in] mask Counters to enable 182 * \note Enables one or more of the following: 183 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 184 * - cycle counter (bit 31) 185 */ 186 void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask); 187 188 /** 189 * \brief Disable counters 190 * \param [in] mask Counters to disable 191 * \note Disables one or more of the following: 192 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 193 * - cycle counter (bit 31) 194 */ 195 void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask); 196 197 /** 198 * \brief Determine counters activation 199 * 200 * \return Event count 201 * \param [in] mask Counters to enable 202 * \return a bitmask where bit-set means: 203 * - event counters activated (bit 0-ETHOSU_PMU_NCOUNTERS) 204 * - cycle counter activate (bit 31) 205 * \note ETHOSU specific. Usage breaks CMSIS complience 206 */ 207 uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv); 208 209 /** 210 * \brief Read cycle counter (64 bit) 211 * \return Cycle count 212 * \note Two HW 32-bit registers that can increment independently in-between reads. 213 * To work-around raciness yet still avoid turning 214 * off the event both are read as one value twice. If the latter read 215 * is not greater than the former, it means overflow of LSW without 216 * incrementing MSW has occurred, in which case the former value is used. 217 */ 218 uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv); 219 220 /** 221 * \brief Set cycle counter (64 bit) 222 * \param [in] val Conter value 223 * \note Two HW 32-bit registers that can increment independently in-between reads. 224 * To work-around raciness, counter is temporary disabled if enabled. 225 * \note ETHOSU specific. Usage breaks CMSIS complience 226 */ 227 void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val); 228 229 /** 230 * \brief Read event counter 231 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) 232 * \return Event count 233 */ 234 uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num); 235 236 /** 237 * \brief Set event counter value 238 * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) 239 * \param [in] val Conter value 240 * \note ETHOSU specific. Usage breaks CMSIS complience 241 */ 242 void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val); 243 244 /** 245 * \brief Read counter overflow status 246 * \return Counter overflow status bits for the following: 247 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)) 248 * - cycle counter (bit 31) 249 */ 250 uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv); 251 252 /** 253 * \brief Clear counter overflow status 254 * \param [in] mask Counter overflow status bits to clear 255 * \note Clears overflow status bits for one or more of the following: 256 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 257 * - cycle counter (bit 31) 258 */ 259 void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask); 260 261 /** 262 * \brief Enable counter overflow interrupt request 263 * \param [in] mask Counter overflow interrupt request bits to set 264 * \note Sets overflow interrupt request bits for one or more of the following: 265 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 266 * - cycle counter (bit 31) 267 */ 268 void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask); 269 270 /** 271 * \brief Disable counter overflow interrupt request 272 * \param [in] mask Counter overflow interrupt request bits to clear 273 * \note Clears overflow interrupt request bits for one or more of the following: 274 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 275 * - cycle counter (bit 31) 276 */ 277 void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask); 278 279 /** 280 * \brief Get counters overflow interrupt request stiinings 281 * \return mask Counter overflow interrupt request bits 282 * \note Sets overflow interrupt request bits for one or more of the following: 283 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 284 * - cycle counter (bit 31) 285 * \note ETHOSU specific. Usage breaks CMSIS compliance 286 */ 287 uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv); 288 289 /** 290 * \brief Software increment event counter 291 * \param [in] mask Counters to increment 292 * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) 293 * - cycle counter (bit 31) 294 * \note Software increment bits for one or more event counters. 295 */ 296 void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask); 297 298 /** 299 * \brief Set start event number for the cycle counter 300 * \param [in] start_event Event to trigger start of the cycle counter 301 * \note Sets the event number that starts the cycle counter. 302 */ 303 void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event); 304 305 /** 306 * \brief Set stop event number for the cycle counter 307 * \param [in] stop_event Event number 308 * \note Sets the event number that stops the cycle counter. 309 */ 310 void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event); 311 312 /** 313 * \brief Read qread register 314 */ 315 uint32_t ETHOSU_PMU_Get_QREAD(struct ethosu_driver *drv); 316 317 /** 318 * \brief Read status register 319 */ 320 uint32_t ETHOSU_PMU_Get_STATUS(struct ethosu_driver *drv); 321 322 #ifdef __cplusplus 323 } 324 #endif 325 326 #endif /* PMU_ETHOSU_H */ 327
