1 /* 2 * Copyright (c) 2019-2020,2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef ETHOSU_CONFIG_H 20 #define ETHOSU_CONFIG_H 21 22 /* Set default values if not manually overriden */ 23 24 #ifndef NPU_QCONFIG 25 #define NPU_QCONFIG 2 26 #endif 27 28 #ifndef NPU_REGIONCFG_0 29 #define NPU_REGIONCFG_0 3 30 #endif 31 32 #ifndef NPU_REGIONCFG_1 33 #define NPU_REGIONCFG_1 2 34 #endif 35 36 #ifndef NPU_REGIONCFG_2 37 #define NPU_REGIONCFG_2 1 38 #endif 39 40 #ifndef NPU_REGIONCFG_3 41 #define NPU_REGIONCFG_3 1 42 #endif 43 44 #ifndef NPU_REGIONCFG_4 45 #define NPU_REGIONCFG_4 1 46 #endif 47 48 #ifndef NPU_REGIONCFG_5 49 #define NPU_REGIONCFG_5 1 50 #endif 51 52 #ifndef NPU_REGIONCFG_6 53 #define NPU_REGIONCFG_6 1 54 #endif 55 56 #ifndef NPU_REGIONCFG_7 57 #define NPU_REGIONCFG_7 1 58 #endif 59 60 #ifndef AXI_LIMIT0_MAX_BEATS_BYTES 61 #define AXI_LIMIT0_MAX_BEATS_BYTES 0x0 62 #endif 63 64 #ifndef AXI_LIMIT0_MEM_TYPE 65 #define AXI_LIMIT0_MEM_TYPE 0x0 66 #endif 67 68 #ifndef AXI_LIMIT0_MAX_OUTSTANDING_READS 69 #define AXI_LIMIT0_MAX_OUTSTANDING_READS 64 70 #endif 71 72 #ifndef AXI_LIMIT0_MAX_OUTSTANDING_WRITES 73 #define AXI_LIMIT0_MAX_OUTSTANDING_WRITES 32 74 #endif 75 76 #ifndef AXI_LIMIT1_MAX_BEATS_BYTES 77 #define AXI_LIMIT1_MAX_BEATS_BYTES 0x0 78 #endif 79 80 #ifndef AXI_LIMIT1_MEM_TYPE 81 #define AXI_LIMIT1_MEM_TYPE 0x0 82 #endif 83 84 #ifndef AXI_LIMIT1_MAX_OUTSTANDING_READS 85 #define AXI_LIMIT1_MAX_OUTSTANDING_READS 64 86 #endif 87 88 #ifndef AXI_LIMIT1_MAX_OUTSTANDING_WRITES 89 #define AXI_LIMIT1_MAX_OUTSTANDING_WRITES 32 90 #endif 91 92 #ifndef AXI_LIMIT2_MAX_BEATS_BYTES 93 #define AXI_LIMIT2_MAX_BEATS_BYTES 0x0 94 #endif 95 96 #ifndef AXI_LIMIT2_MEM_TYPE 97 #define AXI_LIMIT2_MEM_TYPE 0x0 98 #endif 99 100 #ifndef AXI_LIMIT2_MAX_OUTSTANDING_READS 101 #define AXI_LIMIT2_MAX_OUTSTANDING_READS 64 102 #endif 103 104 #ifndef AXI_LIMIT2_MAX_OUTSTANDING_WRITES 105 #define AXI_LIMIT2_MAX_OUTSTANDING_WRITES 32 106 #endif 107 108 #ifndef AXI_LIMIT3_MAX_BEATS_BYTES 109 #define AXI_LIMIT3_MAX_BEATS_BYTES 0x0 110 #endif 111 112 #ifndef AXI_LIMIT3_MEM_TYPE 113 #define AXI_LIMIT3_MEM_TYPE 0x0 114 #endif 115 116 #ifndef AXI_LIMIT3_MAX_OUTSTANDING_READS 117 #define AXI_LIMIT3_MAX_OUTSTANDING_READS 64 118 #endif 119 120 #ifndef AXI_LIMIT3_MAX_OUTSTANDING_WRITES 121 #define AXI_LIMIT3_MAX_OUTSTANDING_WRITES 32 122 #endif 123 124 /* 125 * Address offset between the CPU and the NPU. The offset is 126 * applied to the QBASE and BASEP registers. 127 */ 128 #ifndef BASE_POINTER_OFFSET 129 #define BASE_POINTER_OFFSET 0 130 #endif 131 132 #endif /* #ifndef ETHOSU_CONFIG_H */ 133
