1 /*
2  * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "soc_flash_init.h"
8 
9 #include <stdbool.h>
10 #include <assert.h>
11 #include <string.h>
12 
13 #include "esp_err.h"
14 #include "esp_log.h"
15 #include "esp_rom_gpio.h"
16 #include "esp_rom_efuse.h"
17 #include "esp32/rom/spi_flash.h"
18 #include "esp32/rom/cache.h"
19 #include "soc/gpio_periph.h"
20 #include "soc/efuse_reg.h"
21 #include "soc/spi_reg.h"
22 #include "soc/soc_caps.h"
23 #include "soc/soc_pins.h"
24 #include "soc/chip_revision.h"
25 #include "hal/efuse_hal.h"
26 #include "hal/gpio_hal.h"
27 #include "flash_qio_mode.h"
28 #include "bootloader_common.h"
29 #include "bootloader_flash_config.h"
30 #include "bootloader_flash_priv.h"
31 #include "bootloader_init.h"
32 
33 #include "hal/efuse_ll.h"
34 
35 #define TAG "flash_init"
36 extern esp_image_header_t bootloader_image_hdr;
37 
38 #define FLASH_CLK_IO   SPI_CLK_GPIO_NUM
39 #define FLASH_CS_IO    SPI_CS0_GPIO_NUM
40 #define FLASH_SPIQ_IO  SPI_Q_GPIO_NUM
41 #define FLASH_SPID_IO  SPI_D_GPIO_NUM
42 #define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
43 #define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
44 
get_chip_ver_pkg(void)45 uint32_t get_chip_ver_pkg(void)
46 {
47 	return efuse_ll_get_chip_ver_pkg();
48 }
49 
flash_update_id(void)50 void flash_update_id(void)
51 {
52 	g_rom_flashchip.device_id = bootloader_read_flash_id();
53 }
54 
flash_update_size(uint32_t size)55 void flash_update_size(uint32_t size)
56 {
57 	g_rom_flashchip.chip_size = size;
58 }
59 
flash_cs_timing_config(void)60 void flash_cs_timing_config(void)
61 {
62 	SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
63 	SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
64 	SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
65 	SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
66 	SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
67 	SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
68 }
69 
flash_clock_config(const esp_image_header_t * pfhdr)70 void flash_clock_config(const esp_image_header_t *pfhdr)
71 {
72 	uint32_t spi_clk_div = 0;
73 
74 	switch (pfhdr->spi_speed) {
75 	case ESP_IMAGE_SPI_SPEED_DIV_1:
76 		spi_clk_div = 1;
77 		break;
78 	case ESP_IMAGE_SPI_SPEED_DIV_2:
79 		spi_clk_div = 2;
80 		break;
81 	case ESP_IMAGE_SPI_SPEED_DIV_3:
82 		spi_clk_div = 3;
83 		break;
84 	case ESP_IMAGE_SPI_SPEED_DIV_4:
85 		spi_clk_div = 4;
86 		break;
87 	default:
88 		break;
89 	}
90 	esp_rom_spiflash_config_clk(spi_clk_div, 0);
91 	esp_rom_spiflash_config_clk(spi_clk_div, 1);
92 }
93 
flash_gpio_config(const esp_image_header_t * pfhdr)94 void flash_gpio_config(const esp_image_header_t *pfhdr)
95 {
96 	uint32_t drv = 2;
97 
98 	if (pfhdr->spi_speed == ESP_IMAGE_SPI_SPEED_DIV_1) {
99 		drv = 3;
100 	}
101 
102 	uint32_t pkg_ver = get_chip_ver_pkg();
103 
104 	if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
105 	    pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
106 	    pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
107 	    pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
108 		/* For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured flash
109 		 * clock signal should come from IO MUX.
110 		 */
111 		gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
112 		SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
113 	} else {
114 		const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
115 
116 		if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
117 			esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
118 			esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
119 			esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
120 			esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
121 			esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
122 			esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
123 			esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
124 			esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
125 			esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
126 			/* select pin function gpio */
127 			gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
128 			gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
129 			gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
130 			gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
131 			gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
132 			/* flash clock signal should come from IO MUX. Set drive ability for clock
133 			 */
134 			gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
135 			SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
136 
137 			uint32_t flash_id = g_rom_flashchip.device_id;
138 
139 			if (flash_id == FLASH_ID_GD25LQ32C) {
140 				/* Set drive ability for 1.8v flash in 80Mhz. */
141 				SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
142 				SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
143 				SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
144 				SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
145 				SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
146 				SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
147 			}
148 		}
149 	}
150 }
151 
flash_dummy_config(const esp_image_header_t * pfhdr)152 void flash_dummy_config(const esp_image_header_t *pfhdr)
153 {
154 	int spi_cache_dummy = 0;
155 	uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));
156 
157 	if (modebit & SPI_FASTRD_MODE) {
158 		if (modebit & SPI_FREAD_QIO) {
159 			/* SPI mode is QIO */
160 			spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
161 		} else if (modebit & SPI_FREAD_DIO) {
162 			/* SPI mode is DIO */
163 			spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
164 			SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V,
165 					  SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
166 		} else if (modebit & (SPI_FREAD_QUAD | SPI_FREAD_DUAL)) {
167 			/* SPI mode is QOUT or DIO */
168 			spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
169 		}
170 	}
171 
172 	switch (pfhdr->spi_speed) {
173 	case ESP_IMAGE_SPI_SPEED_DIV_1:
174 		g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
175 		g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
176 		break;
177 	case ESP_IMAGE_SPI_SPEED_DIV_2:
178 		g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
179 		g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
180 		break;
181 	case ESP_IMAGE_SPI_SPEED_DIV_3:
182 	case ESP_IMAGE_SPI_SPEED_DIV_4:
183 		g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
184 		g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
185 		break;
186 	default:
187 		break;
188 	}
189 
190 	SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V,
191 			  spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
192 			  SPI_USR_DUMMY_CYCLELEN_S);
193 }
194 
195 /* ESP32-D2WD & ESP32-PICO-D4 has this GPIO wired to WP pin of flash  */
196 #define ESP32_D2WD_WP_GPIO 7
197 /* ESP32-PICO-V3* use this GPIO for WP pin of flash */
198 #define ESP32_PICO_V3_GPIO 18
199 
flash_get_wp_pin(void)200 int flash_get_wp_pin(void)
201 {
202 	switch (get_chip_ver_pkg()) {
203 	case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:
204 	case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
205 		return ESP32_D2WD_WP_GPIO;
206 	case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
207 		/* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version
208 		 * differentiates
209 		 */
210 		return !ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300) ? ESP32_D2WD_WP_GPIO
211 									   : ESP32_PICO_V3_GPIO;
212 	case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
213 		return ESP32_PICO_V3_GPIO;
214 	default:
215 		return SPI_WP_GPIO_NUM;
216 	}
217 }
218 
update_flash_config(const esp_image_header_t * bootloader_hdr)219 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
220 {
221 	volatile uint32_t size;
222 
223 	switch (bootloader_hdr->spi_size) {
224 	case ESP_IMAGE_FLASH_SIZE_1MB:
225 		size = 1;
226 		break;
227 	case ESP_IMAGE_FLASH_SIZE_2MB:
228 		size = 2;
229 		break;
230 	case ESP_IMAGE_FLASH_SIZE_4MB:
231 		size = 4;
232 		break;
233 	case ESP_IMAGE_FLASH_SIZE_8MB:
234 		size = 8;
235 		break;
236 	case ESP_IMAGE_FLASH_SIZE_16MB:
237 		size = 16;
238 		break;
239 	default:
240 		size = 2;
241 	}
242 	Cache_Read_Disable(0);
243 	/* Set flash chip size */
244 	esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000,
245 				      0x100, 0xffff);
246 	Cache_Flush(0);
247 	Cache_Read_Enable(0);
248 }
249 
print_flash_info(const esp_image_header_t * bootloader_hdr)250 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
251 {
252 	ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
253 	ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
254 	ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
255 	ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
256 	ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
257 
258 	const char *str;
259 
260 	switch (bootloader_hdr->spi_speed) {
261 	case ESP_IMAGE_SPI_SPEED_DIV_2:
262 		str = "40MHz";
263 		break;
264 	case ESP_IMAGE_SPI_SPEED_DIV_3:
265 		str = "26.7MHz";
266 		break;
267 	case ESP_IMAGE_SPI_SPEED_DIV_4:
268 		str = "20MHz";
269 		break;
270 	case ESP_IMAGE_SPI_SPEED_DIV_1:
271 		str = "80MHz";
272 		break;
273 	default:
274 		str = "20MHz";
275 		break;
276 	}
277 	ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
278 
279 	/* SPI mode could have been set to QIO during boot already,
280 	 * so test the SPI registers not the flash header
281 	 */
282 	uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
283 
284 	if (spi_ctrl & SPI_FREAD_QIO) {
285 		str = "QIO";
286 	} else if (spi_ctrl & SPI_FREAD_QUAD) {
287 		str = "QOUT";
288 	} else if (spi_ctrl & SPI_FREAD_DIO) {
289 		str = "DIO";
290 	} else if (spi_ctrl & SPI_FREAD_DUAL) {
291 		str = "DOUT";
292 	} else if (spi_ctrl & SPI_FASTRD_MODE) {
293 		str = "FAST READ";
294 	} else {
295 		str = "SLOW READ";
296 	}
297 	ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
298 
299 	switch (bootloader_hdr->spi_size) {
300 	case ESP_IMAGE_FLASH_SIZE_1MB:
301 		str = "1MB";
302 		break;
303 	case ESP_IMAGE_FLASH_SIZE_2MB:
304 		str = "2MB";
305 		break;
306 	case ESP_IMAGE_FLASH_SIZE_4MB:
307 		str = "4MB";
308 		break;
309 	case ESP_IMAGE_FLASH_SIZE_8MB:
310 		str = "8MB";
311 		break;
312 	case ESP_IMAGE_FLASH_SIZE_16MB:
313 		str = "16MB";
314 		break;
315 	default:
316 		str = "2MB";
317 		break;
318 	}
319 	ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
320 }
321 
init_flash_configure(void)322 static void init_flash_configure(void)
323 {
324 	flash_gpio_config(&bootloader_image_hdr);
325 	flash_dummy_config(&bootloader_image_hdr);
326 	flash_cs_timing_config();
327 }
328 
init_spi_flash(void)329 esp_err_t init_spi_flash(void)
330 {
331 	init_flash_configure();
332 #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
333 	const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
334 
335 	if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI &&
336 	    spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
337 		ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable "
338 				    "CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
339 		return ESP_FAIL;
340 	}
341 #endif
342 
343 	bootloader_flash_unlock();
344 
345 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
346 	bootloader_enable_qio_mode();
347 #endif
348 
349 	print_flash_info(&bootloader_image_hdr);
350 	update_flash_config(&bootloader_image_hdr);
351 	/* ensure the flash is write-protected */
352 	bootloader_enable_wp();
353 	return ESP_OK;
354 }
355