SPI_CS_DELAY_NUM_S 28 RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) EFUSE_XPD_SDIO_REG_S 14 DPORT_PRO_SPI_INTR_1_MAP 0x0000001F RTC_CNTL_PD_EN_V 0x1 DR_REG_PWM3_BASE 0x3ff70000 DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) DPORT_PRO_TX_END_V 0x1 SPI_FREAD_DUAL_S 14 DPORT_DMMU_TABLE13_V 0x7F TIMG_RTC_CALI_VALUE_V 0x1FFFFFF DPORT_CPU_INTR_FROM_CPU_0_S 0 DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F SPI_DMA_TX_STOP_V 0x1 DPORT_PRO_SLAVE_WR (BIT(21)) RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 __int_fast64_t_defined 1 TIMG_T1_ALARM_EN_M (BIT(10)) spi_size CONFIG_LOG_DEFAULT_LEVEL 3 EXCCAUSE_ALLOCA 5 DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) TIMG_T1_LOAD_V 0xFFFFFFFF EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F XCHAL_INSTROM0_ECC_PARITY 0 EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) SPI_TX_CRC_EN_M (BIT(11)) RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) FUNC_GPIO26_GPIO26 2 SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 __LOCK_INIT_RECURSIVE(class,lock) static int lock = 0; DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 XCHAL_NUM_TIMERS 3 SPI_IN_ERR_EOF_INT_ST_V 0x1 DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F SPI_FLASH_WREN (BIT(30)) DPORT_CACHE_IA_INT_EN_S 0 TIMG_T0_INT_ENA_V 0x1 RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 TIMG_LACT_EN_M (BIT(31)) RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) RTC_CNTL_SCRATCH3_S 0 DPORT_APP_UART1_INTR_MAP_V 0x1F __RAND_MAX 0x7fffffff EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) REG_CLR_BIT(_r,_b) (*(volatile uint32_t*)(_r) &= ~(_b)) EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) SPI_BUF9_S 0 SPI_T_PP_SHIFT_V 0xF __DEC64_MIN__ 1E-383DD EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) DPORT_APP_RMT_INTR_MAP 0x0000001F SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F _REENT_INIT_PTR(var) { (var)->_errno = 0; (var)->_stdin = &(var)->__sf[0]; (var)->_stdout = &(var)->__sf[1]; (var)->_stderr = &(var)->__sf[2]; (var)->_inc = 0; memset(&(var)->_emergency, 0, sizeof((var)->_emergency)); (var)->_current_category = 0; (var)->_current_locale = "C"; (var)->__sdidinit = 0; (var)->__cleanup = _NULL; (var)->_result = _NULL; (var)->_result_k = 0; (var)->_p5s = _NULL; (var)->_freelist = _NULL; (var)->_cvtlen = 0; (var)->_cvtbuf = _NULL; (var)->_new._reent._unused_rand = 0; (var)->_new._reent._strtok_last = _NULL; (var)->_new._reent._asctime_buf[0] = 0; memset(&(var)->_new._reent._localtime_buf, 0, sizeof((var)->_new._reent._localtime_buf)); (var)->_new._reent._gamma_signgam = 0; (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; (var)->_new._reent._mblen_state.__count = 0; (var)->_new._reent._mblen_state.__value.__wch = 0; (var)->_new._reent._mbtowc_state.__count = 0; (var)->_new._reent._mbtowc_state.__value.__wch = 0; (var)->_new._reent._wctomb_state.__count = 0; (var)->_new._reent._wctomb_state.__value.__wch = 0; (var)->_new._reent._mbrlen_state.__count = 0; (var)->_new._reent._mbrlen_state.__value.__wch = 0; (var)->_new._reent._mbrtowc_state.__count = 0; (var)->_new._reent._mbrtowc_state.__value.__wch = 0; (var)->_new._reent._mbsrtowcs_state.__count = 0; (var)->_new._reent._mbsrtowcs_state.__value.__wch = 0; (var)->_new._reent._wcrtomb_state.__count = 0; (var)->_new._reent._wcrtomb_state.__value.__wch = 0; (var)->_new._reent._wcsrtombs_state.__count = 0; (var)->_new._reent._wcsrtombs_state.__value.__wch = 0; (var)->_new._reent._l64a_buf[0] = '\0'; (var)->_new._reent._signal_buf[0] = '\0'; (var)->_new._reent._getdate_err = 0; (var)->_atexit = _NULL; (var)->_atexit0._next = _NULL; (var)->_atexit0._ind = 0; (var)->_atexit0._fns[0] = _NULL; (var)->_atexit0._on_exit_args._fntypes = 0; (var)->_atexit0._on_exit_args._fnargs[0] = _NULL; (var)->_sig_func = _NULL; (var)->__sglue._next = _NULL; (var)->__sglue._niobs = 0; (var)->__sglue._iobs = _NULL; memset(&(var)->__sf, 0, sizeof((var)->__sf)); } RTC_CNTL_WIFI_FORCE_PU (BIT(18)) DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) pfhdr DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0) XCHAL_INT30_EXTNUM 24 DPORT_PRO_SLC1_INTR_MAP_S 0 TIMG_LACT_INT_ENA (BIT(3)) SPIEraseSector EFUSE_BLK3_DOUT1_S 0 XCHAL_HAVE_PSO_CDM 0 DPORT_PRO_RWBLE_IRQ_MAP_S 0 SPI_OUTDSCR_BURST_EN_S 10 EFUSE_SPI_PAD_CONFIG_D 0x0000001F DPORT_ARB_IA_S 4 EFUSE_RD_KEY_STATUS_V 0x1 DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F SPI_CLK_EQU_SYSCLK_S 31 EFUSE_BLK3_DOUT4_V 0xFFFFFFFF RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) DPORT_SHROM_MPU_TABLE11 0x00000003 SPI_USR_CMD_HOLD_S 22 DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK) DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 XCHAL_HAVE_FULL_RESET 1 EFUSE_BLK3_DOUT4 0xFFFFFFFF SPI_TRANS_CNT 0x0000000F __FLT_EVAL_METHOD__ 0 RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) TIMG_T0_LOAD_V 0xFFFFFFFF RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 PERIPHS_SPI_FLASH_C2 SPI_W2(1) __ATOMIC_RELAXED 0 FUNC_SD_DATA2_SD_DATA2 0 DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) DPORT_MASK_AHB_M (BIT(4)) SPI_USR_MISO_HIGHPART_M (BIT(24)) DPORT_LSLP_MEM_PD_MASK (BIT(0)) ETS_TG0_WDT_EDGE_INTR_SOURCE 60 _REENT_SMALL_CHECK_INIT(ptr) EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF ETS_WIFI_MAC_INTR_SOURCE 0 RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F EFUSE_BLK3_DIN0 0xFFFFFFFF TIMG_WDT_CLK_PRESCALE_S 16 APB_CLK_FREQ_ROM 26*1000000 DPORT_APP_UHCI0_INTR_MAP_V 0x1F DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) EFUSE_PGM_CMD_V 0x1 __FLT_DENORM_MIN__ 1.4012984643248171e-45F DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) RTC_CNTL_CPUPERIOD_SEL 0x00000003 SPI_INLINK_STOP_V 0x1 RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) SPI_CS_HOLD_DELAY_V 0xF PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) DPORT_AGC_MEM_FORCE_PD_S 1 RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S)) SPI_SLV_CMD_DEFINE_S 27 TIMG_T0_INT_ST (BIT(0)) SPI_SLV_WR_STA_DONE_M (BIT(3)) DPORT_PRO_WR_BAK_TO_READ_V 0x1 TIMG_LACT_INT_CLR (BIT(3)) DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) EFUSE_BLK3_DIN1_S 0 DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) SPI_T_PP_TIME_S 0 DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) SPI_FCS_CRC_EN_V 0x1 __STDINT_EXP(x) __ ##x ##__ __END_DECLS RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 DPORT_SHROM_MPU_TABLE15_S 0 RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) SPI_ERROR_LOG "spi flash error" DPORT_APP_CACHE_TAG_PD_M (BIT(9)) TIMG_T0_LO_V 0xFFFFFFFF DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) DPORT_AHB_ACCESS_GRANT_1 0x000001FF RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) EFUSE_BLK1_DOUT1_V 0xFFFFFFFF RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) FUNC_SD_DATA3_HS1_DATA3 3 DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F FUNC_SD_CLK_GPIO6 2 RTC_CNTL_SW_PROCPU_RST (BIT(5)) TIMG_T0_LOAD 0xFFFFFFFF EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) DPORT_PRO_UART2_INTR_MAP_V 0x1F DPORT_IMMU_TABLE13_S 0 SPI_USR_DUMMY_HOLD (BIT(20)) TIMG_LACT_DIVIDER 0x0000FFFF DPORT_IMMU_PAGE_MODE_V 0x3 DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S)) _REENT_EMERGENCY(ptr) ((ptr)->_emergency) XCHAL_HAVE_MAC16 1 DPORT_PRO_RMT_INTR_MAP 0x0000001F DPORT_IMMU_TABLE1_V 0x7F XCHAL_HAVE_ICACHE_DYN_WAYS 0 DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) __SCHAR_MAX__ 127 EFUSE_BLK3_DIN3_V 0xFFFFFFFF RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F DPORT_PRO_PWM2_INTR_MAP_S 0 DPORT_APP_SLAVE_WR (BIT(21)) EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF SPI_ST_S 0 DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 SPI_CLK_DIV 4 DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) __DBL_DIG__ 15 RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) XCHAL_HAVE_XEAX 0 DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) __DBL_MAX_EXP__ 1024 EFUSE_BLK1_DIN0_V 0xFFFFFFFF DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) RTC_CNTL_DTEST_RTC_V 0x3 EFUSE_XPD_SDIO_REG_M (BIT(14)) PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) EFUSE_READ_DONE_INT_RAW (BIT(0)) DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) __INT64_TYPE__ long long int EFUSE_BLK1_DIN0_S 0 EFUSE_DAC_CLK_PAD_SEL_V 0x1 XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 SPI_CS_SETUP_M (BIT(5)) EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) SPI_SYNC_RESET_V 0x1 TIMG_T1_LOAD_HI_S 0 XCHAL_HAVE_PREDICTED_BRANCHES 0 EFUSE_XPD_SDIO_REG_V 0x1 __const const DPORT_DMMU_TABLE8 0x0000007F RTC_CNTL_DG_WRAP_PD_EN_V 0x1 SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) PERIPHS_SPI_FLASH_C1 SPI_W1(1) EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) DPORT_PRO_UHCI1_INTR_MAP_V 0x1F SPI_SRAM_BYTES_LEN_S 6 SPI_FLASH_DP_V 0x1 RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) DPORT_APPCPU_RUNSTALL_S 0 spiRet1 spiRet2 RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) XCHAL_HAVE_FUSION_SOFTDEMAP 0 DPORT_APP_PCNT_INTR_MAP_V 0x1F __DEC32_MIN__ 1E-95DF DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) SPI_AHBM_FIFO_RST_V 0x1 DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) RTC_CNTL_ROM0_PD_EN_S 24 RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) SPI_MISO_DELAY_MODE_V 0x3 INT_FAST8_MIN (-__STDINT_EXP(INT_MAX)-1) RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 EFUSE_CHIP_VER_DIS_CACHE_S 3 DPORT_APP_OUT_VECBASE_SEL 0x00000003 RTC_CNTL_XTL_FORCE_ISO (BIT(23)) SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 EFUSE_RD_KEY_STATUS_M (BIT(10)) SIZE_MAX __SIZE_MAX__ RTC_CNTL_DTEST_RTC_S 30 XCHAL_DCACHE_BANKS 0 DPORT_SHARE_ROM_MPU_ENA (BIT(0)) RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF SPI_OUT_TOTAL_EOF_INT_ENA_S 8 __attribute_format_strfmon__(a,b) DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF XCHAL_NUM_URAM 0 DPORT_I2S0_CLK_EN (BIT(4)) EFUSE_BLK2_DIN2_V 0xFFFFFFFF RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) XCHAL_HAVE_DCACHE_DYN_WAYS 0 XCHAL_HAVE_FUSION_LFSR_CRC 0 DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) SPI_CS1_DIS (BIT(1)) SPI_USR_S 18 EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 SPI_BUF7_V 0xFFFFFFFF FUNC_GPIO25_EMAC_RXD0 5 DPORT_APP_UART_INTR_MAP_V 0x1F DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) RTC_CNTL_ANA_CLK_RTC_SEL_S 30 DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) SPI_INLINK_START (BIT(29)) RTC_CNTL_BROWN_OUT_ENA_S 30 __INT16_TYPE__ short int SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) MESR_ERRENAB_SHIFT 8 EFUSE_BLK3_DOUT3_V 0xFFFFFFFF EFUSE_RD_CODING_SCHEME_V 0x3 TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF TIMG_T0_INT_CLR_V 0x1 RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) ETS_TG0_WDT_LEVEL_INTR_SOURCE 16 SPI_RD_BYTE_ORDER (BIT(10)) SPI_STATUS_EXT_S 24 DPORT_APP_INTR_STATUS_0 0xFFFFFFFF RTC_CNTL_TIME_VALID (BIT(30)) DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) __INT64_MAX__ 9223372036854775807LL _REENT_CHECK_ASCTIME_BUF(ptr) __DEC128_MANT_DIG__ 34 SPI_RD_BIT_ORDER (BIT(25)) RTC_CNTL_PLLA_FORCE_PU (BIT(24)) SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) XCHAL_INT11_LEVEL 3 __SHRT_MAX__ 32767 EFUSE_RD_DISABLE_DL_CACHE_S 9 DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) DPORT_APP_MAC_NMI_MAP 0x0000001F SPI_FLASH_CE_S 22 DPORT_APP_CACHE_LOCK_3_EN_S 9 XCHAL_INT1_LEVEL 1 DPORT_APP_SLC0_INTR_MAP_S 0 PS_RING_MASK 0x000000C0 DPORT_APP_SPI1_DMA_INT_MAP_S 0 DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF TIMG_WDT_INT_CLR_V 0x1 __SIZEOF_INT__ 4 SPI_MISO_DELAY_MODE 0x00000003 ULLONG_MAX DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) ETS_CACHED_ADDR(addr) (addr) DPORT_PRO_SPI_INTR_3_MAP 0x0000001F DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) SPI_SLV_CMD_DEFINE_V 0x1 DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) XCHAL_DCACHE_IS_COHERENT 0 XCHAL_NUM_DATAROM 1 EFUSE_BLK3_DIN3_S 0 DPORT_IMMU_TABLE7_S 0 EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) cpu_write_dtlb RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF SPI_DMA_OUT_EOF_DES_ADDR_S 0 RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) EFUSE_DISABLE_JTAG (BIT(6)) FUNC_GPIO37_GPIO37 2 data_len SPI_FREAD_DIO_M (BIT(23)) RTC_CNTL_WAKEUP_ENA_V 0x7FF RTC_CNTL_SW_APPCPU_RST (BIT(4)) DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) SPI_USR_DUMMY_HOLD_M (BIT(20)) TIMG_T1_ALARM_HI_V 0xFFFFFFFF SPI_CS_HOLD (BIT(4)) ___int8_t_defined 1 RTC_CNTL_CPUSEL_CONF (BIT(29)) DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF UINT8_C(x) x DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) ETS_LEDC_INTR_SOURCE 43 XCHAL_INT21_EXTNUM 16 RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) TIMG_RTC_CALI_START_CYCLING_V 0x1 DPORT_EFUSE_CLK_EN (BIT(14)) EFUSE_READ_DONE_INT_ST_S 0 SPI_USR_PREP_HOLD_V 0x1 DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) RTC_CNTL_INTER_RAM2_PD_EN_S 27 TIMG_T0_ALARM_LO_S 0 RTC_CNTL_LOW_POWER_DIAG0_S 0 ETS_TG1_T1_LEVEL_INTR_SOURCE 19 DPORT_APP_OUT_VECBASE_SEL_V 0x3 DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) LLONG_MAX __LONG_LONG_MAX__ DPORT_APP_CACHE_MASK_OPSDRAM_S 5 DPORT_SHROM_MPU_TABLE2_S 0 RTC_CNTL_SCRATCH5_V 0xFFFFFFFF TIMG_LACT_INT_RAW_V 0x1 RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) DPORT_SHROM_MPU_TABLE5 0x00000003 SPI_TRANS_CNT_S 23 DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) EXCCAUSE_INSTR_RING 18 XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 TIMG_LACT_INT_ST_M (BIT(3)) EFUSE_CHIP_VER_DIS_CACHE_V 0x1 SPI_DMA_RX_EN (BIT(0)) DPORT_SW_BOOTLOADER_SEL (BIT(0)) DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) DPORT_APP_SLAVE_REQ_V 0x1 TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) EFUSE_BLK3_DOUT4_S 0 TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) SPI_SLV_RD_BUF_DONE_V 0x1 DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F DPORT_PRO_UART2_INTR_MAP_S 0 EFUSE_ABS_DONE_1_V 0x1 XCHAL_HAVE_DIV32 1 DPORT_PRO_PCNT_INTR_MAP 0x0000001F SPI_DMA_RX_EN_M (BIT(0)) EFUSE_BLK1_DOUT2 0xFFFFFFFF SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F __need_NULL DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 INT32_MIN (-2147483647L-1) DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) BIT10 0x00000400 DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) RTC_CNTL_WDT_STG2_HOLD_S 0 DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) DPORT_PERI_RST_EN_V 0xFFFFFFFF TIMG_RTC_CALI_MAX_S 16 PERIPHS_SPI_FLASH_C0 SPI_W0(1) TIMG_LACT_HI 0xFFFFFFFF DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) MEM_CACHE(offset) (uint8_t *)(0x3f400000 + (offset)) XCHAL_HAVE_TURBO16 0 DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) __UINT64_C(c) c ## ULL EFUSE_BLK2_DIN7 0xFFFFFFFF EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) EFUSE_BLK1_DIN5_S 0 RTC_CNTL_DIG_DBIAS_SLP 0x00000007 DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) SPI1_R_FAST_DUMMY_CYCLELEN 7 DPORT_APP_PWM1_INTR_MAP_S 0 SPI_FREAD_DIO_V 0x1 TIMG_NTIMERS_DATE_V 0xFFFFFFF SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58) RTC_CNTL_CK8M_FORCE_PU_V 0x1 TIMG_T0_LOAD_S 0 RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) DPORT_PRO_ROM_MPU_ENA_S 1 _ATEXIT_SIZE 32 DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S)) EFUSE_RD_ABS_DONE_0_M (BIT(4)) DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 RTC_MEM_PID_CONF_S (0) DPORT_SHROM_MPU_TABLE7_S 0 SPI_IN_SUC_EOF_INT_RAW_V 0x1 DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 DPORT_PRO_CPU_RECORDING_M (BIT(0)) DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF ets_printf DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF FUNC_GPIO27_GPIO27 2 DPORT_PRO_CACHE_IA_S 1 LLONG_MIN DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 EFUSE_KEY_STATUS (BIT(10)) SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF FUNC_GPIO24_GPIO24_0 0 RTC_CNTL_PVTMON_PU (BIT(26)) DPORT_APP_UART2_INTR_MAP_S 0 DR_REG_I2C_EXT_BASE 0x3ff53000 DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 FUNC_U0RXD_U0RXD 0 RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F XCHAL_HAVE_PIF_WR_RESP 0 PS_RING_SHIFT 6 SPI_CK_DIS_M (BIT(5)) RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) MESR_INSEXC 0x00000800 DPORT_PRODPORT_APB_MASK0_S 0 DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F REG_WRITE(_r,_v) (*(volatile uint32_t *)(_r)) = (_v) EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) RTC_CNTL_WIFI_PD_EN_M (BIT(30)) SPI_CLKDIV_PRE_V 0x1FFF DPORT_PRO_CACHE_VADDR 0x07FFFFFF _CONST const FUNC_GPIO26_EMAC_RXD1 5 RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 DPORT_APP_SPI_INTR_3_MAP_S 0 DPORT_MASK_APP_DRAM_V 0x1 EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) EFUSE_DISABLE_DL_DECRYPT_S 8 RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) EFUSE_BLK1_DIN3 0xFFFFFFFF DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) TIMG_WDT_INT_RAW_S 2 EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) DPORT_SHROM_MPU_TABLE4 0x00000003 DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF WRITE_PERI_REG(addr,val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) EFUSE_RD_FLASH_CRYPT_CNT_S 20 XCHAL_EXTINT14_NUM 19 RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 FUNC_GPIO22_EMAC_TXD1 5 DR_REG_GPIO_SD_BASE 0x3ff44f00 SPI_INLINK_START_S 29 RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 DPORT_CPU_INTR_FROM_CPU_2_V 0x1 DPORT_APP_DROM0ADDR0_IA 0x000FFFFF DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 DPORT_PRO_UART2_INTR_MAP 0x0000001F RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) DPORT_DMMU_TABLE3_S 0 RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) SPI_FWRITE_QUAD_S 13 SPI_SPEED_80M DPORT_DMMU_TABLE5_V 0x7F DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) DPORT_PRO_SPI_INTR_2_MAP_V 0x1F __int_fast8_t_defined 1 ESP_LOG_INFO SPI_MOSI_DELAY_NUM_S 23 RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) DPORT_PRO_PWM1_INTR_MAP_S 0 CONFIG_LOG_BOOTLOADER_LEVEL 2 DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 RTC_CNTL_TIME_VALID_INT_RAW_S 4 EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F DR_REG_RTCMEM2_BASE 0x3ff63000 DPORT_APP_UHCI0_INTR_MAP 0x0000001F RTC_CNTL_ANALOG_FORCE_NOISO_S 28 SPI_SYNC_RESET_M (BIT(31)) XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S)) DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) EXCCAUSE_DTLB_MULTIHIT 25 XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) SPI0_R_DIO_DUMMY_CYCLELEN 3 TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) RTC_CNTL_FORCE_PU_V 0x1 SPI_CACHE_REQ_EN_V 0x1 RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF XCHAL_INT24_EXTNUM 19 SPI_IN_SUC_EOF_INT_ENA (BIT(5)) RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 SPI_FLASH_WRSR (BIT(26)) DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF _AND , __SIG_ATOMIC_TYPE__ int DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) FUNC_SD_DATA3_SPIWP 1 SPI_SYNC_RESET (BIT(31)) SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) DPORT_PRO_SPI3_DMA_INT_MAP_S 0 DPORT_PRO_ROM_MPU_AD_S 0 SPI_USR_SRAM_DIO (BIT(1)) TIMG_T0_INCREASE_V 0x1 DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 DPORT_PRO_ROM_IA_V 0x1 ETS_TG1_LACT_EDGE_INTR_SOURCE 65 DPORT_PRO_MAC_INTR_MAP_S 0 DPORT_SPI_DECRYPT_ENABLE_V 0x1 EXCCAUSE_CP_DISABLED(n) (32+(n)) SPI_TX_CRC_DATA 0xFFFFFFFF SPI_OUT_EOF_INT_ST_S 7 RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) SPI_MOSI_DELAY_NUM_V 0x7 EFUSE_READ_DONE_INT_ST (BIT(0)) SPI_IN_SUC_EOF_INT_ST_V 0x1 SPI_SLV_LAST_STATE_S 20 BIT27 0x08000000 EFUSE_BLK3_DOUT1_V 0xFFFFFFFF SPI_WB_MODE 0x000000FF EFUSE_BLK2_DIN0_S 0 EXCCAUSE_INSTR_ADDR_ERROR 14 DPORT_APP_PWM2_INTR_MAP_V 0x1F MEMCTL_INV_EN_SHIFT 23 DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) DR_REG_GPIO_BASE 0x3ff44000 RTC_CNTL_DBG_ATTEN_V 0x3 SPI_CACHE_SRAM_USR_WCMD (BIT(28)) RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) _EXPARM(name,proto) (* name) proto DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) EFUSE_BLK2_DOUT3 0xFFFFFFFF SCHAR_MAX __SCHAR_MAX__ TIMG_T0_INCREASE (BIT(30)) DPORT_SHROM_MPU_TABLE19_V 0x3 DPORT_BT_LPCK_DIV_NUM_V 0xFFF DPORT_CPUPERIOD_SEL_S 0 DPORT_IMMU_TABLE9 0x0000007F EXCCAUSE_IFETCHERROR 2 TIMG_LACT_CPST_EN (BIT(8)) RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 DPORT_APP_I2S0_INT_MAP 0x0000001F EFUSE_BLK3_DIN7 0xFFFFFFFF SPI_SLAVE_MODE (BIT(30)) __SIZEOF_FLOAT__ 4 DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF EFUSE_SPI_PAD_CONFIG_HD_V 0x1F DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F RTC_CNTL_WDT_EN_M (BIT(31)) TIMG_T1_INT_ST (BIT(1)) SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) SPI_FLASH_BE_V 0x1 DPORT_APP_PWM3_INTR_MAP 0x0000001F EFUSE_BLK3_DIN0_V 0xFFFFFFFF DPORT_APP_SINGLE_IRAM_ENA_V 0x1 DPORT_APP_LEDC_INT_MAP_V 0x1F RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F DPORT_TIMERS_RST (BIT(0)) DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) DPORT_PRO_EMAC_INT_MAP_V 0x1F RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) SPI_SIZE_8MB XCHAL_ICACHE_LINE_LOCKABLE 0 XCHAL_EXCM_LEVEL 3 FUNC_GPIO17_GPIO17 2 XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_APP_CACHE_MASK_IRAM1_S 1 PERIPHS_SPI_FLASH_USRREG2 SPI_USER2(1) DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) TIMG_T1_EDGE_INT_EN_M (BIT(12)) RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) XCHAL_INTLEVEL7_MASK 0x00004000 DPORT_APPDPORT_APB_MASK0_S 0 WCHAR_MIN __WCHAR_MIN__ entry_t DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 __INT_LEAST8_TYPE__ signed char DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F XCHAL_INT17_LEVEL 1 RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 SPI_OUT_AUTO_WRBACK_V 0x1 DPORT_PRO_RX_END_V 0x1 DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F DPORT_SPI_DECRYPT_ENABLE_S 12 DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) EFUSE_FLASH_CRYPT_CONFIG 0x0000000F DPORT_APP_MMU_IA_INT_MAP 0x0000001F XCHAL_INT14_LEVEL 7 TIMG_LACT_EN_S 31 RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) DPORT_PRO_INTR_STATUS_0_S 0 DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) MESR_RCE_SHIFT 4 _SIZE_T_DEFINED DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) DEBUGCAUSE_DBREAK_MASK 0x04 SPI_OUTLINK_STOP_M (BIT(28)) DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 DPORT_RSA_PD (BIT(0)) EFUSE_BLK2_DIN2_S 0 RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) ETS_SLC0_INTR_SOURCE 10 SCHAR_MIN SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) SPI_IN_SUC_EOF_INT_CLR (BIT(5)) DPORT_PRO_TRACEMEM_ENA_S 0 XCHAL_ICACHE_LINEWIDTH 2 RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 SPI_USR_DUMMY_CYCLELEN_S 0 TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c) RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) RTC_CNTL_TXRF_I2C_PU_V 0x1 DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) TIMG_T1_AUTORELOAD_V 0x1 magic RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) SPI_BUF2 0xFFFFFFFF DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098) RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 SPI_IN_DONE_INT_ST_M (BIT(3)) address DPORT_APP_CACHE_ENABLE_M (BIT(3)) RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) DPORT_APP_BT_BB_NMI_MAP_V 0x1F RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) SPI_MISO_DELAY_MODE_S 16 DPORT_DMMU_TABLE13_S 0 RTC_CNTL_DBIAS_SLP 0x00000007 SPI_SLV_RDBUF_CMD_VALUE 0x000000FF DPORT_APP_CACHE_MASK_DROM0_V 0x1 EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) TIMG_T0_INCREASE_M (BIT(30)) _RAND48_SEED_1 (0xabcd) LOG_COLOR_CYAN "36" DPORT_TIMERGROUP_RST (BIT(13)) DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) XCHAL_USER_VECTOR_PADDR 0x40000340 EFUSE_READ_CMD_M (BIT(0)) XCHAL_VECBASE_RESET_VADDR 0x40000000 TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 DPORT_SHROM_MPU_TABLE21_V 0x3 RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 DPORT_PRO_I2S0_INT_MAP 0x0000001F SPI_CACHE_SRAM_USR_RCMD (BIT(5)) SPI_HOLD_TIME_V 0xF DPORT_PRO_DRAM1ADDR0_IA_S 0 REG_SET_FIELD(_r,_f,_v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f ##_S)))|(((_v) & (_f))<<(_f ##_S))))) DPORT_PRO_CACHE_MASK_DRAM1_S 3 PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF DPORT_PRO_CACHE_ENABLE_S 3 FUNC_MTMS_MTMS 0 FUNC_GPIO37_GPIO37_0 0 DPORT_APP_ROM_IA_S 3 DR_REG_EMAC_BASE 0x3ff69000 DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) __UINT_FAST8_TYPE__ unsigned int TIMG_LACT_AUTORELOAD (BIT(29)) DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F DPORT_PRO_MPU_IA_INT_MAP 0x0000001F DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c) RTC_CNTL_ULP_CP_INT_ENA_V 0x1 EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) RSR(reg,curval) asm volatile ("rsr %0, " #reg : "=r" (curval)); DPORT_PRO_BOOT_REMAP_M (BIT(0)) RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) FUNC_GPIO38_GPIO38 2 SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) TIMG_LACT_UPDATE 0xFFFFFFFF RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) RTC_CNTL_DREFM_SDIO 0x00000003 RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) DPORT_SHROM_MPU_TABLE13 0x00000003 DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 TIMG_LACT_INT_ENA_S 3 BIT0 0x00000001 SPI_IN_DONE_INT_ST_V 0x1 DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) _SIZET_ EFUSE_BLK3_DOUT6 0xFFFFFFFF RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) SPI_USR_SRAM_QIO_M (BIT(2)) get_bin_len DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) RTC_CNTL_CK8M_WAIT_V 0xFF DPORT_APP_LEDC_INT_MAP_S 0 __STRING(x) #x BIT17 0x00020000 SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) DPORT_APP_UHCI1_INTR_MAP_S 0 ETS_TIMER1_INTR_SOURCE 56 LONG_MIN (-LONG_MAX - 1L) RTC_CNTL_PLLA_FORCE_PU_V 0x1 SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) XCHAL_XLMI0_PADDR 0x3FF00000 TIMG_WDT_SYS_RESET_LENGTH 0x00000007 RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) DPORT_SW_BOOTLOADER_SEL_V 0x1 DPORT_APP_CACHE_MASK_IROM0_S 2 __need_size_t DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) __BIGGEST_ALIGNMENT__ 16 DR_REG_PWM1_BASE 0x3ff6C000 TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) DPORT_SHROM_MPU_TABLE10_V 0x3 SPI_OUT_DONE_INT_ENA_S 6 RTC_CNTL_SW_PROCPU_RST_S 5 EFUSE_BLK2_DOUT6_V 0xFFFFFFFF RTC_CNTL_WDT_INT_ST_S 3 XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) SPI_OUTLINK_ADDR 0x000FFFFF __SIZE_MAX__ 4294967295U __LDBL_MAX_10_EXP__ 308 EFUSE_BLK1_DIN7 0xFFFFFFFF SPI_SLV_RD_STA_DONE_V 0x1 DPORT_PRO_CAN_INT_MAP 0x0000001F _REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add) DPORT_SPI2_DMA_CHAN_SEL_S 2 EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F DPORT_SHROM_MPU_TABLE14_S 0 RTC_CNTL_SCRATCH2_V 0xFFFFFFFF XCHAL_UNALIGNED_STORE_HW 1 DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) TIMG_T1_INT_ST_M (BIT(1)) EFUSE_CK8M_FREQ_S 0 TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) DPORT_IMMU_TABLE3_V 0x7F DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F __ATOMIC_CONSUME 1 FUNC_GPIO18_HS1_DATA7 3 DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_CACHE_ENABLE_M (BIT(3)) ETS_GPIO_INTR_SOURCE 22 __LONG_MAX__ 2147483647L RTC_CNTL_REG1P8_READY_M (BIT(24)) TIMG_WDT_EN_M (BIT(31)) SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) SPI_FLASH_BE (BIT(23)) TIMG_T1_LOAD_HI 0xFFFFFFFF EFUSE_RD_SDIO_DREFL 0x00000003 TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) DPORT_RECORD_APP_PDEBUGSTATUS_S 0 DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF INTMAX_C(x) x ##LL RTC_CNTL_BROWN_OUT_INT_CLR_S 7 RTC_CNTL_XTL_FORCE_PD_S 12 SW_CPU_RESET DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF RTC_CNTL_REJECT_CAUSE_V 0xF DPORT_PRO_CACHE_STATE_V 0xFFF DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) SPI_INLINK_RESTART (BIT(30)) RTC_CNTL_DREFH_SDIO 0x00000003 RTC_CNTL_X32N_HOLD_FORCE_S 17 RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 XCHAL_HAVE_VECTORFPU2005 0 EFUSE_BLK3_DIN2 0xFFFFFFFF DPORT_BT_LPCK_DIV_NUM_S 0 XCHAL_EXTINT6_NUM 8 CONFIG_LOG_BOOTLOADER_LEVEL_WARN 1 TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF SPI_SLV_STATUS_BITLEN 0x0000001F DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) __VERSION__ "4.8.5" DPORT_CPUPERIOD_SEL 0x00000003 DPORT_APP_PWM1_INTR_MAP 0x0000001F DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) FUNC_GPIO27_EMAC_RX_DV 5 DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 DPORT_APP_SLC1_INTR_MAP_V 0x1F DR_REG_RTCCNTL_BASE 0x3ff48000 XCHAL_EXTINT21_NUM 26 RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 RTC_CNTL_XTL_FORCE_ISO_V 0x1 DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) DPORT_EFUSE_RST (BIT(14)) DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) RTC_CNTL_WDT_FEED (BIT(31)) RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 __FLT_MAX_EXP__ 128 DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 XCHAL_HAVE_MUL16 1 TIMG_T1_LO_S 0 _CAST_VOID (void) EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) _REENT_CHECK_SIGNAL_BUF(ptr) EFUSE_KEY_STATUS_V 0x1 FUNC_GPIO4_HS2_DATA1 3 DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F DPORT_AHB_LITE_MASK_SDIO (BIT(8)) DPORT_PRO_CACHE_MASK_DROM0_S 4 RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG DPORT_SPI_ENCRYPT_ENABLE_S 8 DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) DPORT_APP_WR_BAK_TO_READ_S 19 DPORT_APP_MMU_RDATA_V 0x1FF DPORT_APP_CACHE_LOCK_1_EN_V 0x1 INTRUSION_RESET PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) RTC_CNTL_DBG_ATTEN 0x00000003 DPORT_PRO_ROM_IA_M (BIT(1)) DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F MESR_DATEXC_SHIFT 10 DPORT_PRO_CACHE_LOCK_0_EN_S 6 EFUSE_RD_SDIO_FORCE_S 16 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F DPORT_PRO_CMMU_FORCE_ON_S 11 DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0) DPORT_DATE 0x0FFFFFFF DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) XCHAL_DATA_WIDTH 4 RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) EFUSE_INST_CONFIG_V 0xFF DPORT_APP_RWBT_IRQ_MAP 0x0000001F SPI_INLINK_ADDR 0x000FFFFF SPI_T_ERASE_ENA (BIT(31)) DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) TIMG_WDT_STG0_S 29 DR_REG_SLCHOST_BASE 0x3ff55000 RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) TIMG_LACT_CPST_EN_S 8 RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 RTC_CNTL_SLP_REJECT_INT_ST_S 1 SPI_T_ERASE_TIME_S 0 RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) XCHAL_HAVE_PIF 1 SPI_IN_DONE_INT_RAW_M (BIT(3)) RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) RTC_CNTL_ENB_CK8M_DIV_S 7 RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) DPORT_DMMU_TABLE4_V 0x7F EFUSE_READ_DONE_INT_RAW_S 0 RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) DPORT_SRAM_FO_1_M (BIT(0)) RTC_CNTL_SLP_REJECT_INT_RAW_S 1 DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) SPI_CK_OUT_EDGE_V 0x1 XCHAL_EXTINT17_NUM 22 XCHAL_HAVE_FLIX3 0 PS_PROG_MASK PS_UM_MASK RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) PS_OWB_SHIFT 8 DPORT_PRO_ROM_PD_M (BIT(0)) DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 RTC_CNTL_WDT_INT_RAW_S 3 SPI_CS_KEEP_ACTIVE (BIT(30)) SPI_CLKCNT_N 0x0000003F TIMG_CLK_EN_S 31 DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) TIMG_LACT_ALARM_HI_S 0 RTC_CNTL_WDT_STG3_V 0x7 SPI_FLASH_DP_M (BIT(21)) EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) attr DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) RTC_CNTL_SLP_VAL_HI 0x0000FFFF DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) DPORT_IMMU_TABLE1_S 0 DPORT_APP_CACHE_IA_INT_MAP_S 0 DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF XCHAL_HAVE_LOOPS 1 EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) SPI_BUF10_V 0xFFFFFFFF TIMG_T0_ALARM_EN (BIT(10)) SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) DPORT_APP_DROM0ADDR0_IA_S 0 RTC_CNTL_BBPLL_FORCE_PU_V 0x1 SPI_BUF5_S 0 DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F DPORT_APP_INTR_STATUS_2 0xFFFFFFFF RTC_CNTL_SDIO_FORCE_V 0x1 XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) XCHAL_HAVE_BBENEP 0 PS_PROG PS_UM XCHAL_HAVE_CONNXD2 0 XCHAL_HW_REL_LX6_0 1 RTC_CNTL_FASTMEM_FORCE_LPD_S 7 SPI_OUTLINK_ADDR_V 0xFFFFF RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 SPI_CLK_EQU_SYSCLK_V 0x1 PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 TIMG_T0_DIVIDER_S 13 RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 DPORT_BT_LPCK_DIV_B 0x00000FFF RTC_CNTL_WDT_INT_RAW_M (BIT(3)) __GNUC_PATCHLEVEL__ 5 EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) TIMG_T1_AUTORELOAD_M (BIT(29)) DPORT_SPI3_DMA_CHAN_SEL_V 0x3 SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) SPI_CS_SETUP_S 5 RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF SPI_IN_RST_V 0x1 DPORT_PRO_CPU_RECORDING (BIT(0)) EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) EFUSE_RD_ABS_DONE_1_S 5 DPORT_WIFI_BB_CFG 0xFFFFFFFF DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) XCHAL_HAVE_MP_INTERRUPTS 0 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF DPORT_PRO_RWBT_IRQ_MAP 0x0000001F DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F _REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state) __DBL_MIN_10_EXP__ (-307) DPORT_RECORD_PRO_PID 0x00000007 __need_size_t RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) XCHAL_SPANNING_WAY 0 SPI_SLAVE_MODE_M (BIT(30)) _NEWLIB_VERSION "2.0.0" __INT_MAX__ 2147483647 __GCC_ATOMIC_SHORT_LOCK_FREE 2 DPORT_LOWSPEED_CLK_SEL_V 0x1 XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) TIMG_LACT_INCREASE_S 30 DPORT_IMMU_TABLE10 0x0000007F DROM_HIGH 0x3F800000 DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF DPORT_DMMU_TABLE4_S 0 DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) _HAVE_LONG_DOUBLE 1 RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 XCHAL_INT0_LEVEL 1 DPORT_APP_BT_BB_NMI_MAP_S 0 DPORT_PIDGEN_IA 0x00000003 EFUSE_SPI_PAD_CONFIG_Q 0x0000001F RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) RTC_CNTL_XPD_SDIO_REG (BIT(31)) RTC_CNTL_BROWN_OUT_DET (BIT(31)) DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) TIMG_WDT_INT_ST_M (BIT(2)) SPI_RD_BYTE_ORDER_S 10 XCHAL_INT1_EXTNUM 1 __INT_LEAST32_TYPE__ long int SPI_USR_WR_SRAM_DUMMY_S 3 DPORT_APP_CACHE_LOCK_0_EN_V 0x1 FUNC_GPIO18_GPIO18 2 EFUSE_BLK2_DIN7_S 0 DPORT_APP_MMU_IA_INT_MAP_V 0x1F RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) INT_FAST64_MAX INT_LEAST64_MAX RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) DPORT_PRO_CACHE_TAG_PD_V 0x1 DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) SPI_IN_RST_M (BIT(2)) DPORT_LINK_DEVICE_SEL_S 8 DPORT_APP_CMMU_FORCE_ON_S 11 DPORT_PRO_PWM3_INTR_MAP 0x0000001F DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) EFUSE_BLK2_DOUT6_S 0 FUNC_GPIO17_U2TXD 4 DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) TIMG_T0_INT_ST_M (BIT(0)) DPORT_SHROM_MPU_TABLE23_S 0 SPI_USR_COMMAND_VALUE_S 0 TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) DPORT_SHROM_MPU_TABLE1_S 0 FUNC_MTDO_MTDO 0 DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) SPI_OUT_AUTO_WRBACK (BIT(8)) DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) LOG_COLOR_I LOG_COLOR(LOG_COLOR_GREEN) RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) SPI_CACHE_SRAM_USR_WCMD_S 28 DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90) PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) TIMG_T0_AUTORELOAD_M (BIT(29)) DROM_LOW 0x3F400000 DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF RTC_CNTL_INTER_RAM4_PD_EN_S 29 XCHAL_INT20_LEVEL 2 DPORT_SHROM_MPU_TABLE0_V 0x3 DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) DPORT_APP_ROM_IA_V 0x1 SPI_WRSR_2B_S 22 DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF SPI_IN_DONE_INT_ENA (BIT(3)) EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) DPORT_SPI_CLK_EN_1 (BIT(1)) EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) DPORT_CPU_INTR_FROM_CPU_1_S 0 TIMG_T0_INT_ENA_S 0 EFUSE_BLK1_DIN1_V 0xFFFFFFFF RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL FUNC_SD_CLK_SD_CLK 0 DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) DPORT_IMMU_TABLE0 0x0000007F SPI_CS1_DIS_V 0x1 DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) RTC_CNTL_SCRATCH2_S 0 SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 XCHAL_HAVE_OCD_DIR_ARRAY 0 DPORT_APP_TIMER_INT1_MAP_V 0x1F EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) LONG_LONG_MIN (-LONG_LONG_MAX - 1LL) EFUSE_BLK1_DOUT4 0xFFFFFFFF TIMG_T0_EN_V 0x1 memcpy XCHAL_CLOCK_GATING_GLOBAL 1 DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) __UINT_LEAST8_TYPE__ unsigned char RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) DPORT_SPI_RST (BIT(16)) RTC_CNTL_WDT_STG0 0x00000007 RTC_CNTL_PLL_BUF_WAIT 0x000000FF __GXX_ABI_VERSION 1002 SPI_SLV_WR_ST_V 0xFFFFFFFF DPORT_SHROM_MPU_TABLE1_V 0x3 SPI_IN_SUC_EOF_INT_CLR_S 5 SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 SPI_CS_HOLD_V 0x1 SPI_T_ERASE_TIME 0x00000FFF DPORT_APP_BT_BB_INT_MAP 0x0000001F SPI_T_PP_SHIFT_S 16 DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 EFUSE_CHIP_VER_DIS_BT_V 0x1 MEMCTL_SNOOP_EN 0x02 EXCCAUSE_INSTR_PROHIBITED 20 DPORT_APP_ROM_MPU_ENA (BIT(2)) LOG_COLOR_W LOG_COLOR(LOG_COLOR_BROWN) DPORT_IMMU_TABLE12 0x0000007F SPI_IN_LOOP_TEST (BIT(6)) EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 EFUSE_BLK3_DOUT7 0xFFFFFFFF SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38) EFUSE_DISABLE_DL_CACHE_V 0x1 SPI_IN_DONE_INT_ENA_V 0x1 DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) FUNC_GPIO16_U2RXD 4 RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) EFUSE_BLK1_DIN5 0xFFFFFFFF XCHAL_HAVE_GRIVPEP 0 RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 TIMG_T1_ALARM_LO 0xFFFFFFFF DPORT_IMMU_TABLE11_V 0x7F DPORT_SHROM_MPU_TABLE6 0x00000003 PS_INTLEVEL_MASK 0x0000000F DR_REG_TIMERGROUP0_BASE 0x3ff5F000 __WCHAR_MIN__ 0 BIT19 0x00080000 DPORT_APP_EFUSE_INT_MAP 0x0000001F DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 EFUSE_BLK3_DOUT2_S 0 DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) XCHAL_HAVE_CP 1 TIMG_RTC_CALI_START_CYCLING_S 12 DPORT_ROM_MPU_TABLE0_S 0 FUNC_GPIO39_GPIO39 2 DPORT_APP_DRAM_HL (BIT(14)) TIMG_WDT_STG0_HOLD_S 0 SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) DPORT_PRO_EFUSE_INT_MAP_S 0 DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F DPORT_SRAM_FO_0_V 0xFFFFFFFF RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) SPI_WR_BYTE_ORDER_M (BIT(11)) DPORT_AHBLITE_IA (BIT(10)) _STRING_H_ SPI_SRAM_QIO (BIT(1)) XCHAL_HAVE_DEBUG_EXTERN_INT 1 DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) RTC_CNTL_SDIO_PD_EN (BIT(21)) EFUSE_BLK2_DIN1 0xFFFFFFFF XCHAL_HW_MIN_VERSION_MAJOR 2600 SPI_SRAM_QIO_S 1 _REENT _impure_ptr DPORT_SRAM_FO_1 (BIT(0)) XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING PATH_MAX 4096 RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 TIMG_WDT_INT_ENA_M (BIT(2)) RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) SPI_FLASH_PP (BIT(25)) _SOC_EFUSE_REG_H_ DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 FUNC_GPIO27_GPIO27_0 0 TIMG_T0_INT_CLR_S 0 _SOC_CPU_H TIMG_T0_EN_M (BIT(31)) DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) SPI_SIZE_1MB XCHAL_EXTINT16_NUM 21 DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF EFUSE_DISABLE_DL_CACHE_M (BIT(9)) DPORT_DMMU_TABLE7_V 0x7F EFUSE_DISABLE_SDIO_HOST_S 3 _VA_LIST_ EFUSE_BLK3_DIN2_S 0 SPI_IN_DONE_INT_CLR (BIT(3)) SPI_SLV_RDBUF_DUMMY_EN_S 0 EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) RTC_CNTL_FORCE_NOISO_V 0x1 DPORT_PRO_RTC_CORE_INTR_MAP_S 0 RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) SPI_CLKCNT_L_V 0x3F EFUSE_BLK2_DOUT3_V 0xFFFFFFFF DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 SPI_SLV_LAST_STATE_V 0x7 RTC_CNTL_WDT_STG1_S 25 RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 DPORT_APP_OUT_VECBASE_SEL_S 0 DPORT_RECORD_PRO_PID_V 0x7 DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) DEBUGCAUSE_IBREAK_SHIFT 1 RTC_CNTL_TIME_UPDATE_S 31 EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 SPI_DMA_TX_STOP_M (BIT(15)) DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F INT_FAST32_MAX __STDINT_EXP(INT_MAX) SPI_CACHE_FLASH_PES_EN_M (BIT(3)) RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) EFUSE_DISABLE_DL_CACHE (BIT(9)) DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F FUNC_MTDO_GPIO15 2 MESR_ACCTYPE_SHIFT 20 RTC_CNTL_CK8M_FORCE_PD_V 0x1 SPI_OUTDSCR_BURST_EN_M (BIT(10)) DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) FUNC_GPIO32_GPIO32 2 SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 RTC_CNTL_WAIT_TIMER_V 0x1FF DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) XCHAL_DOUBLEEXC_VECOFS 0x000003C0 EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 _STDBOOL_H SPI_SLV_WRSTA_CMD_VALUE 0x000000FF DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) SPI_WB_MODE_V 0xFF EXCCAUSE_DIVIDE_BY_ZERO 6 DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) XCHAL_HW_MIN_VERSION_MINOR 3 EFUSE_CLK_EN_S 16 REG_GET_BIT(_r,_b) (*(volatile uint32_t*)(_r) & (_b)) FUNC_SD_DATA0_SD_DATA0 0 SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) DR_REG_TIMERGROUP1_BASE 0x3ff60000 SPI_DMA_RX_EN_V 0x1 __STDC_HOSTED__ 1 DPORT_SPI_DECRYPT_ENABLE (BIT(12)) DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) TIMG_T1_INCREASE (BIT(30)) DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) XCHAL_HAVE_THREADPTR 1 TIMG_T1_DIVIDER 0x0000FFFF EFUSE_RD_SDIO_DREFL_S 12 RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 DPORT_RSA_PD_V 0x1 RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 XCHAL_INST_FETCH_WIDTH 4 DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) DPORT_UART_ACCESS_GRANT_CONFIG_S 0 DPORT_PRO_PWM1_INTR_MAP 0x0000001F DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) XCHAL_HAVE_BSP3_TRANSPOSE 0 DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) DPORT_SHARE_ROM_PD 0x0000003F ULONG_MAX RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) SLP_DRV_S 5 DPORT_APP_CPU_RECORD_ENABLE_S 0 RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 __GNUC_VA_LIST DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134) __GCC_ATOMIC_CHAR_LOCK_FREE 2 ESP_LOG_NONE RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) DPORT_PRO_MAC_NMI_MAP_V 0x1F XCHAL_INT26_EXTNUM 21 SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108) DPORT_APP_SLC0_INTR_MAP_V 0x1F SPI_DMA_IN_STATUS_V 0xFFFFFFFF SPI_SETUP_TIME_V 0xF TIMG_T0_LEVEL_INT_EN (BIT(11)) DPORT_IMMU_TABLE2 0x0000007F TIMG_WDT_INT_RAW_V 0x1 __SIZEOF_DOUBLE__ 8 RTC_CNTL_ROM0_FORCE_PU (BIT(6)) TIMG_LACT_LOAD_HI_V 0xFFFFFFFF DPORT_SPI3_DMA_CHAN_SEL 0x00000003 DPORT_PRO_MAC_INTR_MAP_V 0x1F DRAM_ATTR __attribute__((section(".dram1"))) DR_REG_I2S1_BASE 0x3ff6D000 EFUSE_BLK1_DOUT5 0xFFFFFFFF DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 XCHAL_HAVE_EXTERN_REGS 1 DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F FUNC_GPIO4_EMAC_TX_ER 5 DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) RTC_CNTL_PLL_I2C_PU_M (BIT(31)) DPORT_PRO_SPI_INTR_0_MAP_S 0 RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) INT8_MAX 127 DPORT_DMMU_TABLE1 0x0000007F XCHAL_NUM_MISC_REGS 4 _XTENSA_CORE_CONFIGURATION_H DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4) XCHAL_HAVE_XEA2 1 __GNUC__ 4 ota_select EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) __DEFINED_size_t XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) SPI_TRANS_CNT_V 0xF DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) SPI_WR_BIT_ORDER (BIT(26)) DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) EXCCAUSE_CP7_DISABLED 39 RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) DPORT_APP_RWBLE_NMI_MAP_S 0 CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) RTC_CNTL_ROM0_FORCE_PU_V 0x1 EXCCAUSE_CP3_DISABLED 35 SLP_OE (BIT(0)) SPI_T_PP_ENA_V 0x1 TIMG_LACT_ALARM_LO_V 0xFFFFFFFF SPI_BUF4 0xFFFFFFFF DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) RTC_CNTL_PLL_I2C_PU_V 0x1 DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 RTC_CNTL_TIME_UPDATE_M (BIT(31)) __SYS_LOCK_H__ DR_REG_SLC_BASE 0x3ff58000 DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) SPI_CK_DIS (BIT(5)) DPORT_SHROM_MPU_TABLE5_V 0x3 DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 SPI_DOUTDIN_V 0x1 DPORT_AHB_LITE_MASK_PRO (BIT(0)) RTC_CNTL_SAR_INT_CLR (BIT(5)) DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) XCHAL_XEA_VERSION 2 FUNC_GPIO23_HS1_STROBE 3 RTC_CNTL_SCK_DCAP_V 0xFF DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) _EXFUN_NOTHROW(name,proto) name proto _NOTHROW DPORT_PRO_SLAVE_REQ (BIT(13)) RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) XCHAL_INT3_LEVEL 1 TIMG_LACT_CPST_EN_M (BIT(8)) RTC_CNTL_FASTMEM_PD_EN_S 14 RTC_CNTL_MAIN_TIMER_INT_ST_S 8 DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) WCHAR_MAX __WCHAR_MAX__ SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) DPORT_SHARE_ROM_FO_S 2 DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 SPI_CK_OUT_HIGH_MODE_V 0xF TIMG_LACT_LOAD_LO_V 0xFFFFFFFF SPI_MODE_QIO SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C) DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) DPORT_CPU_INTR_FROM_CPU_0_V 0x1 DPORT_IMMU_TABLE8_S 0 DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) INT_LEAST64_MAX 9223372036854775807LL DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) EFUSE_FLASH_CRYPT_CONFIG_S 28 SLP_PU (BIT(3)) FUNC_MTMS_SD_CLK 4 RTC_CNTL_SDIO_TIEH_S 23 DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 DPORT_PWM0_RST (BIT(17)) SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) DPORT_SHROM_MPU_TABLE15 0x00000003 RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) __INT32_TYPE__ long int SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) BIT2 0x00000004 XCHAL_HAVE_FUSION_VITERBI 0 EFUSE_RD_CHIP_VER_32PAD_M (BIT(2)) RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) SPI_INLINK_AUTO_RET_V 0x1 EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) __need_NULL EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) EXCCAUSE_LEVEL1_INTERRUPT 4 SPI_FWRITE_QUAD_V 0x1 DPORT_SHROM_MPU_TABLE17_V 0x3 INT32_C(x) x ##L SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F XCHAL_INT23_LEVEL 3 TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) EFUSE_SDIO_DREFL_V 0x3 DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) SPI_IN_DONE_INT_CLR_V 0x1 DPORT_PRO_ROM_PD (BIT(0)) EFUSE_RD_CHIP_VER_32PAD_V 0x1 SPI_TRANS_DONE_S 4 DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) __BOOT_CONFIG_H__ DPORT_PRO_CMMU_PD_M (BIT(12)) DPORT_LPCLK_SEL_8M_M (BIT(25)) SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF DPORT_PRO_CACHE_MODE_V 0x1 DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF DPORT_MASK_APP_IRAM (BIT(1)) DPORT_APP_MAC_INTR_MAP_S 0 DPORT_APP_CPU_PDEBUG_ENABLE_S 8 FUNC_GPIO19_GPIO19 2 FUNC_U0TXD_EMAC_RXD2 3 MEMCTL_SNOOP_EN_SHIFT 1 SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) SPI_FLASH_PES_M (BIT(17)) XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 DPORT_CAN_RST (BIT(19)) DPORT_APP_MAC_NMI_MAP_V 0x1F __UINTMAX_C(c) c ## ULL DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) INT64_MIN (-9223372036854775807LL-1LL) SPI_WR_BIT_ORDER_V 0x1 EFUSE_PGM_DONE_INT_CLR_S 1 DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F RTC_CNTL_SW_STALL_APPCPU_C0_S 0 DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) XCHAL_EXTINT23_NUM 28 DPORT_INTERNAL_SRAM_IA_V 0xFFF DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) SPI_IN_DONE_INT_RAW (BIT(3)) RTC_CNTL_PD_EN_S 20 RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) XCHAL_INTLEVEL1_MASK 0x000637FF FUNC_GPIO16_EMAC_CLK_OUT 5 EFUSE_ABS_DONE_0 (BIT(4)) SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) PS_WOE_SHIFT 18 RTC_CNTL_SOC_CLK_SEL 0x00000003 DPORT_APP_SPI_INTR_0_MAP_S 0 DPORT_IMMU_TABLE5_V 0x7F SPI_RD_BYTE_ORDER_V 0x1 DPORT_APP_TRACEMEM_ENA_S 0 RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) DPORT_SHROM_MPU_TABLE20 0x00000003 RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 SPI_AHBM_FIFO_RST_S 4 EFUSE_BLK3_DIN4 0xFFFFFFFF SPI_CK_OUT_LOW_MODE 0x0000000F RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) SPI_SLV_CMD_DEFINE (BIT(27)) DPORT_PRO_CACHE_LOCK_2_EN_S 8 XCHAL_HAVE_VECTRALX 0 SPI_OUT_DONE_INT_RAW (BIT(6)) DPORT_APP_SLAVE_WR_V 0x1 RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 __LDBL_HAS_DENORM__ 1 __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 EFUSE_DISABLE_DL_ENCRYPT_V 0x1 XCHAL_HW_REL_LX6_0_3 1 RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 DPORT_MASK_APP_IRAM_S 1 DPORT_LINK_DEVICE_SEL_V 0xFF PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) DPORT_APP_CACHE_STATE 0x00000FFF RTC_CNTL_SDIO_TIEH_V 0x1 TIMG_LACT_LOAD_V 0xFFFFFFFF EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) _GLOBAL_REENT _global_impure_ptr DPORT_MPU_IA_INT_EN 0x0001FFFF RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) SPI_BUF10_S 0 SPI_USR_MISO_DBITLEN_S 0 DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) SPI_STATUS 0x0000FFFF RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) __UINT16_C(c) c RTC_MEM_CRC_FINISH_M (BIT(31)) cpu_write_itlb SPI_USR_DUMMY (BIT(29)) __unbounded SPI_USR_MOSI_DBITLEN_V 0xFFFFFF SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4) TIMG_LACT_LOAD 0xFFFFFFFF DPORT_APP_RMT_INTR_MAP_V 0x1F RTC_CNTL_PVTMON_PU_S 26 TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) DPORT_PRO_DRAM_HL_S 16 DPORT_APP_SLAVE_WR_M (BIT(21)) DPORT_PRODPORT_APB_MASK1_S 0 TIMG_WDT_STG2_V 0x3 DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80) TIMG_WDT_STG0_HOLD 0xFFFFFFFF RTC_CNTL_PWC_FORCE_PU_V 0x1 DPORT_APP_RWBT_IRQ_MAP_V 0x1F DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) SPI_SRAM_BYTES_LEN_V 0xFF XCHAL_CLOCK_GATING_FUNCUNIT 1 TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) RTC_CNTL_DREFH_SDIO_S 29 DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F MESR_MEME 0x00000001 DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF DPORT_UART2_RST (BIT(23)) RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) partition RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) DPORT_PRO_UART1_INTR_MAP_V 0x1F DPORT_PRO_BT_BB_INT_MAP 0x0000001F TIMG_T1_ALARM_EN_V 0x1 SPI_SLV_WRSTA_DUMMY_EN_V 0x1 RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) ESP_LOGW(tag,format,...) ESP_EARLY_LOGW(tag, format, ##__VA_ARGS__) TIMG_LACT_LAC_EN_V 0x1 EFUSE_RD_ABS_DONE_1_V 0x1 SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) EFUSE_BLK2_DIN0 0xFFFFFFFF DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) DPORT_APP_SLAVE_REQ_S 13 DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) XCHAL_HAVE_RELEASE_SYNC 1 SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) RTC_CNTL_ENB_CK8M_M (BIT(6)) DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF __strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))); RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) DPORT_PRO_BOOT_REMAP (BIT(0)) ETS_UART1_INUM 5 SPI_FLASH_HPM_V 0x1 DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) DPORT_WIFI_BB_CFG_V 0xFFFFFFFF RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) RTC_CNTL_DBROWN_OUT_THRES_V 0x7 DPORT_PRO_EFUSE_INT_MAP 0x0000001F ETS_RWBT_INTR_SOURCE 6 TIMG_WDT_CPU_RESET_LENGTH_V 0x7 RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 SPI_CS_DELAY_MODE_V 0x3 _SOC_RTC_CNTL_REG_H_ RTC_CNTL_RESET_CAUSE_APPCPU_S 6 RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) SPI_IN_DONE_INT_ST (BIT(3)) ETS_TG0_T0_LEVEL_INTR_SOURCE 14 TIMG_WDT_LEVEL_INT_EN_S 21 DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) RTC_CNTL_WIFI_FORCE_NOISO_S 29 RTC_CNTL_BROWN_OUT_INT_ENA_S 7 RTC_CNTL_CPU_STALL_WAIT 0x0000001F DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) FUNC_GPIO17_GPIO17_0 0 SPI_FLASH_WREN_M (BIT(30)) DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_SPI_INTR_2_MAP 0x0000001F EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 DPORT_APP_CACHE_ENABLE_S 3 EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) RTC_CNTL_CPUSEL_CONF_S 29 TIMG_T1_INCREASE_S 30 __UINT_FAST16_MAX__ 4294967295U RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 set_cache_and_start_app RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF DPORT_AGC_MEM_FORCE_PD (BIT(1)) DPORT_PRO_UHCI0_INTR_MAP_V 0x1F EFUSE_DEC_WARNINGS_S 0 RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) extra_header DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) SPI1_R_DIO_ADDR_BITSLEN 31 DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF EFUSE_BLK2_DOUT7 0xFFFFFFFF FUNC_GPIO19_U0CTS 3 RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F _SYS__TYPES_H SPI_WR_BIT_ORDER_M (BIT(26)) XCHAL_HW_MIN_VERSION 260003 SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114) DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF _REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state) DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) SPI_CS_KEEP_ACTIVE_M (BIT(30)) EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) SPI_USR_MOSI_DBITLEN_S 0 EFUSE_BLK2_DOUT0_V 0xFFFFFFFF DPORT_APP_CACHE_TAG_FORCE_ON_S 8 XCHAL_SW_VERSION 1100003 CONFIG_LOG_COLORS 1 RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 SPI_INLINK_ADDR_S 0 EFUSE_CLK_SEL0_S 0 PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 TIMG_LACT_DIVIDER_V 0xFFFF RTC_CNTL_WDT_INT_RAW (BIT(3)) DPORT_SRAM_FO_1_V 0x1 DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) EFUSE_BLK2_DIN1_S 0 DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 XCHAL_DATAROM0_VADDR 0x3F400000 DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) DPORT_PRO_WDG_INT_MAP_S 0 FUNC_MTDI_EMAC_TXD3 5 RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c) EFUSE_BLK2_DOUT0_S 0 DPORT_PRO_PCNT_INTR_MAP_S 0 SPI_IN_DONE_INT_CLR_S 3 DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) DPORT_PRO_SPI_INTR_3_MAP_S 0 PART_SUBTYPE_DATA_OTA 0x00 DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF SPI_WP_REG (BIT(21)) DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) ETS_UART0_INTR_SOURCE 34 MEMCTL_DCWU_MASK 0x00001F00 EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) SPI_BUF0_V 0xFFFFFFFF DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144) RTC_CNTL_X32N_HOLD_FORCE_V 0x1 RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) RTC_CNTL_CK8M_FORCE_PD_S 25 DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) CONFIG_LOG_DEFAULT_LEVEL_INFO 1 SPI_CS_HOLD_DELAY_RES 0x00000FFF DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) XCHAL_PREFETCH_ENTRIES 0 MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" RTC_CNTL_WAIT_TIMER 0x000001FF TIMG_T1_EN_S 31 SLP_DRV 0x3 __DEC32_MIN_EXP__ (-94) _SIZE_T_DECLARED RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) XCHAL_DATAROM0_ECC_PARITY 0 TIMG_T1_UPDATE 0xFFFFFFFF RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) DPORT_SHROM_MPU_TABLE8_V 0x3 __lock_acquire(lock) (_CAST_VOID 0) __DEC32_MAX__ 9.999999E96DF SPI_USR (BIT(18)) EFUSE_SDIO_FORCE_V 0x1 __DBL_HAS_QUIET_NAN__ 1 __CHAR_UNSIGNED__ 1 TIMG_WDT_FEED_V 0xFFFFFFFF DPORT_APPDPORT_APB_MASK1_S 0 VALUE_GET_FIELD(_r,_f) (((_r) >> (_f ##_S)) & (_f)) RTC_CNTL_GPIO_REJECT_EN_V 0x1 RTC_CNTL_FORCE_PD (BIT(30)) DPORT_APP_INTRUSION_RECORD_S 0 FUNC_GPIO5_GPIO5_0 0 SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) RTC_CNTL_BBPLL_FORCE_PD_S 10 __FLT_DECIMAL_DIG__ 9 XCHAL_HAVE_EXCEPTIONS 1 RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) XCHAL_EXTINT4_NUM 4 XCHAL_INSTROM0_SIZE 4194304 RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) EFUSE_READ_DONE_INT_RAW_V 0x1 EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) RTC_CNTL_ENB_CK8M (BIT(6)) XCHAL_HAVE_FP 1 INT8_MIN -128 DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) SPI_T_ERASE_SHIFT_V 0xF DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) XCHAL_INT6_LEVEL 1 RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) __DBL_HAS_INFINITY__ 1 SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) DPORT_PRO_MAC_NMI_MAP_S 0 FUNC_GPIO5_GPIO5 2 UINT32_C(x) x ##UL EFUSE_RD_FLASH_CRYPT_CNT_V 0xFF XCHAL_INT17_EXTNUM 12 DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) DPORT_IMMU_PAGE_MODE 0x00000003 XCHAL_HAVE_MP_RUNSTALL 0 DPORT_PRO_CMMU_PD (BIT(12)) RTC_CNTL_DG_PAD_FORCE_ISO_S 13 SPI_BUF11 0xFFFFFFFF ULONG_MAX (LONG_MAX * 2UL + 1UL) RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) ETS_FROM_CPU_INTR1_SOURCE 25 RTC_CNTL_WDT_STG1_V 0x7 RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) SPI_BUF4_V 0xFFFFFFFF DPORT_APP_BT_MAC_INT_MAP_V 0x1F RTC_CNTL_CK8M_DFREQ 0x000000FF RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) SPI_BUF1_V 0xFFFFFFFF RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) EFUSE_DATE_S 0 DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) SPI_HOLD_TIME_S 4 TIMG_T0_HI_V 0xFFFFFFFF EFUSE_READ_CMD_V 0x1 XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS uint16_t DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) SPI_USR_SRAM_DIO_S 1 __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF __STDC__ 1 esp_log_level_t __Long long DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF EFUSE_DISABLE_JTAG_S 6 SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) TIMG_T1_INT_RAW_S 1 FUNC_U0TXD_GPIO1 2 DPORT_RSA_PD_S 0 DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 XCHAL_INT26_LEVEL 5 _PTR void * SPI_BUF13_V 0xFFFFFFFF FUNC_GPIO22_VSPIWP 1 DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) ___int16_t_defined 1 RTC_CNTL_SLP_WAKEUP_S 29 RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) DPORT_CAN_CLK_EN (BIT(19)) TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF SPI_T_ERASE_TIME_V 0xFFF DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) RTC_CNTL_FASTMEM_FORCE_ISO_S 1 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) LOG_COLOR_PURPLE "35" RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) DPORT_RMT_RST (BIT(9)) TIMG_CLK_EN_V 0x1 DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F DPORT_APP_RMT_INTR_MAP_S 0 DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F DPORT_MASK_AHB_S 4 DPORT_APP_TX_END_V 0x1 DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) XCHAL_INTLEVEL6_VECOFS 0x00000280 RTC_CNTL_WAKEUP_CAUSE 0x000007FF PART_SUBTYPE_END 0xff EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) EFUSE_DISABLE_JTAG_V 0x1 PS_PROGSTACK_SHIFT PS_UM_SHIFT DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) DPORT_DMMU_TABLE9_V 0x7F DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F XCHAL_HW_VERSION_MAJOR 2600 FUNC_GPIO20_GPIO20_0 0 LOG_LOCAL_LEVEL ((esp_log_level_t) CONFIG_LOG_BOOTLOADER_LEVEL) DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) TIMG_T1_ALARM_EN_S 10 DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_ANALOG_FORCE_ISO_S 25 ota_seq EFUSE_CK8M_FREQ 0x000000FF SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28) SPI_MASTER_CK_SEL 0x0000001F DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) EXCCAUSE_INSTR_DATA_ERROR 12 RTC_CNTL_XPD_SDIO_REG_V 0x1 SPI_SLV_RDATA_BIT 0x00FFFFFF RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 TIMG_T0_LEVEL_INT_EN_S 11 RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) SPI_FWRITE_DUAL_M (BIT(12)) DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) MESR_DME_SHIFT 1 DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F TIMG_LACT_INT_ST (BIT(3)) RTC_CNTL_PLL_FORCE_ISO_V 0x1 RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) SPI_CS2_DIS_S 2 DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF SPI_USR_COMMAND_VALUE_V 0xFFFF __UINT_FAST64_MAX__ 18446744073709551615ULL EFUSE_DEBUG_V 0xFFFFFFFF DPORT_SHROM_MPU_TABLE8 0x00000003 PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64) DPORT_APP_CACHE_FLUSH_DONE_S 5 XCHAL_NUM_AREGS_LOG2 6 DPORT_APP_DRAM_HL_M (BIT(14)) XCHAL_MMU_ASID_BITS 0 XCHAL_HAVE_TAP_MASTER 0 DPORT_PRO_OPSDRAMADDR_IA_S 0 DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) EFUSE_DISABLE_SDIO_HOST (BIT(3)) RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 SPI_USR_RD_SRAM_DUMMY_S 4 DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) RTC_CNTL_XTL_FORCE_PU_S 13 XCHAL_EXTINT18_NUM 23 SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 TIMG_T1_ALARM_LO_S 0 EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) DPORT_SHARE_ROM_IA 0x0000000F EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) EFUSE_ABS_DONE_1 (BIT(5)) __lock_close_recursive(lock) (_CAST_VOID 0) XCHAL_INTLEVEL2_VECOFS 0x00000180 EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) SPI_USR_COMMAND_M (BIT(31)) RTC_CNTL_DBROWN_OUT_THRES 0x00000007 SCHAR_MIN (-SCHAR_MAX - 1) SPI_T_ERASE_ENA_V 0x1 SPI_CLKCNT_N_V 0x3F SPI_OUT_EOF_MODE_V 0x1 RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 SPI_FLASH_WRDI_M (BIT(29)) XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) RTC_CNTL_WDT_INT_ENA (BIT(3)) __INT64_C(c) c ## LL DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) RTC_CNTL_ROM0_FORCE_NOISO_S 17 DPORT_APP_ROM_MPU_AD_M (BIT(2)) DPORT_SLAVE_SPI_MASK_PRO_S 0 SPI_CACHE_SRAM_USR_RCMD_S 5 EFUSE_RD_INST_CONFIG 0x000000FF __GCC_ATOMIC_LONG_LOCK_FREE 2 EFUSE_BLK1_DOUT5_V 0xFFFFFFFF DPORT_APP_EMAC_INT_MAP 0x0000001F DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F SPI_FREAD_QIO (BIT(24)) DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 WINT_MAX __WINT_MAX__ SPI_CACHE_REQ_EN_M (BIT(0)) DPORT_PRO_CACHE_MMU_IA_S 0 RTC_CNTL_TIME_UPDATE (BIT(31)) DPORT_MAC_DUMP_MODE 0x00000003 RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) __DBL_MANT_DIG__ 53 ETS_TG1_WDT_LEVEL_INTR_SOURCE 20 RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) RTC_CNTL_DIG_DBIAS_SLP_V 0x7 DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) XCHAL_WINDOW_UF12_VECOFS 0x00000140 RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) RTC_CNTL_DTEST_RTC 0x00000003 RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) EFUSE_BLK3_DIN7_V 0xFFFFFFFF DPORT_MASK_AHB_V 0x1 RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF XCHAL_HAVE_PREFETCH_L1 0 DPORT_DMMU_TABLE4 0x0000007F TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F EXCCAUSE_EXCCAUSE_MASK 0x3F DPORT_PRO_CPU_RECORDING_V 0x1 DPORT_PRO_SPI2_DMA_INT_MAP_S 0 RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) SPI_OUT_DATA_BURST_EN_S 12 DPORT_AHBLITE_IA_V 0x1 DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) DPORT_PRO_ROM_FO_M (BIT(0)) EFUSE_BLK2_DIN6_V 0xFFFFFFFF XCHAL_USER_VECOFS 0x00000340 DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) XCHAL_NMI_VECOFS 0x000002C0 TIMG_WDT_INT_ST_V 0x1 DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF LONG_MAX __LONG_MAX__ SPI_OUT_EOF_INT_RAW_S 7 SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) SPI_SLV_RDSTA_CMD_VALUE_S 16 DPORT_UART_MEM_CLK_EN (BIT(24)) bool _Bool DPORT_PRO_RMT_INTR_MAP_V 0x1F RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 FUNC_SD_CLK_U1CTS 4 TIMG_T1_INT_ENA_M (BIT(1)) RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140) __ELF__ 1 TIMG_T1_LOAD_LO_V 0xFFFFFFFF DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 RTC_CNTL_CK8M_DFREQ_V 0xFF DPORT_DMMU_TABLE3 0x0000007F DPORT_PRO_RSA_INTR_MAP_S 0 SPI_FREAD_DUAL_V 0x1 EXCCAUSE_ILLEGAL 0 DPORT_BT_ACCESS_GRANT_CONFIG_S 0 DPORT_APP_OPSDRAMADDR_IA_S 0 TIMG_RTC_CALI_VALUE_S 7 RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) UINTMAX_C(x) x ##ULL DPORT_TIMERGROUP1_CLK_EN (BIT(15)) RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) SPI_SLV_LAST_STATE 0x00000007 DPORT_RECORD_APP_PID_S 0 __INTPTR_TYPE__ int SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48) RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF TIMG_WDT_INT_ENA (BIT(2)) DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF NO_MEAN FUNC_MTMS_EMAC_TXD2 5 RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 XCHAL_HAVE_ADDX 1 CONFIG_PYTHON "python" TIMG_T0_LOAD_LO_V 0xFFFFFFFF DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) MEMCTL_ICWU_SHIFT 18 SPI_BUF6 0xFFFFFFFF RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) TIMG_LACT_INT_CLR_V 0x1 RTC_CNTL_MIN_SLP_VAL_S 8 DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) SPI_DMA_TX_STOP_S 15 DPORT_IMMU_TABLE2_S 0 RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 XCHAL_UNALIGNED_STORE_EXCEPTION 0 EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) DPORT_PRO_RSA_INTR_MAP_V 0x1F DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) XCHAL_HAVE_CACHE_BLOCKOPS 0 TIMG_T0_LOAD_HI_S 0 __flexarr [0] RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) DPORT_PRO_IROM0ADDR_IA_S 0 DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) UINT64_C(x) x ##ULL DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) SPI_BUF6_S 0 RTC_CNTL_BROWN_OUT_DET_S 31 DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 DPORT_PRO_EMAC_INT_MAP 0x0000001F RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 DPORT_PRO_AHB_SPI_REQ_V 0x1 RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) DPORT_APP_UART1_INTR_MAP 0x0000001F EFUSE_RD_SDIO_TIEH (BIT(15)) _REENT_STRTOK_LAST(ptr) ((ptr)->_new._reent._strtok_last) DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 TIMG_LACT_EN (BIT(31)) RTC_CNTL_ENB_CK8M_S 6 SPI_FWRITE_DUAL (BIT(12)) DPORT_APPCPU_RESETTING_V 0x1 WSR(reg,newval) asm volatile ("wsr %0, " #reg : : "r" (newval)); FUNC_GPIO4_GPIO4 2 SPI_CACHE_FLASH_USR_CMD_V 0x1 DPORT_APP_PWM1_INTR_MAP_V 0x1F RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 DR_REG_DPORT_BASE 0x3ff00000 RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) DPORT_AHB_SPI_REQ_V 0x1 RTC_CNTL_BROWN_OUT_RST_ENA_S 26 DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) EFUSE_SPI_PAD_CONFIG_D_V 0x1F EFUSE_FLASH_CRYPT_CONFIG_V 0xF DPORT_DMMU_TABLE11 0x0000007F DPORT_APP_CACHE_MMU_IA_CLR_S 13 DPORT_APP_DRAM_HL_S 14 DPORT_PERI_IO_SWAP_V 0xFF RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) irom_size DPORT_PRO_TIMER_INT1_MAP 0x0000001F DPORT_PRO_TIMER_INT1_MAP_S 0 __SYS_CONFIG_H__ ETS_FROM_CPU_INUM 2 TIMG_T1_AUTORELOAD (BIT(29)) RTC_CNTL_WIFI_FORCE_ISO_V 0x1 RTC_CNTL_GPIO_REJECT_EN_S 24 EFUSE_BLK3_DIN2_V 0xFFFFFFFF SPI_FLASH_RDSR_V 0x1 DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) DEBUGCAUSE_BREAK_SHIFT 3 RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) DPORT_BT_LPCK_DIV_A_V 0xFFF PART_SUBTYPE_FACTORY 0x00 RTC_CNTL_EXT_WAKEUP1_LV_S 31 RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) __ORDER_PDP_ENDIAN__ 3412 RTC_CNTL_SAR_INT_ST_S 5 SPI_USR_DUMMY_M (BIT(29)) PS_PROGSTACK_MASK PS_UM_MASK DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) XCHAL_INT5_EXTNUM 5 RTC_CNTL_WDT_STG1_HOLD_S 0 _REENT_CHECK_RAND48(ptr) ARG_MAX 4096 SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) SPI_CACHE_FLASH_PES_EN_V 0x1 DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) RTC_MEM_CRC_FINISH (BIT(31)) DPORT_BTEXTWAKEUP_REQ_S 12 __UINT_LEAST64_MAX__ 18446744073709551615ULL XCHAL_INT9_LEVEL 1 RTC_CNTL_SCRATCH4_V 0xFFFFFFFF SPI_WRSR_2B_M (BIT(22)) SPI_IN_ERR_EOF_INT_ENA (BIT(4)) DPORT_APP_TIMER_INT1_MAP_S 0 partition_pos_t RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) SPI_MOSI_DELAY_NUM 0x00000007 EFUSE_RD_SDIO_DREFM_S 10 DPORT_APP_BT_BB_NMI_MAP 0x0000001F RTC_CNTL_DIG_DBIAS_WAK 0x00000007 DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) EFUSE_SDIO_DREFM 0x00000003 SPI_USR_DIN_HOLD_S 19 RTC_CNTL_ENT_RTC_M (BIT(29)) RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) ETS_ETH_MAC_INTR_SOURCE 38 DPORT_DMMU_TABLE10_V 0x7F RTC_CNTL_ROM0_FORCE_PD (BIT(5)) DPORT_BT_LPCK_DIV_B_S 0 DPORT_LEDC_RST (BIT(11)) XCHAL_HAVE_FUSION_FP 0 _ATTRIBUTE(attrs) __attribute__ (attrs) TIMG_WDT_STG1 0x00000003 DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF FUNC_GPIO33_GPIO33_0 0 TIMG_T0_ALARM_EN_V 0x1 DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F DPORT_APP_ROM_IA (BIT(3)) EFUSE_CHIP_VER_DIS_BT_S 1 DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) __GNUC_STDC_INLINE__ 1 TIMG_WDT_LEVEL_INT_EN_M (BIT(21)) DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) DPORT_PRO_SLAVE_REQ_V 0x1 DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 RTC_CNTL_TOUCH_INT_RAW_S 6 RTC_CNTL_MIN_SLP_VAL_V 0xFF TIMG_T0_ALARM_HI_S 0 EFUSE_BLK2_DOUT7_S 0 DPORT_PWM2_CLK_EN (BIT(25)) TIMG_T0_UPDATE_V 0xFFFFFFFF SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4) __INT16_MAX__ 32767 SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 SPI_USR_COMMAND_S 31 DPORT_WIFI_RST 0xFFFFFFFF SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) FUNC_GPIO21_EMAC_TX_EN 5 INT16_MIN -32768 HAVE_INITFINI_ARRAY 1 DPORT_PRO_RWBLE_NMI_MAP_V 0x1F XCHAL_INT29_LEVEL 3 SPI_INLINK_STOP_M (BIT(28)) RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) SPI_USR_COMMAND_BITLEN_V 0xF __EXP(x) __ ##x ##__ DPORT_ROM_MPU_TABLE1_S 0 DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F _EXFNPTR(name,proto) (* name) proto DPORT_APP_DRAM_HL_V 0x1 DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F DPORT_PRO_ROM_FO_S 0 INT_LEAST64_MIN (-9223372036854775807LL-1LL) XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 TIMG_RTC_CALI_RDY_S 15 DPORT_APPCPU_CLKGATE_EN (BIT(0)) DPORT_PRO_SPI_INTR_3_MAP_V 0x1F RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF CACHE_READ_32(offset) ((uint32_t *)(0x3f400000 + (offset))) __INT32_MAX__ 2147483647L EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) DPORT_SHROM_MPU_TABLE22 0x00000003 RTC_CNTL_TIME_HI_S 0 UINT_FAST32_MAX (__STDINT_EXP(INT_MAX)*2U+1U) SPI_RD_BYTE_ORDER_M (BIT(10)) TIMG_T0_INT_RAW_M (BIT(0)) EFUSE_BLK3_DIN6 0xFFFFFFFF RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) DPORT_APP_SPI_INTR_1_MAP_V 0x1F DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 SPI_IN_RST (BIT(2)) TIMG_LACT_LOAD_LO_S 0 DPORT_CPU_INTR_FROM_CPU_2_S 0 BIT4 0x00000010 DPORT_LPCLK_SEL_XTAL32K (BIT(27)) SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) drom_page_count RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 TIMG_WDT_INT_RAW (BIT(2)) DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F RTC_CNTL_TOUCH_INT_ST (BIT(6)) SPI_MASTER_CS_POL_V 0x1F DPORT_AHB_LITE_MASK_APP_M (BIT(4)) DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F DPORT_APP_ROM_PD_V 0x1 RTC_CNTL_SDIO_REJECT_EN_S 25 FIELD_TO_VALUE2(_f,_v) (((_v)<<_f ##_S) & (_f)) DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F DPORT_SPI_CLK_EN_2 (BIT(6)) EFUSE_WIFI_MAC_CRC_HIGH_S 0 SPI_SLV_RDSTA_DUMMY_EN_S 2 SPI_MODE_FAST_READ load_rtc_memory DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_WDT_WKEY 0xFFFFFFFF XCHAL_EXTINT25_NUM 31 RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 XCHAL_NUM_INTERRUPTS 32 RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 INT_LEAST32_MIN (-2147483647L-1) SPI0_R_FAST_ADDR_BITSLEN 23 TIMG_RTC_CALI_RDY (BIT(15)) RTC_CNTL_ADC1_HOLD_FORCE_S 0 CHAR_MAX UCHAR_MAX DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F TIMG_WDT_STG1_S 27 RTC_CNTL_SCK_DCAP_FORCE_S 7 DPORT_AGC_MEM_FORCE_PU (BIT(0)) SPI_DATE_V 0xFFFFFFF RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) RTC_CNTL_SCRATCH5_S 0 RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 _ROM_ETS_SYS_H_ __FLT_EPSILON__ 1.1920928955078125e-7F DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) SPI_IN_ERR_EOF_INT_CLR (BIT(4)) __bool_true_false_are_defined 1 ___int64_t_defined 1 TIMG_LACT_LAC_EN_M (BIT(9)) TIMG_WDT_INT_ENA_V 0x1 RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) DPORT_PRO_RWBT_NMI_MAP_S 0 __DEC32_MAX_EXP__ 97 DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) SPI_USR_ADDR_M (BIT(30)) DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) FUNC_SD_CLK_HS1_CLK 3 SPI_FLASH_PES_V 0x1 SPI_CS_I_MODE 0x00000003 RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) __INT_LEAST16_TYPE__ short int EFUSE_BLK3_DOUT3_S 0 DPORT_PRO_PWM3_INTR_MAP_V 0x1F EFUSE_BLK2_DIN2 0xFFFFFFFF RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 DPORT_PRO_ROM_MPU_ENA (BIT(1)) PART_TYPE_APP 0x00 RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) EFUSE_RD_CHIP_VER_32PAD (BIT(2)) EXCCAUSE_LOAD_STORE_DATA_ERROR 13 FUN_PU (BIT(8)) DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) DPORT_AHB_ACCESS_GRANT_0_S 0 SPI_USR_MISO (BIT(28)) TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) FUNC_MTDI_MTDI 0 DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 SPI_OUT_DONE_INT_ENA_M (BIT(6)) DPORT_APP_INTRUSION_RECORD_V 0xF TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S)) _GCC_WRAP_STDINT_H TIMG_WDT_STG2_HOLD 0xFFFFFFFF EFUSE_DAC_CLK_PAD_SEL (BIT(8)) SPI_OUT_EOF_INT_ST (BIT(7)) MESR_DATEXC 0x00000400 XCHAL_NUM_INTERRUPTS_LOG2 5 DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_SLEEP_EN (BIT(31)) DPORT_SHROM_MPU_TABLE15_V 0x3 mmu_init DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) SPI_USR_ADDR_VALUE_S 0 XCHAL_HAVE_HIFI2 0 DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F __warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous") TIMG_LACT_RTC_ONLY_M (BIT(7)) RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 __need___va_list SPI_CS_DELAY_NUM_V 0xF RTC_MEM_CRC_ADDR (0x7ff) RTC_CNTL_XTL_FORCE_PD (BIT(12)) DPORT_DATE_S 0 XCHAL_INT23_EXTNUM 18 DPORT_APP_DRAM_SPLIT_S 11 RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER RTC_CNTL_FORCE_PU_S 31 _REENT_MP_RESULT(ptr) ((ptr)->_result) DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) SPI_IN_ERR_EOF_INT_CLR_S 4 SpiFlashOpResult RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 XCHAL_NUM_DBREAK 2 DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) SPI_RESANDRES_V 0x1 DPORT_PRO_RX_END_M (BIT(23)) DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) SPI_USR_HOLD_POL (BIT(17)) FUNC_GPIO4_SD_DATA1 4 EFUSE_BLK3_DOUT5_V 0xFFFFFFFF XCHAL_INT25_LEVEL 4 RTC_CNTL_XTL_FORCE_PU_V 0x1 SPI1_R_QIO_ADDR_BITSLEN 31 EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) ROMFN_ATTR XCHAL_NUM_INTLEVELS 6 SPI_CK_IDLE_EDGE_M (BIT(29)) DPORT_RECORD_APP_PDEBUGDATA_S 0 PERIPHS_SPI_FLASH_C3 SPI_W3(1) RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state) boot_cache_redirect SPI_FLASH_BUSY_FLAG BIT0 EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) DPORT_UHCI0_CLK_EN (BIT(8)) FUNC_GPIO22_GPIO22_0 0 TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) EFUSE_RD_KEY_STATUS (BIT(10)) _NOTHROW DPORT_APP_BT_BB_INT_MAP_V 0x1F DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S)) DPORT_IMMU_TABLE14_S 0 RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF DPORT_AGC_MEM_FORCE_PD_V 0x1 DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F __UINT32_MAX__ 4294967295UL RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) EFUSE_SPI_PAD_CONFIG_HD_S 4 DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) SPI_USR_DUMMY_IDLE_S 26 RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) DPORT_IMMU_TABLE15_S 0 XCHAL_INSTRAM0_ECC_PARITY 0 XCHAL_HAVE_SPANNING_WAY 1 RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) TIMG_LACT_INT_CLR_S 3 DPORT_MASK_PRO_IRAM_S 0 EFUSE_CLK_SEL0 0x000000FF MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK) DPORT_PRO_MPU_IA_INT_MAP_S 0 __FLT_MIN_EXP__ (-125) DPORT_APP_CACHE_MODE_V 0x1 RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) DR_REG_UART1_BASE 0x3ff50000 DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) SPI_SLV_WR_RD_BUF_EN_S 29 BIT13 0x00002000 SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) SPI_USR_DUMMY_S 29 DPORT_UART_CLK_EN (BIT(2)) DPORT_IMMU_TABLE4 0x0000007F ETS_BT_HOST_INUM 1 DPORT_WIFI_CLK_EN_V 0xFFFFFFFF EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124) DPORT_LOWSPEED_CLK_SEL (BIT(2)) TIMG_T0_DIVIDER_V 0xFFFF _REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam) XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 EFUSE_BLK1_DOUT7 0xFFFFFFFF DPORT_APP_MAC_INTR_MAP 0x0000001F SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F DPORT_ROM_MPU_TABLE2_V 0x3 EFUSE_RD_CHIP_VER_RESERVE 0x000000FF DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) SPI_SLV_WR_BUF_DONE_M (BIT(1)) RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F RTC_CNTL_SLEEP_EN_M (BIT(31)) DPORT_PRO_CAN_INT_MAP_V 0x1F XCHAL_HAVE_MUL32_HIGH 1 DPORT_PRO_EMAC_INT_MAP_S 0 RTC_CNTL_PWC_FORCE_PU (BIT(19)) RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) DPORT_APP_EMAC_INT_MAP_S 0 DPORT_PRO_RMT_INTR_MAP_S 0 XCHAL_HAVE_FUSION_CONVENC 0 SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) XCHAL_INSTRAM0_PADDR 0x40000000 DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F TIMG_WDT_STG0_V 0x3 DPORT_PERI_CLK_EN 0xFFFFFFFF XCHAL_INSTROM0_PADDR 0x40800000 DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) SPI_FLASH_BP2 BIT4 RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) TIMG_T0_INCREASE_S 30 TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) EFUSE_BLK3_DIN4_V 0xFFFFFFFF DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94) DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) DPORT_PRO_PWM3_INTR_MAP_S 0 RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 TIMG_LACT_HI_V 0xFFFFFFFF SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) DPORT_LOWSPEED_CLK_SEL_S 2 RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) RTC_CNTL_RST_BIAS_I2C_V 0x1 DPORT_PRO_WDG_INT_MAP_V 0x1F _REENT_CHECK_MISC(ptr) DPORT_SRAM_FO_0 0xFFFFFFFF TIMG_WDT_FEED 0xFFFFFFFF DPORT_IMMU_TABLE14 0x0000007F SPI_CLKCNT_L_S 0 XCHAL_MMU_RINGS 1 XCHAL_DATARAM0_ECC_PARITY 0 __UINT64_TYPE__ long long unsigned int SPI_INLINK_START_V 0x1 XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER DPORT_APP_I2S1_INT_MAP 0x0000001F RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 DPORT_RSA_PD_M (BIT(0)) FUNC_GPIO2_HS2_DATA0 3 SPI_OUT_EOF_INT_ENA_V 0x1 RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) INT32_MAX 2147483647L RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF XCHAL_HAVE_DFP_ACCEL 1 RTC_CNTL_TIME_HI_V 0xFFFF DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) RTC_CNTL_XTL_FORCE_NOISO_S 26 SPI_USR_DUMMY_IDLE (BIT(26)) DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F XCHAL_HAVE_BBP16 0 XCHAL_INSTRAM0_SIZE 4194304 RTC_DATA_LOW 0x50000000 irom_addr RTC_CNTL_BROWN_OUT_DET_V 0x1 RTC_CNTL_BBPLL_FORCE_PU_S 11 TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S)) SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) XCHAL_INT22_LEVEL 3 DPORT_IMMU_TABLE8_V 0x7F RTC_CNTL_PD_EN (BIT(20)) XCHAL_HAVE_IDENTITY_MAP 1 RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 DPORT_APP_IRAM1ADDR_IA 0x000FFFFF POWERON_RESET ETS_I2C_EXT0_INTR_SOURCE 49 DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__ XCHAL_HAVE_USER_SPFPU 0 flash_encrypt DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) __ESP_LOG_H__ SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 SPI_CK_OUT_EDGE_M (BIT(7)) RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) DPORT_APP_RX_END_M (BIT(23)) SPI_CS_I_MODE_S 10 DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) _MB_LEN_MAX 1 RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 RTC_CNTL_DBIAS_WAK 0x00000007 FUNC_SD_DATA2_SPIHD 1 XCHAL_HAVE_CACHEATTR 0 ETS_SDIO_HOST_INTR_SOURCE 37 _DEFUN(name,arglist,args) name(args) EFUSE_BLK2_DIN3_V 0xFFFFFFFF SPI_INLINK_RESTART_S 30 SPI_CS_DELAY_MODE 0x00000003 DPORT_PRO_MAC_INTR_MAP 0x0000001F EFUSE_XPD_SDIO_REG (BIT(14)) PS_EXCM_MASK 0x00000010 SPI_USR_WR_SRAM_DUMMY_V 0x1 XCHAL_ICACHE_ACCESS_SIZE 1 SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) DPORT_APP_CACHE_VADDR_S 0 SPI_OUT_DONE_INT_ST_S 6 RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) RTC_CNTL_TOUCH_INT_ENA_V 0x1 XCHAL_HAVE_INTERRUPTS 1 va_arg(v,l) __builtin_va_arg(v,l) RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) RTC_CNTL_CPU_STALL_WAIT_S 1 EFUSE_BLK1_DIN2_V 0xFFFFFFFF DPORT_IMMU_TABLE9_S 0 REG_READ(_r) (*(volatile uint32_t *)(_r)) DPORT_APP_MMU_RDATA 0x000001FF EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) DPORT_APP_BT_BB_INT_MAP_S 0 RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) RTC_CNTL_ENB_SCK_XTAL (BIT(26)) XCHAL_HAVE_BBE16_RSQRT 0 DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S)) BIT24 0x01000000 RTC_CNTL_WDT_STG1 0x00000007 DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) LOG_COLOR_GREEN "32" RTC_CNTL_FAST_CLK_RTC_SEL_S 29 RTC_CNTL_WDT_STG2_S 22 DPORT_APP_RWBLE_NMI_MAP 0x0000001F TIMG_LACT_ALARM_LO 0xFFFFFFFF image_header SPI_FLASH_HPM_M (BIT(19)) DPORT_DMMU_TABLE14_S 0 SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C) FUNC_GPIO23_GPIO23_0 0 DPORT_APP_MPU_IA_INT_MAP_S 0 DPORT_APP_SLC1_INTR_MAP_S 0 TIMG_LACT_INT_RAW (BIT(3)) SPI_FLASH_WREN_V 0x1 DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) DR_REG_FE_BASE 0x3ff46000 DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) SPI_WAIT_FLASH_IDLE_EN (BIT(12)) RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) _REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf) EFUSE_READ_DONE_INT_ST_V 0x1 RTC_CNTL_SDIO_ACT_DNUM 0x000003FF RTC_CNTL_SCRATCH3 0xFFFFFFFF SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) DPORT_PRO_TX_END_M (BIT(20)) SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) RTC_CNTL_ENB_SCK_XTAL_S 26 DPORT_APP_CAN_INT_MAP_V 0x1F DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) __lock_init(lock) (_CAST_VOID 0) DPORT_PRO_SPI_INTR_0_MAP 0x0000001F XCHAL_RESET_VECTOR_VADDR 0x40000400 DPORT_PRO_BT_BB_NMI_MAP 0x0000001F RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) TIMG_T0_ALARM_HI_V 0xFFFFFFFF DPORT_SHROM_MPU_TABLE6_V 0x3 SPI_SLV_RD_BUF_DONE_M (BIT(0)) SPI_SLV_WR_ST 0xFFFFFFFF ETS_TG0_LACT_LEVEL_INTR_SOURCE 17 RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 __GCC_ATOMIC_LLONG_LOCK_FREE 1 DPORT_RMT_CLK_EN (BIT(9)) XCHAL_INT10_LEVEL 1 DPORT_IMMU_TABLE0_S 0 SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 DPORT_APP_RSA_INTR_MAP_V 0x1F SHRT_MIN (-SHRT_MAX - 1) __LDBL_MIN_10_EXP__ (-307) DPORT_PRO_CACHE_FLUSH_DONE_S 5 RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0) TIMG_T1_INT_CLR (BIT(1)) DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 DPORT_PRO_RWBT_NMI_MAP_V 0x1F ETS_UHCI1_INTR_SOURCE 13 RTC_CNTL_FORCE_NOISO (BIT(5)) DR_REG_SPI0_BASE 0x3ff43000 RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) XCHAL_EXTINT2_NUM 2 DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 DPORT_APP_EMAC_INT_MAP_V 0x1F RTC_CNTL_SCRATCH6_V 0xFFFFFFFF DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F SPI_INDSCR_BURST_EN_M (BIT(11)) EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) __FLT_MIN__ 1.1754943508222875e-38F SPI_SRAM_DIO_M (BIT(0)) __TIMG_REG_H__ RTC_CNTL_CPU_STALL_EN (BIT(0)) MESR_ERRENAB 0x00000100 DPORT_APP_WDG_INT_MAP_V 0x1F EFUSE_BLK1_DIN7_S 0 RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C) DPORT_APP_ROM_MPU_AD (BIT(2)) TIMG_WDT_CLK_PRESCALE_V 0xFFFF SPI_MASTER_CS_POL_S 6 __size_t __DEC64_EPSILON__ 1E-15DD XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL SPI_FLASH_BE_M (BIT(23)) DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) SPI_CK_IDLE_EDGE (BIT(29)) EFUSE_SDIO_FORCE_M (BIT(16)) DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) _VOID void DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 __XTENSA__ 1 TIMG_CLK_EN (BIT(31)) SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F SPI_CACHE_SRAM_USR_WCMD_V 0x1 ETS_UART2_INTR_SOURCE 36 EFUSE_BLK3_DOUT1 0xFFFFFFFF DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) XCHAL_MAX_INSTRUCTION_SIZE 3 RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) DPORT_APP_CPU_RECORD_DISABLE_S 4 DPORT_SHROM_MPU_TABLE9_S 0 strnicmp strncasecmp DPORT_PRO_CACHE_MASK_IRAM0_S 0 RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) SPI_CACHE_USR_CMD_4BYTE (BIT(1)) XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_DMMU_TABLE13 0x0000007F DPORT_PRO_UHCI0_INTR_MAP 0x0000001F SPI_BUF11_S 0 DEBUGCAUSE_DEBUGINT_SHIFT 5 SPI_USR_MOSI_M (BIT(27)) SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) RTC_CNTL_SAR_INT_ST_V 0x1 RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) DPORT_APP_EFUSE_INT_MAP_V 0x1F DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK) XCHAL_PREFETCH_CASTOUT_LINES 0 EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) TIMG_WDT_FLASHBOOT_MOD_EN_S 14 DPORT_APP_PWM2_INTR_MAP_S 0 DPORT_MPU_IA_INT_EN_V 0x1FFFF _PARAMS(paramlist) paramlist DPORT_PRO_DRAM_HL (BIT(16)) TIMG_WDT_INT_CLR_M (BIT(2)) SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 UINT_LEAST16_MAX 65535 FUNC_SD_CLK_SPICLK 1 EFUSE_RD_SDIO_DREFL_V 0x3 DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) SPI_OUT_TOTAL_EOF_INT_CLR_S 8 DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) SPI_FLASH_SE_M (BIT(24)) DEBUGCAUSE_BREAK_MASK 0x08 DPORT_APP_CACHE_IA_INT_MAP_V 0x1F _REENT_MP_RESULT_K(ptr) ((ptr)->_result_k) RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF TIMG_T0_UPDATE_S 0 ETS_TG0_T0_EDGE_INTR_SOURCE 58 DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 DPORT_LINK_DEVICE_SEL 0x000000FF TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF DPORT_SHARE_ROM_PD_S 2 RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 EFUSE_RD_EFUSE_RD_DIS_S 16 DPORT_APP_CACHE_STATE_S 7 DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) EFUSE_BLK1_DOUT5_S 0 DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F FUNC_GPIO2_GPIO2 2 MESR_LCE_SHIFT ? SPI_BUF0_S 0 FUNC_MTDO_EMAC_RXD3 5 SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) RTC_CNTL_CPU_STALL_WAIT_V 0x1F DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) DPORT_APP_CACHE_IA_S 1 RTC_CNTL_SLP_WAKEUP (BIT(29)) RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) SPI_USR_MISO_HIGHPART_V 0x1 SPI0_R_QIO_ADDR_BITSLEN 31 DPORT_APP_ROM_PD_M (BIT(1)) TIMG_T1_INT_ST_V 0x1 RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 TIMG_T0_ALARM_EN_S 10 DPORT_AHB_ACCESS_DENY_S 8 EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) __LOCK_INIT(class,lock) static int lock = 0; DR_REG_PCNT_BASE 0x3ff57000 DPORT_WIFI_CLK_EN_S 0 DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F _VOLATILE volatile APP_CPU_NUM (1) RTC_CNTL_BB_I2C_FORCE_PU_S 7 SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) DPORT_PRO_CACHE_MODE_S 2 EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 SPI_HOLD_TIME 0x0000000F EFUSE_CONSOLE_DEBUG_DISABLE_S 2 EFUSE_RD_DISABLE_JTAG_S 6 SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) SPI_USR_MISO_DBITLEN_V 0xFFFFFF RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) XCHAL_DATARAM0_VADDR 0x3FF80000 EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) DPORT_APP_RX_END_S 23 DPORT_APP_TX_END_M (BIT(20)) RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074) DPORT_PRO_BB_INT_MAP 0x0000001F EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) DPORT_WDG_RST (BIT(3)) EFUSE_DEBUG_S 0 DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) DPORT_PRO_CACHE_MODE (BIT(2)) __ORDER_BIG_ENDIAN__ 4321 TIMG_LACT_AUTORELOAD_S 29 RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 TIMG_T0_ALARM_HI 0xFFFFFFFF EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) __NEWLIB_H__ 1 _REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult) DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 RTC_CNTL_TOUCH_INT_CLR_V 0x1 RTC_CNTL_SW_SYS_RST (BIT(31)) DPORT_DMMU_TABLE5 0x0000007F DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F SPI_SLV_WR_STA_DONE (BIT(3)) RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) __DEC_EVAL_METHOD__ 2 SPI_OUT_EOF_INT_CLR_V 0x1 RTC_MEM_PID_CONF_V (0xff) TG0WDT_SYS_RESET DPORT_SHARE_ROM_MPU_ENA_V 0x1 DPORT_SLAVE_SPI_MASK_APP (BIT(4)) EFUSE_KEY_STATUS_S 10 RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 RTC_CNTL_SW_SYS_RST_S 31 DPORT_APP_SPI_INTR_2_MAP 0x0000001F RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) EFUSE_CHIP_VER_RESERVE_V 0xFF SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) FUNC_GPIO0_GPIO0_0 0 EFUSE_BLK2_DOUT0 0xFFFFFFFF INT64_MAX 9223372036854775807LL DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) RTC_CNTL_FASTMEM_PD_EN_V 0x1 DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) SPI_BUF8 0xFFFFFFFF XCHAL_INT14_EXTNUM 11 SPI_SLV_WRBUF_DBITLEN_S 0 DPORT_CPUPERIOD_SEL_V 0x3 DPORT_APP_BB_INT_MAP 0x0000001F __FP_FAST_FMAF 1 RTC_CNTL_SDIO_FORCE_M (BIT(22)) DPORT_APP_TRACEMEM_ENA (BIT(0)) SPI_FLASH_CE (BIT(22)) DPORT_I2C_EXT1_CLK_EN (BIT(18)) DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) DPORT_APP_CMMU_PD_V 0x1 DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F EFUSE_BLK2_DOUT1_S 0 RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) XCHAL_HAVE_CCOUNT 1 SPI_DMA_CONTINUE (BIT(16)) TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 TIMER_CLK_FREQ (80000000>>4) RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 TIMG_LACT_INT_ST_S 3 DPORT_PRO_SLC1_INTR_MAP 0x0000001F DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) DPORT_APP_CACHE_IA_V 0x3F RTC_CNTL_WDT_INT_CLR_V 0x1 __LDBL_HAS_QUIET_NAN__ 1 DPORT_LSLP_MEM_PD_MASK_S 0 DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) _REENT_MP_FREELIST(ptr) ((ptr)->_freelist) DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF DPORT_APP_SLC0_INTR_MAP 0x0000001F RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 DPORT_CACHE_MUX_MODE_V 0x3 DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF DPORT_APP_DRAM_SPLIT (BIT(11)) RTC_CNTL_CNTL_DATE 0x0FFFFFFF __INT_FAST8_MAX__ 2147483647 XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 DPORT_LPCLK_SEL_8M_S 25 EXCCAUSE_ITLB_MISS 16 DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0) EFUSE_PGM_DONE_INT_RAW (BIT(1)) __LDBL_MAX_EXP__ 1024 DPORT_PRO_MMU_IA_INT_MAP 0x0000001F DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK) DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 EFUSE_DAC_CLK_DIV_V 0xFF spi_mode RTC_CNTL_PLL_I2C_PU (BIT(31)) RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) SPI_OUT_DATA_BURST_EN_M (BIT(12)) __FLT_RADIX__ 2 BIT31 0x80000000 UINTMAX_MAX __UINTMAX_MAX__ RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) SPI_FLASH_SE_V 0x1 SPI_IN_DONE_INT_ENA_M (BIT(3)) XCHAL_NUM_EXTINTERRUPTS 26 DPORT_SHROM_MPU_TABLE19 0x00000003 PIN_SET_DRV(PIN_NAME,drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); DPORT_SPI_CLK_EN (BIT(16)) uint8_t DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) SPI_CS_HOLD_S 4 XCHAL_HAVE_ABS 1 EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) SPI_USR_MISO_V 0x1 RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) DPORT_APP_CACHE_MMU_IA_S 0 DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 EFUSE_BLK3_DIN1_V 0xFFFFFFFF DPORT_APP_CACHE_LOCK_0_EN_S 6 DPORT_IMMU_TABLE9_V 0x7F DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F TIMG_WDT_INT_ENA_S 2 SPI_OUT_EOF_INT_ENA (BIT(7)) DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) CONFIG_ESPTOOLPY_BAUD_115200B 1 RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) PART_SUBTYPE_DATA_WIFI 0x02 DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) SPI_SLV_RDBUF_DUMMY_EN_V 0x1 DPORT_APP_CACHE_STATE_V 0xFFF __attribute_malloc__ DPORT_PERIP_RST_V 0xFFFFFFFF TIMG_WDT_EN_S 31 RTCWDT_RTC_RESET EFUSE_RD_EFUSE_RD_DIS_V 0xF SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 _REENT_SIGNAL_SIZE 24 ___int_size_t_h BIT16 0x00010000 DPORT_APP_BOOT_REMAP_M (BIT(0)) crc32_le __ATTRIBUTE_IMPURE_PTR__ SPI_WAIT_FLASH_IDLE_EN_S 12 RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8) RTC_CNTL_SCK_DCAP_FORCE_V 0x1 RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) TIMG_T1_LOAD_LO 0xFFFFFFFF DPORT_SHROM_MPU_TABLE8_S 0 DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) SPI_MOSI_DELAY_MODE_S 21 RTC_CNTL_PLLA_FORCE_PD_S 23 DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) DPORT_SHARE_ROM_PD_V 0x3F WINT_MIN __WINT_MIN__ FUNC_GPIO36_GPIO36_0 0 RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) DPORT_PRO_CACHE_MASK_DROM0_V 0x1 DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) DPORT_WIFI_RST_S 0 EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) XCHAL_HAVE_SSP16_VITERBI 0 DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) SPI_FCS_CRC_EN_S 10 TIMG_WDT_EDGE_INT_EN (BIT(22)) DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) SPI_CK_OUT_EDGE_S 7 DPORT_APP_RSA_INTR_MAP_S 0 DPORT_IMMU_TABLE13_V 0x7F SPI_IN_ERR_EOF_INT_ENA_V 0x1 PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) _RAND48_SEED_0 (0x330e) EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 SPI_USR_ADDR_HOLD_M (BIT(21)) DPORT_SRAM_PD_1_S 0 DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 DPORT_PRO_SLAVE_REQ_M (BIT(13)) DPORT_PRO_PWM0_INTR_MAP_S 0 DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) SPI_WR_BIT_ORDER_S 26 SPI_IN_SUC_EOF_INT_RAW_S 5 RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) RTC_CNTL_ENT_RTC (BIT(29)) DPORT_PRO_RX_END (BIT(23)) SPI_OUTLINK_RESTART_M (BIT(30)) EFUSE_CLK_EN (BIT(16)) UINT16_C(x) x DPORT_APP_SPI_INTR_3_MAP_V 0x1F SPI_FREAD_QUAD_S 20 RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F EFUSE_BLK2_DIN0_V 0xFFFFFFFF RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) RTC_CNTL_TOUCH_INT_ENA (BIT(6)) EFUSE_RD_SDIO_FORCE_V 0x1 XCHAL_INT13_LEVEL 1 DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070) SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) __OPTIMIZE__ 1 DPORT_APP_ROM_IA_M (BIT(3)) DPORT_PERI_RST_EN_S 0 DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) _READ_WRITE_RETURN_TYPE int RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) XCHAL_HAVE_DEBUG 1 TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) XCHAL_HAVE_PDX4 0 SPI_SRAM_RSTIO (BIT(4)) DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) EFUSE_RD_DISABLE_JTAG (BIT(6)) SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 EFUSE_RD_DISABLE_JTAG_V 0x1 RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) EFUSE_CHIP_VER_RESERVE 0x000000FF RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) XCHAL_INSTRAM1_ECC_PARITY 0 DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) EFUSE_PGM_DONE_INT_ENA (BIT(1)) EFUSE_SPI_PAD_CONFIG_Q_V 0x1F DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) RTC_CNTL_SLP_REJECT_S 30 EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) SPI_FLASH_PER_S 16 RTC_CNTL_TIME_VALID_INT_ENA_S 4 RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) TIMG_LACT_INCREASE_M (BIT(30)) RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 DBREAKC_STOREBREAK_SHIFT 31 _RAND48_MULT_0 (0xe66d) DPORT_PRO_RWBLE_NMI_MAP 0x0000001F EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) DPORT_PRO_I2S1_INT_MAP 0x0000001F __DBL_MAX__ ((double)1.7976931348623157e+308L) DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F EFUSE_READ_CMD (BIT(0)) DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F XCHAL_HAVE_MEM_ECC_PARITY 0 DPORT_APP_SPI_INTR_1_MAP_S 0 cpu_configure_region_protection __int_fast32_t_defined 1 SPI_DMA_TX_EN_V 0x1 XCHAL_HAVE_IMEM_LOADSTORE 1 SCHAR_MAX RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) APB_CLK_FREQ 80*1000000 DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) DPORT_SHROM_MPU_TABLE14_V 0x3 RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) SPI_OUTLINK_STOP_S 28 ESP_LOGE(tag,format,...) ESP_EARLY_LOGE(tag, format, ##__VA_ARGS__) DPORT_SHROM_MPU_TABLE16_S 0 RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 TIMG_RTC_CALI_RDY_V 0x1 FUNC_GPIO17_HS1_DATA5 3 SPI_OUT_EOF_INT_ST_V 0x1 RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) RTC_CNTL_DBIAS_WAK_V 0x7 DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) DPORT_PRO_CACHE_MODE_M (BIT(2)) XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL SPI1_R_SIO_ADDR_BITSLEN 23 EFUSE_DEBUG 0xFFFFFFFF DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF XCHAL_HW_CONFIGID1 0x1CC5FE96 CONFIG_ESPTOOLPY_PORT "/dev/ttyUSB0" DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) RTC_CNTL_SAR_INT_ST_M (BIT(5)) EFUSE_SDIO_TIEH_M (BIT(15)) SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44) RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) EFUSE_BLK1_DIN0 0xFFFFFFFF DPORT_APPCPU_RUNSTALL_M (BIT(0)) SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 DPORT_SHROM_MPU_TABLE1 0x00000003 DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 XCHAL_INTTYPE_MASK_TIMER 0x00018040 RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF ETS_SPI2_DMA_INTR_SOURCE 53 XCHAL_INT28_EXTNUM 23 TIMG_LACT_LAC_EN_S 9 MEMCTL_L0IBUF_EN 0x01 EFUSE_BLK1_DIN1_S 0 DPORT_FE_ACCESS_GRANT_CONFIG_S 0 _bss_end EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) EFUSE_BLK2_DOUT7_V 0xFFFFFFFF __SIZEOF_SHORT__ 2 SPI_FASTRD_MODE_M (BIT(13)) PIN_FUNC_SELECT(PIN_NAME,FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) RTC_CNTL_WIFI_FORCE_PU_S 18 RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 ETS_WMAC_INUM 0 DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F SPI_USR_DOUT_HOLD_S 18 DPORT_PERI_RST_EN 0xFFFFFFFF XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR BIT12 0x00001000 RTC_CNTL_SCRATCH3_V 0xFFFFFFFF RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) DPORT_PRO_CTAG_RAM_RDATA_S 0 TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S)) RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) TIMG_T1_LOAD 0xFFFFFFFF DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) DPORT_PRO_RX_END_S 23 RTC_CNTL_DBG_ATTEN_S 24 SPI_FLASH_RES_M (BIT(20)) TIMG_T0_EN (BIT(31)) TIMG_T1_ALARM_LO_V 0xFFFFFFFF _WINT_T DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF RTC_CNTL_TOUCH_INT_CLR (BIT(6)) RTC_CNTL_PWC_FORCE_PD_S 18 DPORT_PRO_SLAVE_WDATA_V_V 0x1 TIMG_T0_INT_RAW_S 0 TIMG_RTC_CALI_START_S 31 DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F XCHAL_INTLEVEL4_MASK 0x53000000 RTC_CNTL_WDT_INT_CLR (BIT(3)) __DECIMAL_DIG__ 17 RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) EFUSE_DISABLE_DL_CACHE_S 9 EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) DPORT_DMMU_TABLE2_V 0x7F SPI_SLV_RDBUF_CMD_VALUE_V 0xFF XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED TIMG_LACT_LEVEL_INT_EN_M (BIT(11)) PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) SPI_SPEED_20M SPI_IN_SUC_EOF_INT_RAW (BIT(5)) EFUSE_PGM_DONE_INT_CLR (BIT(1)) DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88) RTC_CNTL_PWC_FORCE_PD_V 0x1 DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) SPI_INLINK_STOP (BIT(28)) RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) DPORT_APP_ROM_MPU_ENA_M (BIT(2)) TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S)) RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) DPORT_SLAVE_SPI_MASK_APP_S 4 DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) RTC_CNTL_TIME_LO 0xFFFFFFFF XCHAL_EXTINT11_NUM 14 DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) XCHAL_INT9_EXTNUM 7 DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) ETS_TG1_T1_EDGE_INTR_SOURCE 63 SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF DPORT_PRO_BT_BB_INT_MAP_S 0 _LIBC_LIMITS_H_ 1 TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080) DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F SPI_SRAM_ADDR_BITLEN_S 22 DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) UINT_FAST64_MAX UINT_LEAST64_MAX TIMG_T0_INT_ST_V 0x1 EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 DPORT_APPCPU_RUNSTALL (BIT(0)) DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F __ptr_t void * SPI_SRAM_DIO_S 0 SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF ETS_CAN_INTR_SOURCE 45 EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) DPORT_SHROM_MPU_TABLE13_V 0x3 DPORT_PBUS_MEM_FORCE_PD_V 0x1 EXCCAUSE_LOADSTOREERROR 3 EFUSE_BLK3_DOUT2_V 0xFFFFFFFF SPI_DMA_INLINK_DSCR_S 0 EXCCAUSE_CP2_DISABLED 34 RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) ETS_UNCACHED_ADDR(addr) (addr) RTC_CNTL_SW_STALL_PROCPU_C0_S 2 EFUSE_SDIO_DREFH_V 0x3 SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) SPI_MASTER_CK_SEL_V 0x1F SPI_SLV_RD_STA_DONE_M (BIT(2)) RTC_CNTL_PLLA_FORCE_PU_S 24 SPI_SRAM_BYTES_LEN 0x000000FF RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) TIMG_LACT_ALARM_HI_V 0xFFFFFFFF DPORT_APP_CAN_INT_MAP 0x0000001F RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) RTC_CNTL_SLOWMEM_PD_EN_V 0x1 RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) DPORT_DPORT_DATE_VERSION 0x1605190 DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) DPORT_APP_RWBT_NMI_MAP_S 0 LOG_COLOR_BLUE "34" RTC_CNTL_TIME_UPDATE_V 0x1 TIMG_RTC_CALI_CLK_SEL_V 0x3 SPI_BUF7_S 0 XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 __INT_FAST16_MAX__ 2147483647 RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) RTC_MEM_CRC_FINISH_V 0x1 DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 SPI_SLV_WR_ADDR_BITLEN 0x0000003F RTC_CNTL_XTL_BUF_WAIT 0x000003FF EFUSE_BLK1_DOUT3_S 0 SPI_SRAM_QIO_M (BIT(1)) DPORT_PERIP_RST 0xFFFFFFFF XCHAL_CP_MAXCFG 8 DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F DPORT_PRO_BB_INT_MAP_S 0 TIMG_T1_LOAD_HI_V 0xFFFFFFFF RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 SPI_SLV_LAST_COMMAND_S 17 RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) INTMAX_MAX __INTMAX_MAX__ PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80) DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) ETS_CACHE_IA_INTR_SOURCE 68 SPI_CACHE_SRAM_USR_RCMD_V 0x1 TIMG_T1_HI 0xFFFFFFFF RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) DPORT_PRO_INTR_STATUS_2_S 0 UART_CLK_FREQ APB_CLK_FREQ ESP_LOG_DEBUG SPI_BUF15 0xFFFFFFFF DPORT_PRO_MAC_NMI_MAP 0x0000001F EFUSE_CODING_SCHEME_S 0 RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) DPORT_PRO_CACHE_MMU_IA_V 0x1 EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) DPORT_PRO_I2S1_INT_MAP_V 0x1F SPI_SIZE_2MB BIT14 0x00004000 irom_load_addr DPORT_APP_DRAM1ADDR0_IA_S 0 DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) ETS_MMU_IA_INTR_SOURCE 66 DPORT_IMMU_TABLE6 0x0000007F DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF DPORT_WIFI_BB_CFG_2_S 0 DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF __UINTMAX_TYPE__ long long unsigned int EFUSE_CLK_SEL1_S 8 SPI_DATE_S 0 XCHAL_XLMI0_ECC_PARITY 0 RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) RTC_CNTL_TXRF_I2C_PU (BIT(27)) DPORT_APP_CACHE_TAG_PD_V 0x1 SPI_FWRITE_DIO_S 14 DPORT_MPU_IA_INT_EN_S 0 TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) RTC_CNTL_ADC2_HOLD_FORCE_S 1 RTC_CNTL_FASTMEM_FOLW_CPU_S 6 RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 EXCCAUSE_SPECULATION 7 RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 DPORT_APP_ROM_PD (BIT(1)) _REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed) UINT8_MAX 255 DPORT_APP_CTAG_RAM_RDATA_S 0 TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) DPORT_DMMU_TABLE6_S 0 RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 SPI_IN_ERR_EOF_INT_CLR_V 0x1 RTC_CNTL_SLP_REJECT_V 0x1 SPI_SLV_STATUS_BITLEN_V 0x1F TIMG_LACT_INCREASE (BIT(30)) SPI_FREAD_DIO_S 23 SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) RTC_CNTL_SCRATCH5 0xFFFFFFFF DPORT_ROM_MPU_TABLE0_V 0x3 DPORT_APP_RWBLE_IRQ_MAP_V 0x1F pages_to_protect XCHAL_HAVE_DENSITY 1 DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 TIMG_T0_LEVEL_INT_EN_M (BIT(11)) EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF DPORT_I2C_EXT0_RST (BIT(7)) DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) SPI_AHBM_RST_V 0x1 XCHAL_INT20_EXTNUM 15 DPORT_DMMU_TABLE0_V 0x7F SPI_OUT_DONE_INT_ENA_V 0x1 SPI_OUT_RST_V 0x1 SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 SPI_OUT_AUTO_WRBACK_M (BIT(8)) DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F TIMG_T0_UPDATE 0xFFFFFFFF ETS_WIFI_BB_INTR_SOURCE 2 DPORT_MMU_IA_INT_EN 0x00FFFFFF EFUSE_READ_DONE_INT_CLR_S 0 EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) FUNC_GPIO19_EMAC_TXD0 5 SPI_FREAD_DUAL (BIT(14)) RTC_CNTL_BROWN_OUT_INT_RAW_S 7 SPI_WR_BYTE_ORDER_S 11 DPORT_DMMU_TABLE12_V 0x7F RTC_CNTL_WDT_STG3 0x00000007 DPORT_SHROM_MPU_TABLE3_S 0 SPI_CS0_DIS (BIT(0)) SPI_SPEED_26M EFUSE_RD_CHIP_VER_RESERVE_S 9 SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) RTC_MEM_PID_CONF_M (0xff) EFUSE_FLASH_CRYPT_CNT_S 20 DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) EFUSE_SPI_PAD_CONFIG_D_S 10 RTC_CNTL_WDT_STG2 0x00000007 RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) SPI_USR_MISO_HIGHPART (BIT(24)) RTC_CNTL_ROM0_FORCE_PU_S 6 EFUSE_ABS_DONE_0_S 4 SPI_DMA_TX_EN_M (BIT(1)) RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF DPORT_SHROM_MPU_TABLE10 0x00000003 SPI_OUT_DATA_BURST_EN_V 0x1 RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) DPORT_ACCESS_CHECK_PRO (BIT(0)) DPORT_APP_MAC_INTR_MAP_V 0x1F RTC_CNTL_SLOWMEM_FORCE_PD_S 15 DPORT_APP_IROM0ADDR_IA 0x000FFFFF TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) TIMG_T1_INT_ST_S 1 DPORT_CPU_INTR_FROM_CPU_3_S 0 EFUSE_BLK3_DOUT3 0xFFFFFFFF XCHAL_EXTINT9_NUM 12 DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) XCHAL_INT16_LEVEL 5 TIMG_T0_LO 0xFFFFFFFF FUNC_GPIO0_GPIO0 2 SPI_SETUP_TIME_S 0 _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err)) DPORT_PRO_BT_MAC_INT_MAP_S 0 SPI_FLASH_WRDI (BIT(29)) TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) PIN_FUNC_GPIO 2 DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) XCHAL_HAVE_TLBS 1 EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S)) XCHAL_HAVE_OCD_LS32DDR 1 DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) DPORT_PRO_BT_MAC_INT_MAP_V 0x1F __CHAR_BIT__ 8 CONFIG_TOOLPREFIX "xtensa-esp32-elf-" DPORT_INTERNAL_SRAM_MMU_AD_S 10 DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF __STDC_UTF_32__ 1 DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F section_index DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 DPORT_APP_CACHE_MMU_IA_M (BIT(0)) SPI_FLASH_HPM (BIT(19)) DPORT_APP_LEDC_INT_MAP 0x0000001F XCHAL_ICACHE_LINESIZE 4 DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL RTC_CNTL_CK8M_FORCE_PU_S 26 RTC_CNTL_CNTL_DATE_V 0xFFFFFFF VALUE_SET_FIELD2(_r,_f,_v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f ##_S)))) RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 DPORT_ACCESS_CHECK_APP_M (BIT(8)) RTC_CNTL_SCRATCH6_S 0 TIMG_T0_EN_S 31 DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 XCHAL_HAVE_FP_SQRT 1 SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) __UINT16_MAX__ 65535 DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) TIMG_T1_LEVEL_INT_EN_V 0x1 RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) XCHAL_HAVE_NSA 1 DPORT_PERIP_CLK_EN_S 0 RTC_CNTL_DREFL_SDIO_V 0x3 TIMG_LACT_UPDATE_S 0 DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F INT_LEAST16_MAX 32767 EFUSE_PGM_DONE_INT_ST (BIT(1)) DPORT_PRO_IRAM1ADDR_IA_S 0 DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) DPORT_PRO_SLAVE_WDATA_V_S 22 DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F DPORT_APP_CMMU_PD_M (BIT(12)) DPORT_ROM_MPU_TABLE2_S 0 EFUSE_RD_DISABLE_JTAG_M (BIT(6)) RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF RTC_CNTL_WDT_INT_ENA_S 3 RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) FUNC_SD_DATA0_U2RTS 4 DPORT_AHB_ACCESS_GRANT_1_S 0 RTC_CNTL_DIG_CLK8M_EN_V 0x1 EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S)) RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) EFUSE_RD_SDIO_TIEH_S 15 EFUSE_PGM_DONE_INT_ENA_V 0x1 SPI_SLV_WRBUF_DUMMY_EN_S 1 XCHAL_DATARAM0_SIZE 524288 EFUSE_CHIP_VER_32PAD_M (BIT(2)) DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) DPORT_SPI1_DMA_CHAN_SEL_V 0x3 FUNC_GPIO26_GPIO26_0 0 ota_select_valid RTC_CNTL_SOC_CLK_SEL_S 27 SPI_DMA_RX_STOP_V 0x1 DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) ETS_SPI3_INTR_SOURCE 31 XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL __LDBL_MIN__ 2.2250738585072014e-308L RTC_MEM_PID_CONF (0xff) TIMG_T1_LEVEL_INT_EN_S 11 SPI_SRAM_ADDR_BITLEN 0x0000003F SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF SPI_FASTRD_MODE (BIT(13)) DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) SPI_CACHE_REQ_EN (BIT(0)) EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) DPORT_PRO_PCNT_INTR_MAP_V 0x1F RTC_CNTL_CPUSEL_CONF_M (BIT(29)) DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F XCHAL_HAVE_DFP 0 TIMG_LACT_LO_S 0 DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) XCHAL_HW_VERSION_NAME "LX6.0.3" DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) TIMG_T1_INT_CLR_M (BIT(1)) DPORT_PRO_IROM0ADDR_IA 0x000FFFFF __FLT_MIN_10_EXP__ (-37) DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_APP_BT_MAC_INT_MAP_S 0 RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) TIMG_RTC_CALI_VALUE 0x01FFFFFF DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) DPORT_AHB_LITE_MASK_PRODPORT_S 9 DPORT_RECORD_PRO_PID_S 0 EFUSE_BLK3_DIN4_S 0 DPORT_SLAVE_REQ_M (BIT(15)) RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) DPORT_DMMU_TABLE7 0x0000007F DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F DPORT_APP_SLAVE_REQ (BIT(13)) FUNC_GPIO4_GPIO4_0 0 DPORT_IMMU_TABLE0_V 0x7F TIMG_T0_INT_ENA_M (BIT(0)) EFUSE_PGM_DONE_INT_ST_V 0x1 RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) DPORT_PRO_UART_INTR_MAP_V 0x1F DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_BB_INT_MAP_V 0x1F RTC_CNTL_CK8M_DIV_S 4 SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) XCHAL_EXTINT0_NUM 0 RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 XCHAL_INTTYPE_MASK_NMI 0x00004000 RTC_CNTL_PVTMON_PU_V 0x1 DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) SPI_CS_KEEP_ACTIVE_V 0x1 TIMG_T0_HI 0xFFFFFFFF SPI_USR_PREP_HOLD_S 23 PS_UM_MASK 0x00000020 DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) RTC_CNTL_SDIO_FORCE_S 22 RTC_CNTL_TIME_VALID_M (BIT(30)) FUNC_GPIO0_EMAC_TX_CLK 5 RTC_CNTL_EXT_WAKEUP1_SEL_S 0 DEBUGCAUSE_BREAKN_MASK 0x10 DPORT_WIFI_BB_CFG_2 0xFFFFFFFF SPI_USR_MOSI (BIT(27)) XCHAL_INTLEVEL3_VECOFS 0x000001C0 SPI_FREAD_QUAD_M (BIT(20)) SPI_OUT_EOF_INT_RAW (BIT(7)) DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) SPI_USR_DUMMY_HOLD_S 20 DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) XCHAL_DATAROM0_SIZE 4194304 ETS_PCNT_INTR_SOURCE 48 SPI_USR_SRAM_QIO_V 0x1 _GCC_LIMITS_H_ RTC_CNTL_SDIO_REJECT_EN (BIT(25)) DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) _REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state) __UINT_FAST16_TYPE__ unsigned int DPORT_APP_I2C_EXT0_INTR_MAP_S 0 DPORT_PRO_SPI1_DMA_INT_MAP_S 0 DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) va_end(v) __builtin_va_end(v) RTC_CNTL_SW_APPCPU_RST_S 4 DPORT_WIFI_BB_CFG_S 0 PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC(1) EFUSE_BLK2_DOUT4_V 0xFFFFFFFF SDIO_RESET DPORT_APP_RWBLE_IRQ_MAP_S 0 EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) DPORT_APP_CMMU_FORCE_ON (BIT(11)) DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_DBIAS_SLP_S 22 XCHAL_INT19_EXTNUM 14 DPORT_SHROM_MPU_TABLE4_V 0x3 SPI_OUT_EOF_INT_ENA_M (BIT(7)) DPORT_SHROM_MPU_TABLE23_V 0x3 RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 XCHAL_INTLEVEL7_NUM 14 SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) DPORT_CPU_INTR_FROM_CPU_1_V 0x1 DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F SPI_OUT_DONE_INT_CLR_V 0x1 TIMG_LACT_LOAD_LO 0xFFFFFFFF SPI_FLASH_DP (BIT(21)) RTC_CNTL_DG_PAD_AUTOHOLD_S 9 EXCCAUSE_LEVEL1INTERRUPT 4 RTC_CNTL_CK8M_DIV_SEL_V 0x7 DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 DPORT_DMMU_TABLE15 0x0000007F __GCC_ATOMIC_POINTER_LOCK_FREE 2 PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) FUNC_SD_DATA1_SPID 1 SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120) RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8) TIMG_T1_UPDATE_S 0 SPI_USR_SRAM_QIO (BIT(2)) SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_LEDC_INT_MAP 0x0000001F SPI_SRAM_RSTIO_M (BIT(4)) DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F RTC_CNTL_DIG_XTAL32K_EN_V 0x1 FUNC_MTDI_HSPIQ 1 RTC_MEM_CRC_ADDR_V (0x7ff) DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF EFUSE_BLK2_DOUT2 0xFFFFFFFF DPORT_RECORD_PRO_PDEBUGPC_S 0 PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS(1) DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) EXCCAUSE_SYSCALL 1 XCHAL_DCACHE_LINESIZE 4 RTC_CNTL_SLEEP_EN_S 31 TIMG_LACT_CPST_EN_V 0x1 NULL ((void *)0) DPORT_PRO_ROM_PD_S 0 SPI_CACHE_USR_CMD_4BYTE_V 0x1 RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) PERIPHS_SPI_FLASH_CMD SPI_CMD(1) DPORT_SHROM_MPU_TABLE3_V 0x3 DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F DPORT_PRO_DRAM_SPLIT_M (BIT(11)) __need_wint_t DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) XCHAL_HW_MAX_VERSION 260003 FUNC_MTDI_HS2_DATA2 3 DPORT_PRO_DRAM_SPLIT_V 0x1 XCHAL_NUM_WRITEBUFFER_ENTRIES 4 DR_REG_UART2_BASE 0x3ff6E000 ___int_least32_t_defined 1 DPORT_APP_SLAVE_WDATA_V_S 22 DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) _ESP32_SOC_H_ XCHAL_XLMI0_VADDR 0x3FF00000 __BEGIN_DECLS __UINT32_C(c) c ## UL DPORT_APP_INTRUSION_RECORD 0x0000000F reserved DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) RTC_CNTL_SCRATCH0_V 0xFFFFFFFF RTC_CNTL_SDIO_PD_EN_S 21 DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) ETS_TG1_LACT_LEVEL_INTR_SOURCE 21 ETS_FROM_CPU_INTR3_SOURCE 27 EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) offset RTC_CNTL_WAKEUP_CAUSE_S 0 TIMG_NTIMERS_DATE 0x0FFFFFFF DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) DPORT_APP_AHB_SPI_REQ_M (BIT(12)) DPORT_UART1_CLK_EN (BIT(5)) DPORT_APP_CACHE_LOCK_2_EN_S 8 DPORT_APP_PWM0_INTR_MAP_V 0x1F DPORT_APP_SLAVE_REQ_M (BIT(13)) RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 SPI_INT_HOLD_ENA_S 0 DPORT_PRO_ROM_MPU_ENA_V 0x1 EFUSE_SPI_PAD_CONFIG_HD 0x0000001F DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) XCHAL_NMI_VECTOR_VADDR 0x400002C0 DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) EFUSE_CLK_SEL1_V 0xFF DPORT_APP_BOOT_REMAP (BIT(0)) TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) FUNC_GPIO4_HSPIHD 1 UINT32_MAX 4294967295UL SPI_MODE_QOUT RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) memset RTC_CNTL_SDIO_PD_EN_M (BIT(21)) RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) GET_PERI_REG_BITS2(reg,mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) SPI_BUF8_V 0xFFFFFFFF DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF __WINT_TYPE__ unsigned int ETS_PWM1_INTR_SOURCE 40 RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) XCHAL_KERNEL_VECTOR_PADDR 0x40000300 DPORT_AHB_ACCESS_DENY_V 0x1 DPORT_PRO_CMMU_PD_S 12 DPORT_PRO_CMMU_FORCE_ON (BIT(11)) SPI_SLV_WR_RD_STA_EN (BIT(28)) EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 TIMG_T1_ALARM_EN (BIT(10)) EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) TIMG_LACT_RTC_ONLY (BIT(7)) TIMG_WDT_STG2_S 25 XCHAL_HW_CONFIGID0 0xC2BCFFFE DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) EFUSE_READ_DONE_INT_RAW_M (BIT(0)) FUNC_SD_DATA0_SPIQ 1 ETS_GPIO_NMI_SOURCE 23 XCHAL_HAVE_S32C1I 1 DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) XCHAL_ICACHE_SIZE 0 DPORT_ROM_MPU_TABLE1 0x00000003 EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) DPORT_PRO_CACHE_MASK_IROM0_V 0x1 DPORT_APP_CACHE_LOCK_3_EN_V 0x1 RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) DR_REG_LEDC_BASE 0x3ff59000 _NULL 0 EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F SPI_DMA_OUT_STATUS_S 0 _GCC_NEXT_LIMITS_H DPORT_IMMU_TABLE15_V 0x7F XCHAL_NUM_IBREAK 2 XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) RTC_CNTL_INTER_RAM1_PD_EN_S 26 DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) CONFIG_ESPTOOLPY_FLASHMODE "dio" SPI_OUT_EOF_MODE_S 9 __lock_release(lock) (_CAST_VOID 0) ETS_EFUSE_INTR_SOURCE 44 DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) UINT_FAST16_MAX (__STDINT_EXP(INT_MAX)*2U+1U) ESP_LOG_VERBOSE SPI_TX_CRC_EN_V 0x1 RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 DPORT_SHROM_MPU_TABLE10_S 0 FUNC_SD_DATA1_U2CTS 4 _REENT_ASCTIME_SIZE 26 SPI_DMA_OUTLINK_DSCR_S 0 DPORT_DMMU_TABLE15_S 0 _ANSI_STDARG_H_ XCHAL_ICACHE_WAYS 1 _REENT_MP_P5S(ptr) ((ptr)->_p5s) DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) DPORT_APP_UART_INTR_MAP 0x0000001F SPI_DMA_RX_EN_S 0 DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) SPI_SLV_RDBUF_DBITLEN_S 0 EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) EFUSE_SDIO_TIEH_V 0x1 SPI_DMA_TX_STOP (BIT(15)) DPORT_PWM1_CLK_EN (BIT(20)) DPORT_APP_EFUSE_INT_MAP_S 0 TIMG_LACT_ALARM_EN (BIT(10)) XCHAL_HAVE_ICACHE_TEST 0 FUNC_MTCK_HSPID 1 EFUSE_BLK3_DOUT2 0xFFFFFFFF DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) __CHAR16_TYPE__ short unsigned int DPORT_AHB_LITE_MASK_PRO_V 0x1 EFUSE_BLK1_DOUT1 0xFFFFFFFF XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_SW_PROCPU_RST_V 0x1 DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) FUNC_GPIO39_GPIO39_0 0 DPORT_APP_WDG_INT_MAP 0x0000001F SPI_SLV_RD_BUF_DONE (BIT(0)) RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 _GCC_SIZE_T RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) RTC_CNTL_WDT_STG0_HOLD_S 0 DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) SIG_ATOMIC_MAX __STDINT_EXP(INT_MAX) RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) SPI_USR_MOSI_HIGHPART_V 0x1 DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F SPI_STATUS_S 0 XCHAL_HAVE_CLAMPS 1 XCHAL_HAVE_HIFI4_VFPU 0 DPORT_PRO_DRAM_HL_V 0x1 SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 __SIZEOF_POINTER__ 4 ETS_RWBLE_NMI_SOURCE 9 DPORT_PRO_CACHE_MMU_IA_CLR_S 13 XCHAL_INT2_LEVEL 1 __INTMAX_MAX__ 9223372036854775807LL EFUSE_PGM_DONE_INT_CLR_V 0x1 SPI_TX_CRC_EN_S 11 DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) RTC_CNTL_PLLA_FORCE_PD_V 0x1 SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98) __EXP REG_GET_FIELD(_r,_f) ((REG_READ(_r) >> (_f ##_S)) & (_f)) DPORT_CPU_INTR_FROM_CPU_3_V 0x1 TIMG_T1_DIVIDER_S 13 RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 ETS_PWM3_INTR_SOURCE 42 DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) __UINT8_C(c) c SPI_CLKCNT_N_S 12 SPI_CK_DIS_V 0x1 XCHAL_WINDOW_UF8_VECOFS 0x000000C0 DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_SLEEP_EN_V 0x1 DPORT_DMMU_PAGE_MODE_S 1 SPI_FWRITE_DUAL_V 0x1 DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 XCHAL_HAVE_PRID 1 __UINT_LEAST32_MAX__ 4294967295UL SPI_INDSCR_BURST_EN_V 0x1 LOG_FORMAT(letter,format) LOG_COLOR_ ## letter #letter " (%d) %s: " format LOG_RESET_COLOR "\n" RTC_CNTL_WAIT_TIMER_S 0 DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F EFUSE_ABS_DONE_1_M (BIT(5)) false 0 TIMG_WDT_FEED_S 0 DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) XCHAL_DCACHE_SETWIDTH 0 DPORT_PRO_CACHE_MASK_IRAM1_S 1 SPI_OUT_DONE_INT_CLR_M (BIT(6)) RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) SPI_BUF12_S 0 SPI_SLV_RDBUF_CMD_VALUE_S 0 ETS_TG0_T1_INUM 10 XCHAL_HAVE_MINMAX 1 SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 SPI_T_PP_ENA_S 31 __FLT_HAS_INFINITY__ 1 INT_LEAST32_MAX 2147483647L DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 XCHAL_RESET_VECTOR1_PADDR 0x40000400 EFUSE_DISABLE_DL_DECRYPT_V 0x1 XCHAL_EXTINT13_NUM 18 SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078) DPORT_PRO_PWM2_INTR_MAP_V 0x1F EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F EFUSE_BLK1_DIN2 0xFFFFFFFF RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 SPI_FLASH_DP_S 21 DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) TIMG_LACT_AUTORELOAD_M (BIT(29)) ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 RTC_CNTL_FORCE_ISO_V 0x1 __UINT8_TYPE__ unsigned char DR_REG_PWM_BASE 0x3ff5E000 SPI_DATE 0x0FFFFFFF EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) DPORT_PRO_BT_MAC_INT_MAP 0x0000001F DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) DPORT_UHCI1_RST (BIT(12)) DPORT_PWM1_RST (BIT(20)) RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) EFUSE_BLK1_DOUT6_S 0 PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) SPI_RD_BIT_ORDER_S 25 TIMG_WDT_STG3 0x00000003 SPI_BUF1_S 0 DPORT_APP_CACHE_MASK_IRAM0_V 0x1 DPORT_FAST_CLK_RTC_SEL (BIT(3)) RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) RTC_CNTL_SW_SYS_RST_M (BIT(31)) SPI_IN_LOOP_TEST_V 0x1 DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S)) DPORT_APP_AHB_SPI_REQ_S 12 DPORT_PRO_SPI_INTR_1_MAP_V 0x1F RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 SPI_USR_HOLD_POL_V 0x1 SPI_USR_MISO_HIGHPART_S 24 FUNC_GPIO16_GPIO16_0 0 XCHAL_HAVE_DEBUG_ERI 1 RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) selected_subtype RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) XCHAL_HAVE_DEPBITS 0 SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C) TIMG_WDT_INT_RAW_M (BIT(2)) DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) SPI_CS_KEEP_ACTIVE_S 30 DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F SPI_CK_OUT_HIGH_MODE 0x0000000F SPI_CS_DELAY_NUM 0x0000000F SPI_OUTLINK_ADDR_S 0 DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) RTC_CNTL_REG1P8_READY_V 0x1 RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) RTC_CNTL_X32P_HOLD_FORCE_S 16 RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF DPORT_APP_RX_END (BIT(23)) DPORT_LSLP_MEM_PD_MASK_V 0x1 SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) RTC_CNTL_CPUPERIOD_SEL_V 0x3 XCHAL_HAVE_AXI 0 DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) DPORT_IMMU_TABLE3_S 0 SPI_CS0_DIS_V 0x1 RTC_CNTL_DREFL_SDIO 0x00000003 SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF DPORT_APP_CPU_RECORD_ENABLE_V 0x1 DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 UINT_MAX (INT_MAX * 2U + 1U) PART_TYPE_DATA 0x01 RTC_CNTL_XTL_EXT_CTR_LV_S 30 DPORT_LEDC_CLK_EN (BIT(11)) DPORT_SPI_DMA_CLK_EN (BIT(22)) DPORT_SHARE_ROM_IA_V 0xF SPI_CK_IDLE_EDGE_V 0x1 SPI_FLASH_RDID_M (BIT(28)) TIMG_LACT_LAC_EN (BIT(9)) RTC_CNTL_RFRX_PBUS_PU (BIT(28)) RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F DPORT_DMMU_TABLE0_S 0 EFUSE_RD_DISABLE_SDIO_HOST_S 3 DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) RTC_CNTL_SDIO_FORCE (BIT(22)) SPI_USR_DOUT_HOLD (BIT(18)) DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF true 1 SPI_TRANS_DONE_M (BIT(4)) DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) RTC_CNTL_WDT_STG3_S 19 DPORT_PRO_BT_BB_NMI_MAP_V 0x1F RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F DPORT_APP_BOOT_REMAP_S 0 DPORT_IMMU_TABLE8 0x0000007F SPI_SRAM_DUMMY_CYCLELEN_S 14 TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) SPI_WRSR_2B_V 0x1 RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F EFUSE_BLK2_DIN3_S 0 DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 SPI_USR_CMD_HOLD (BIT(22)) DPORT_PRO_CACHE_MASK_IROM0_S 2 DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) TIMG_WDT_LEVEL_INT_EN_V 0x1 RTC_CNTL_SENSE4_HOLD_FORCE_S 7 MESR_ERRTYPE_SHIFT 30 SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104) RTC_CNTL_CK8M_DIV_SEL 0x00000007 DPORT_PRO_DRAM_HL_M (BIT(16)) SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF SPI_OUT_EOF_MODE (BIT(9)) RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F XCHAL_RESET_VECTOR0_PADDR 0x50000000 EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) __SPI_REG_H__ DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF _REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state) DPORT_PRO_ROM_MPU_AD (BIT(0)) TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094) RTC_CNTL_ENT_RTC_V 0x1 SPI_BUF1 0xFFFFFFFF DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F TIMG_T0_AUTORELOAD_V 0x1 XCHAL_WINDOW_VECTORS_PADDR 0x40000000 DPORT_SHROM_MPU_TABLE22_V 0x3 SPI_SLV_STATUS_READBACK_V 0x1 SPI_DMA_RX_STOP_M (BIT(14)) RTC_CNTL_SCRATCH7 0xFFFFFFFF DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF RTC_CNTL_SCRATCH0_S 0 PARTITION_MAGIC 0x50AA DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF DPORT_PRO_SLC0_INTR_MAP_V 0x1F RTC_CNTL_TXRF_I2C_PU_S 27 DPORT_PERI_IO_SWAP 0x000000FF DPORT_AHBLITE_IA_M (BIT(10)) XCHAL_TIMER0_INTERRUPT 6 DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF SPI_OUT_EOF_INT_ST_M (BIT(7)) RTC_CNTL_CNTL_DATE_S 0 SPI_SLV_WR_ADDR_BITLEN_S 4 DPORT_SPI3_DMA_CHAN_SEL_S 4 EFUSE_CHIP_VER_32PAD_S 2 MEMCTL_DCWA_SHIFT 13 SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) RTC_CNTL_ULP_CP_INT_RAW_S 5 DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) _ANSIDECL_H_ DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) __DEC128_MIN_EXP__ (-6142) RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) RTC_CNTL_PLL_BUF_WAIT_V 0xFF DPORT_SPI1_DMA_CHAN_SEL 0x00000003 DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) Cache_Flush DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) SLP_SEL (BIT(1)) RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) TIMG_LACT_LO 0xFFFFFFFF _T_SIZE RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) ETS_TG1_T0_LEVEL_INTR_SOURCE 18 DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) TIMG_LACT_INT_ST_V 0x1 DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) PERIPHS_SPI_FLASH_USRREG SPI_USER(1) DPORT_PRO_ROM_PD_V 0x1 RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF DPORT_DMMU_TABLE14_V 0x7F EFUSE_DEC_WARNINGS 0x00000FFF DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F DR_REG_I2C1_EXT_BASE 0x3ff67000 ETS_TG1_WDT_EDGE_INTR_SOURCE 64 DPORT_PERI_IO_SWAP_S 0 DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) __UINT_LEAST16_MAX__ 65535 RTC_CNTL_TIME_VALID_V 0x1 DPORT_SHROM_MPU_TABLE11_V 0x3 EFUSE_BLK2_DOUT1_V 0xFFFFFFFF DBREAKC_MASK_SHIFT 0 BIT22 0x00400000 strncmpi strncasecmp DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) MESR_ERRTEST 0x00000200 DPORT_PRO_SPI_INTR_2_MAP_S 0 DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) RTC_CNTL_REG1P8_READY (BIT(24)) SPI_CLKCNT_L 0x0000003F SPI_INLINK_STOP_S 28 EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) EFUSE_DAC_CLK_DIV_S 0 FUNC_GPIO5_HS1_DATA6 3 EFUSE_SDIO_DREFH 0x00000003 RTC_CNTL_SDIO_REJECT_EN_V 0x1 MCU_SEL 0x7 DPORT_APP_IROM0ADDR_IA_V 0xFFFFF SPI_OUTLINK_RESTART_S 30 TIMG_LACT_EDGE_INT_EN_S 12 SPI_WR_BYTE_ORDER (BIT(11)) PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 DPORT_APP_CACHE_MMU_IA (BIT(0)) XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) SPI_SLV_RD_ADDR_BITLEN 0x0000003F SPI_FLASH_READ (BIT(31)) DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) EFUSE_RD_SDIO_FORCE (BIT(16)) RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 DPORT_APPCPU_RESETTING_S 0 PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) EFUSE_RD_INST_CONFIG_V 0xFF EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F DPORT_APP_CPU_RECORDING_V 0x1 __UINT32_TYPE__ long unsigned int UINT_FAST8_MAX (__STDINT_EXP(INT_MAX)*2U+1U) DPORT_PRO_SLC1_INTR_MAP_V 0x1F XCHAL_WINDOW_OF8_VECOFS 0x00000080 SPI_T_PP_ENA_M (BIT(31)) DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) DPORT_APP_TIMER_INT2_MAP 0x0000001F DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) SPI_CLKDIV_PRE_S 18 DPORT_IMMU_TABLE7_V 0x7F SPI_FLASH_RES (BIT(20)) DPORT_APP_UHCI1_INTR_MAP 0x0000001F SPI_CK_I_EDGE_S 6 SPI_DMA_INLINK_DSCR_BF0_S 0 DEBUGCAUSE_ICOUNT_SHIFT 0 XCHAL_HAVE_DFP_DIV 0 XCHAL_XLMI0_SIZE 524288 DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF LLONG_MIN (-LLONG_MAX - 1LL) RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF EFUSE_KEY_STATUS_M (BIT(10)) XCHAL_EXTINT7_NUM 9 XCHAL_INT25_EXTNUM 20 DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) SPI_INLINK_AUTO_RET_S 20 DPORT_RECORD_APP_PDEBUGPC_S 0 EFUSE_BLK3_DOUT5 0xFFFFFFFF DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F _GCC_NEXT_LIMITS_H DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) spi_speed TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 SPI_SLV_WR_STA_DONE_S 3 XCHAL_INT5_LEVEL 1 RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68) RTC_CNTL_SOC_CLK_SEL_V 0x3 DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 SPI_SLV_WRBUF_DUMMY_EN_V 0x1 FUNC_U0RXD_GPIO3 2 SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) SPI_BUF14_V 0xFFFFFFFF XCHAL_INTLEVEL5_VECOFS 0x00000240 TIMG_T1_HI_V 0xFFFFFFFF RTC_CNTL_LOW_POWER_DIAG1_S 0 DPORT_PRO_I2S1_INT_MAP_S 0 XCHAL_INT12_EXTNUM 9 INT_FAST8_MAX __STDINT_EXP(INT_MAX) EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) SPI_USR_MOSI_S 27 CLK_OUT1_S 0 DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF EFUSE_RD_ABS_DONE_0 (BIT(4)) DPORT_AHB_LITE_MASK_PRO_S 0 RTC_CNTL_SLP_VAL_LO_S 0 RTC_CNTL_PDAC2_HOLD_FORCE_S 3 DPORT_APPCPU_BOOT_ADDR_S 0 DPORT_DMMU_PAGE_MODE_V 0x3 FUNC_SD_DATA2_GPIO9 2 __GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) DPORT_PRO_UART_INTR_MAP 0x0000001F _SYS_REENT_H_ __INT_FAST16_TYPE__ int SLP_IE (BIT(4)) EFUSE_OP_CODE_V 0xFFFF SPI_USR_MOSI_HIGHPART (BIT(25)) _END_STD_C EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) DPORT_IMMU_TABLE10_S 0 DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF __lock_release_recursive(lock) (_CAST_VOID 0) TIMG_RTC_CALI_MAX 0x00007FFF __UINT16_TYPE__ short unsigned int DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 DPORT_SHROM_MPU_TABLE17_S 0 EFUSE_RD_XPD_SDIO_REG (BIT(14)) ota_select_crc DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) SPI_CS_SETUP (BIT(5)) UINT_LEAST64_MAX 18446744073709551615ULL PIN_CTRL (DR_REG_IO_MUX_BASE +0x00) RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) DPORT_BT_LPCK_DIV_NUM 0x00000FFF __INT_FAST64_MAX__ 9223372036854775807LL DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F __INTMAX_C(c) c ## LL RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 UINT_MAX RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) FUNC_MTMS_HS2_CLk 3 XCHAL_EXTINT20_NUM 25 __DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L) __DBL_MAX_10_EXP__ 308 SPI_DMA_OUT_STATUS_V 0xFFFFFFFF XCHAL_DCACHE_ECC_PARITY 0 DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF INTMAX_MIN (-INTMAX_MAX - 1) DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 XCHAL_DCACHE_LINE_LOCKABLE 0 __UINT_FAST32_MAX__ 4294967295U RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 DPORT_SRAM_PD_1_V 0x1 TIMG_T0_LO_S 0 XCHAL_HW_CONFIGID_RELIABLE 1 DPORT_I2C_EXT0_CLK_EN (BIT(7)) RTC_CNTL_SLP_REJECT_M (BIT(30)) SPI_IN_DONE_INT_RAW_S 3 DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) DPORT_IMMU_TABLE2_V 0x7F DPORT_BTEXTWAKEUP_REQ (BIT(12)) RTC_CNTL_BROWN_OUT_ENA_V 0x1 XCHAL_HW_VERSION 260003 EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) DPORT_PRO_DRAM_SPLIT_S 11 DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F __DEC32_MANT_DIG__ 7 DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) __P(args) args DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 XCHAL_INT4_EXTNUM 4 DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F SLP_PD (BIT(2)) XCHAL_HAVE_PREFETCH 0 DPORT_APP_SPI_INTR_2_MAP_S 0 XCHAL_HW_MAX_VERSION_MAJOR 2600 RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 DPORT_DMMU_TABLE9 0x0000007F DR_REG_FE2_BASE 0x3ff45000 XCHAL_HAVE_BBE16_VECDIV 0 _REENT_CHECK_TM(ptr) RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 DPORT_APP_PCNT_INTR_MAP_S 0 RTC_CNTL_ROM0_FORCE_ISO_V 0x1 SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 RTC_CNTL_ULP_CP_INT_RAW_V 0x1 EFUSE_BLK3_DIN1 0xFFFFFFFF RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) RTC_CNTL_PLLA_FORCE_PD (BIT(23)) SPI_MASTER_CS_POL 0x0000001F __LONG_LONG_MAX__ 9223372036854775807LL EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) SPI_CK_IDLE_EDGE_S 29 RTC_CNTL_FORCE_PD_V 0x1 SPI_SLV_RDSTA_DUMMY_EN_V 0x1 SPI_CS1_DIS_S 1 DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) DPORT_APP_WR_BAK_TO_READ_V 0x1 SPI_SLV_STATUS_FAST_EN_S 26 PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1(1) SPI_RD_BIT_ORDER_M (BIT(25)) CHAR_BIT EFUSE_BLK1_DOUT6_V 0xFFFFFFFF EFUSE_BLK2_DOUT4 0xFFFFFFFF RTC_CNTL_SW_APPCPU_RST_V 0x1 RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 RTC_CNTL_SCK_DCAP_S 14 SPI_STATUS_V 0xFFFF TIMG_LACT_AUTORELOAD_V 0x1 RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1) SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) XCHAL_WINDOW_OF12_VECOFS 0x00000100 DPORT_AHB_LITE_MASK_SDIO_V 0x1 DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) DPORT_BB_ACCESS_GRANT_CONFIG_S 0 __have_long32 1 RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 __ATOMIC_RELEASE 3 DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F CONFIG_ESPTOOLPY_FLASHFREQ_40M 1 ETS_PWM2_INTR_SOURCE 41 DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF SPI_OUTLINK_STOP_V 0x1 DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) DPORT_SHROM_MPU_TABLE4_S 0 FUNC_GPIO0_CLK_OUT1 1 PRO_CPU_NUM (0) TIMG_LACT_INT_ENA_V 0x1 TIMG_T0_INT_RAW (BIT(0)) DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) RTC_CNTL_PWC_FORCE_PU_S 19 RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 UINTPTR_MAX __UINTPTR_MAX__ BIT15 0x00008000 PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) SPI_FLASH_BYTES_LEN 24 DEBUGCAUSE_ICOUNT_MASK 0x01 RTC_CNTL_CKGEN_I2C_PU_S 30 XCHAL_INSTRAM1_PADDR 0x40400000 TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) DPORT_PRO_CMMU_PD_V 0x1 DPORT_AHB_SPI_REQ_M (BIT(14)) DPORT_WIFI_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) DPORT_APP_INTR_STATUS_1_S 0 RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 GET_PERI_REG_BITS(reg,hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) SPI_FCS_CRC_EN (BIT(10)) DPORT_PRO_UART1_INTR_MAP 0x0000001F DPORT_FAST_CLK_RTC_SEL_V 0x1 SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) TIMG_T1_AUTORELOAD_S 29 SPI_USR_COMMAND_BITLEN 0x0000000F RTC_CNTL_XTL_BUF_WAIT_V 0x3FF DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F EFUSE_CHIP_VER_32PAD_V 0x1 __signed signed DPORT_IMMU_TABLE4_S 0 _RAND48_ADD (0x000b) DPORT_APP_CMMU_PD (BIT(12)) XCHAL_HAVE_HIFIPRO 0 EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL factory SPI_SLV_WR_RD_STA_EN_M (BIT(28)) SPI_BUF8_S 0 SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) SPI_SIZE_16MB SPI_CS_I_MODE_V 0x3 MB_LEN_MAX _MB_LEN_MAX DPORT_APP_IRAM1ADDR_IA_S 0 DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) XCHAL_TRAX_MEM_SIZE 16384 DPORT_LPCLK_SEL_XTAL_S 26 SPI_USR_COMMAND_BITLEN_S 28 DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) PS_INTLEVEL_SHIFT 0 DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) DPORT_SRAM_PD_1_M (BIT(0)) DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) XCHAL_HAVE_HIFI3 0 BIT9 0x00000200 load RTC_CNTL_FASTMEM_PD_EN (BIT(14)) ___int_least16_t_defined 1 ETS_RTC_CORE_INTR_SOURCE 46 TIMG_T0_LEVEL_INT_EN_V 0x1 DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F DPORT_ROM_MPU_TABLE3 0x00000003 DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) SPI_USR_DUMMY_IDLE_V 0x1 DPORT_MASK_PRO_DRAM_S 2 SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) SPI_FLASH_WRDI_S 29 DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138) EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 SPI_IN_SUC_EOF_INT_ENA_V 0x1 DPORT_PRO_BOOT_REMAP_V 0x1 EFUSE_BLK2_DIN7_V 0xFFFFFFFF RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) RTC_CNTL_SW_SYS_RST_V 0x1 SPI_WP_REG_S 21 RTC_CNTL_INTER_RAM3_PD_EN_S 28 TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) ESP_LOGI(tag,format,...) ESP_EARLY_LOGI(tag, format, ##__VA_ARGS__) DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 partition_usage SPI_FLASH_PP_V 0x1 RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF XCHAL_HAVE_NMI 1 SPI_CS_HOLD_DELAY 0x0000000F _LIMITS_H___ __CHAR32_TYPE__ long unsigned int DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) RTC_CNTL_FORCE_ISO (BIT(4)) FUNC_SD_DATA3_U1TXD 4 DPORT_PRO_OUT_VECBASE_SEL_V 0x3 RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) DPORT_DMMU_TABLE7_S 0 SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) __va_copy(d,s) __builtin_va_copy(d,s) DPORT_PERIP_CLK_EN 0xFFFFFFFF XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 PART_SUBTYPE_TEST 0x20 RTC_CNTL_GPIO_REJECT_EN (BIT(24)) SPI_FCS_CRC_EN_M (BIT(10)) XCHAL_HAVE_FUSION 0 TIMG_T0_EDGE_INT_EN_S 12 DPORT_AHB_LITE_MASK_APP (BIT(4)) XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 TIMG_T1_INCREASE_M (BIT(30)) DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) SPI_FLASH_BE_S 23 DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) EFUSE_BLK1_DOUT3 0xFFFFFFFF XCHAL_DATAROM0_BANKS 1 _NOINLINE __attribute__ ((__noinline__)) DPORT_AHB_LITE_MASK_APP_V 0x1 BOOT_VERSION "V0.1" DPORT_PRO_CACHE_VADDR_S 0 SPI_DMA_INLINK_DSCR 0xFFFFFFFF DPORT_AGC_MEM_FORCE_PU_S 0 DPORT_APP_PWM2_INTR_MAP 0x0000001F DPORT_PRO_CACHE_ENABLE_V 0x1 XCHAL_HAVE_L32R 1 __SIZEOF_PTRDIFF_T__ 4 EFUSE_RD_SDIO_DREFH_V 0x3 EFUSE_FLASH_CRYPT_CNT 0x000000FF EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) __ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cname RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 SPI_USR_PREP_HOLD_M (BIT(23)) SPI_SLV_RDSTA_CMD_VALUE_V 0xFF DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 FUNC_U0TXD_U0TXD 0 DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) _REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state) SPI_SIO_V 0x1 SPI_FLASH_WRDI_V 0x1 SPI_FWRITE_DIO (BIT(14)) __INT8_C(c) c DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) EFUSE_DATE_V 0xFFFFFFFF DPORT_PERIP_CLK_EN_V 0xFFFFFFFF SPI_FLASH_SE_S 24 DPORT_PRO_RWBT_IRQ_MAP_S 0 RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F FUNC_SD_CMD_SPICS0 1 TIMG_T1_INT_ENA (BIT(1)) DPORT_PRO_ROM_FO_V 0x1 DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F TIMG_RTC_CALI_START (BIT(31)) RTC_CNTL_WIFI_FORCE_PD_S 17 ESP_LOG_WARN RTCWDT_BROWN_OUT_RESET UINT64_MAX 18446744073709551615ULL RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) XCHAL_UNALIGNED_LOAD_HW 1 FUNC_SD_DATA1_GPIO8 2 encrypt_flag DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF DPORT_PRO_TRACEMEM_ENA (BIT(0)) EFUSE_ABS_DONE_1_S 5 __LDBL_MANT_DIG__ 53 SPI_USR_ADDR_VALUE 0xFFFFFFFF RTC_CNTL_EXT_WAKEUP0_LV_S 30 __FLT_MANT_DIG__ 24 DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) __WINT_MIN__ 0U _POSIX2_RE_DUP_MAX 255 DPORT_APP_INTR_STATUS_1 0xFFFFFFFF DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 XCHAL_DATARAM1_PADDR 0x3F800000 TIMG_LACT_EDGE_INT_EN_M (BIT(12)) TIMG_T1_ALARM_HI_S 0 RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F EFUSE_RD_EFUSE_RD_DIS 0x0000000F FUNC_MTDI_SD_DATA2 4 TIMG_LACT_UPDATE_V 0xFFFFFFFF EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) DPORT_WIFI_CLK_EN 0xFFFFFFFF FUNC_SD_DATA2_U1RXD 4 XCHAL_INT8_LEVEL 1 SPI_FWRITE_QIO_V 0x1 __DEC64_MANT_DIG__ 16 EFUSE_READ_DONE_INT_ENA_S 0 RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) DPORT_APP_CACHE_MMU_IA_V 0x1 RTC_CNTL_PLL_I2C_PU_S 31 SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 EFUSE_ABS_DONE_0_V 0x1 EFUSE_BLK1_DOUT0_S 0 DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) SPI_T_PP_SHIFT 0x0000000F _LDBL_EQ_DBL 1 DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 EXCCAUSE_LOAD_STORE_ERROR 3 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) SPI_IN_DONE_INT_ST_S 3 EFUSE_BLK1_DIN4 0xFFFFFFFF SPI_TX_CRC_DATA_V 0xFFFFFFFF XCHAL_NUM_INSTRAM 2 DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) DPORT_APP_DRAM_SPLIT_V 0x1 DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) XCHAL_HAVE_HIFI2EP 0 RTC_CNTL_WIFI_FORCE_PU_V 0x1 SPI_SLV_WRSTA_DUMMY_EN_S 3 SPI_T_PP_ENA (BIT(31)) RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) EFUSE_CHIP_VER_32PAD (BIT(2)) SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC) TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) TIMG_WDT_EN_V 0x1 DPORT_APP_TX_END_S 20 RTC_CNTL_DREFM_SDIO_S 27 RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) TIMG_LACT_LO_V 0xFFFFFFFF RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 RTC_CNTL_SLOWMEM_FORCE_PU_S 16 SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84) DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) SPI_CS2_DIS_M (BIT(2)) SPI_USR_ADDR (BIT(30)) block_hdr SPI_IN_LOOP_TEST_M (BIT(6)) XCHAL_INT28_LEVEL 4 DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) EFUSE_BLK3_DOUT5_S 0 RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) SPI_USR_ADDR_HOLD (BIT(21)) SPI_FWRITE_DIO_M (BIT(14)) XCHAL_RESET_VECBASE_OVERLAP 0 DPORT_ROM_MPU_TABLE3_S 0 DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) XCHAL_INT31_LEVEL 5 XCHAL_NMI_VECTOR_PADDR 0x400002C0 EFUSE_BLK2_DIN6 0xFFFFFFFF RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 SPI_BUFF_BYTE_READ_NUM 64 DPORT_LPCLK_SEL_XTAL32K_S 27 RTC_CNTL_DIG_CLK8M_EN (BIT(10)) XCHAL_EXTINT15_NUM 20 __DEC128_EPSILON__ 1E-33DL __INTMAX_TYPE__ long long int DR_REG_SPI2_BASE 0x3ff64000 __DBL_HAS_DENORM__ 1 DPORT_APP_ROM_MPU_AD_S 2 DPORT_DMMU_TABLE6_V 0x7F __lock_try_acquire_recursive(lock) (_CAST_VOID 0) RTC_CNTL_TIME_VALID_S 30 RTC_CNTL_WDT_EDGE_INT_EN_S 18 DPORT_APP_MPU_IA_INT_MAP_V 0x1F DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128) FUNC_GPIO2_HSPIWP 1 SPI_INT_HOLD_ENA_V 0x3 RTC_CNTL_ENT_RTC_S 29 DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) EFUSE_RD_ABS_DONE_1 (BIT(5)) DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) DPORT_SHARE_ROM_IA_S 6 DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 XCHAL_HAVE_BOOTLOADER 0 DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF XCHAL_INT31_EXTNUM 25 RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 DPORT_APP_SPI_INTR_1_MAP 0x0000001F DPORT_SRAM_FO_0_S 0 __DBL_MIN_EXP__ (-1021) DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) FUNC_GPIO32_GPIO32_0 0 RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F XCHAL_TIMER1_INTERRUPT 15 PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) XCHAL_HAVE_WIDE_BRANCHES 0 SPI_FREAD_DIO (BIT(23)) DPORT_UHCI0_RST (BIT(8)) SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) SPI_SLV_WR_RD_BUF_EN (BIT(29)) EFUSE_BLK3_DIN5_S 0 FUNC_MTMS_GPIO14 2 DPORT_MASK_PRO_IRAM_V 0x1 DPORT_PRO_CACHE_STATE_S 7 ETS_BT_BB_INTR_SOURCE 4 EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF DPORT_DATE_V 0xFFFFFFF DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50) RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) SPI_BUF2_V 0xFFFFFFFF SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 XCHAL_DCACHE_IS_WRITEBACK 0 RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) BIT21 0x00200000 RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) TIMG_RTC_CALI_CLK_SEL_S 13 RTC_CNTL_WIFI_PD_EN_S 30 INT64_C(x) x ##LL DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 INT_FAST64_MIN INT_LEAST64_MIN RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S)) DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 DPORT_APP_AHB_SPI_REQ_V 0x1 XCHAL_HAVE_FUSION_BITOPS 0 TIMG_WDT_STG3_HOLD_S 0 SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) DPORT_APP_WR_BAK_TO_READ (BIT(19)) __DBL_MIN__ ((double)2.2250738585072014e-308L) TIMG_WDT_INT_ST_S 2 SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) SPI_CS_DELAY_MODE_S 26 ETS_ASSERT(v) do { if (!(v)) { ets_printf("%s %u \n", __FILE__, __LINE__); while (1) {}; } } while (0); EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) DPORT_PWM0_CLK_EN (BIT(17)) DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 DPORT_APPCPU_CLKGATE_EN_S 0 DPORT_UHCI1_CLK_EN (BIT(12)) RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL FUNC_GPIO19_GPIO19_0 0 DPORT_PERI_CLK_EN_V 0xFFFFFFFF SPI_BUF11_V 0xFFFFFFFF TGWDT_CPU_RESET RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S)) PART_TYPE_END 0xff EFUSE_DAC_CLK_DIV 0x000000FF EFUSE_RD_CHIP_VER_RESERVE_V 0xFF ETS_FROM_CPU_INTR0_SOURCE 24 SPI_USR_COMMAND_V 0x1 DPORT_LPCLK_SEL_XTAL (BIT(26)) DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) TIMG_T1_INT_RAW_V 0x1 RTC_CNTL_SLP_WAKEUP_V 0x1 SPI_RESANDRES_M (BIT(15)) __PRAGMA_REDEFINE_EXTNAME 1 RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) XCHAL_NUM_PERF_COUNTERS 2 DPORT_APP_PWM0_INTR_MAP 0x0000001F SPI_FLASH_CE_V 0x1 RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) XCHAL_INT0_EXTNUM 0 __UINT_FAST64_TYPE__ long long unsigned int DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) SPI_IN_DONE_INT_RAW_V 0x1 EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) RTC_CNTL_DG_WRAP_FORCE_RST_S 29 EFUSE_RD_DISABLE_DL_CACHE_V 0x1 RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) __lock_close(lock) (_CAST_VOID 0) __IMPORT DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF RTC_CNTL_BBPLL_FORCE_PD_V 0x1 DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) __INT_LEAST32_MAX__ 2147483647L INT_LEAST16_MIN -32768 SPI_AHBM_RST_M (BIT(5)) SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) DPORT_SHROM_MPU_TABLE2_V 0x3 DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) TIMG_LACT_ALARM_EN_V 0x1 DEBUGCAUSE_DBREAK_SHIFT 2 RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 SPI_FWRITE_QIO (BIT(15)) DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F TICKS_PER_US_ROM 26 XCHAL_HAVE_VECTRA1 0 TIMG_RTC_CALI_START_M (BIT(31)) TIMG_LACT_LEVEL_INT_EN_S 11 TIMG_LACT_RTC_ONLY_S 7 MESR_LCE DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130) __need_wint_t DPORT_DMMU_TABLE0 0x0000007F DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) FUNC_SD_DATA3_SD_DATA3 0 DPORT_APP_SPI3_DMA_INT_MAP_S 0 DPORT_SRAM_PD_1 (BIT(0)) _SIGNED signed DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C) EFUSE_BLK3_DOUT6_V 0xFFFFFFFF PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60) SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) DPORT_APP_MMU_RDATA_S 0 ESP_LOG_ERROR EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) EFUSE_RD_XPD_SDIO_REG_V 0x1 SPI_FLASH_RDID_V 0x1 DPORT_APP_RWBT_NMI_MAP_V 0x1F EFUSE_BLK1_DOUT3_V 0xFFFFFFFF DPORT_INTERNAL_SRAM_IA_S 14 EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) RTC_CNTL_SDIO_PD_EN_V 0x1 DPORT_SHROM_MPU_TABLE18_V 0x3 XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) USHRT_MAX FUNC_MTDO_SD_CMD 4 XCHAL_EXTINT22_NUM 27 RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) DPORT_PRO_CACHE_IA_V 0x3F SPI_BUF3 0xFFFFFFFF EFUSE_SDIO_DREFM_V 0x3 SPI_DMA_RX_STOP (BIT(14)) XCHAL_ICACHE_SETWIDTH 0 RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) DPORT_PRO_CPU_RECORDING_S 0 SPI_MOSI_DELAY_MODE_V 0x3 DPORT_DMMU_TABLE12_S 0 pos_aligned XCHAL_HW_MAX_VERSION_MINOR 3 __attribute_pure__ FUNC_MTDI_GPIO12 2 TIMG_T0_EDGE_INT_EN_V 0x1 DPORT_PERIP_RST_S 0 TIMG_LACT_LEVEL_INT_EN_V 0x1 SPI_ST 0x00000007 EFUSE_BLK3_DIN5_V 0xFFFFFFFF RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 TIMG_LACT_ALARM_LO_S 0 EXCCAUSE_STORE_PROHIBITED 29 SPI_SLV_WRBUF_CMD_VALUE 0x000000FF RTC_CNTL_SW_STALL_PROCPU_C1_S 26 DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) SPI_FLASH_RDSR (BIT(27)) DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) TIMG_T1_INCREASE_V 0x1 EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) DPORT_PRO_SLAVE_WR_M (BIT(21)) RTC_CNTL_TIME_LO_V 0xFFFFFFFF SPI_CK_I_EDGE (BIT(6)) DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_TIME_HI 0x0000FFFF XCHAL_INT8_EXTNUM 6 TIMG_LACT_INCREASE_V 0x1 DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) RTC_MEM_CRC_START_M (BIT(8)) XCHAL_BUILD_UNIQUE_ID 0x0005FE96 DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) XCHAL_DATARAM1_ECC_PARITY 0 SPI_USR_MISO_S 28 rtc_get_reset_reason DPORT_PRO_UART_INTR_MAP_S 0 SPI1_R_DIO_DUMMY_CYCLELEN 3 FUNC_MTDO_HSPICS0 1 ETS_T0_WDT_INUM 3 RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) TIMG_T0_LOAD_HI 0xFFFFFFFF FUNC_SD_DATA0_GPIO7 2 SPI_CK_OUT_EDGE (BIT(7)) EFUSE_DISABLE_SDIO_HOST_V 0x1 RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F XCHAL_HAVE_FP_RECIP 1 XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) DPORT_PRO_TIMER_INT1_MAP_V 0x1F SPI_USR_DOUT_HOLD_M (BIT(18)) SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF DPORT_MASK_PRO_IRAM (BIT(0)) DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF FUNC_GPIO20_GPIO20 2 DPORT_PRO_CMMU_FORCE_ON_V 0x1 DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) XCHAL_INSTRAM1_SIZE 4194304 SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) DPORT_IMMU_PAGE_MODE_S 1 EFUSE_RD_CODING_SCHEME_S 0 EFUSE_RD_SDIO_DREFH_S 8 DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F DPORT_BT_LPCK_DIV_A_S 12 DPORT_APP_CACHE_ENABLE (BIT(3)) DPORT_INTERNAL_SRAM_MMU_AD_V 0xF DPORT_SHROM_MPU_TABLE14 0x00000003 DPORT_APPCPU_RUNSTALL_V 0x1 DPORT_APP_SINGLE_IRAM_ENA_S 10 BIT1 0x00000002 SPI_FWRITE_QUAD (BIT(13)) RTC_CNTL_FORCE_ISO_S 4 EXCCAUSE_DTLB_MISS 24 SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F DPORT_APP_CACHE_MODE (BIT(2)) RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) EFUSE_RD_CHIP_VER_DIS_BT_S 1 DPORT_PRO_CACHE_FLUSH_ENA_S 4 __LDBL_DIG__ 15 DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78) DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) DPORT_SHROM_MPU_TABLE11_S 0 XCHAL_LOOP_BUFFER_SIZE 256 EFUSE_CK8M_FREQ_V 0xFF RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) EFUSE_BLK2_DIN4_V 0xFFFFFFFF RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) partition_info_t TIMG_LACT_LOAD_HI_S 0 SPI_CLKCNT_H 0x0000003F __int_least64_t_defined 1 SPI_IN_ERR_EOF_INT_RAW_S 4 DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) _REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state) EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF RTC_CNTL_PDAC1_HOLD_FORCE_S 2 DPORT_DMMU_PAGE_MODE 0x00000003 RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) DPORT_APP_CACHE_VADDR 0x07FFFFFF RTC_MEM_CRC_LEN (0x7ff) DPORT_SHROM_MPU_TABLE20_V 0x3 TIMG_T1_EDGE_INT_EN (BIT(12)) __PMT(args) args SPI_USR_DOUT_HOLD_V 0x1 TIMG_WDT_STG3_V 0x3 SPI_INT_HOLD_ENA 0x00000003 DPORT_PRO_CACHE_TAG_PD_S 1 _SOC_DPORT_REG_H_ __XTENSA_WINDOWED_ABI__ 1 SPI_USR_ADDR_V 0x1 DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) XCHAL_HAVE_SPECULATION 0 RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) UCHAR_MAX (SCHAR_MAX * 2 + 1) EFUSE_RD_SDIO_DREFM 0x00000003 XCHAL_NUM_INSTROM 1 RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 DPORT_IMMU_TABLE4_V 0x7F __INT8_TYPE__ signed char SPI_WP_REG_V 0x1 SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S)) RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) DBREAKC_MASK_MASK 0x0000003F TIMG_LACT_INT_ENA_M (BIT(3)) DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 DPORT_PRO_CACHE_LOCK_1_EN_S 7 ETS_UHCI0_INTR_SOURCE 12 DPORT_CACHE_MUX_MODE_S 0 DPORT_APP_INTR_STATUS_0_S 0 XCHAL_NUM_CONTEXTS 1 DPORT_PRO_PWM2_INTR_MAP 0x0000001F DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) RTC_CNTL_SLP_REJECT_INT_ENA_S 1 _SYS_CDEFS_H EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) EFUSE_BLK3_DIN3 0xFFFFFFFF RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F SPI_SRAM_QIO_V 0x1 TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) EFUSE_RD_DISABLE_DL_DECRYPT_S 8 DPORT_AHB_SPI_REQ (BIT(14)) DPORT_APP_IRAM0ADDR_IA 0x000FFFFF ETS_BT_MAC_INTR_SOURCE 3 DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) SPI_INT_EN_V 0x1F DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) TIMG_T1_LO 0xFFFFFFFF TIMG_RTC_CALI_START_CYCLING (BIT(12)) EFUSE_BLK1_DIN3_V 0xFFFFFFFF TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S)) __XTENSA_EL__ 1 ETS_TIMER2_INTR_SOURCE 57 TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) DPORT_SLAVE_SPI_MASK_PRO_V 0x1 RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) ETS_PRINTF(...) ets_printf(...) TIMG_T1_LEVEL_INT_EN_M (BIT(11)) DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) XCHAL_HAVE_BBE16 0 TIMG_T0_INT_CLR_M (BIT(0)) DPORT_PRO_SLAVE_WR_V 0x1 PART_SUBTYPE_OTA_FLAG 0x10 DEBUGCAUSE_DEBUGINT_MASK 0x20 RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 RTC_CNTL_SDIO_TIEH_M (BIT(23)) DPORT_PRO_SLAVE_REQ_S 13 RTC_CNTL_PLL_FORCE_NOISO_S 27 DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 RTC_CNTL_CPU_STALL_EN_V 0x1 RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 SPI_BUF13_S 0 TIMG_T0_INT_ENA (BIT(0)) DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_SCRATCH7_V 0xFFFFFFFF XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) SPI_CK_OUT_LOW_MODE_S 8 DPORT_PRO_CACHE_IA_INT_MAP_S 0 DPORT_SHROM_MPU_TABLE3 0x00000003 DPORT_APP_CPU_RECORD_DISABLE_V 0x1 DPORT_APP_CACHE_MASK_DRAM1_S 3 DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F LOG_COLOR_RED "31" _BEGIN_STD_C SPI_SLV_WR_RD_STA_EN_S 28 SPI_MODE_SLOW_READ ULONG_LONG_MAX RTC_CNTL_DREFH_SDIO_V 0x3 LOG_COLOR(COLOR) "\033[0;" COLOR "m" __INT_FAST64_TYPE__ long long int DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) ETS_UART0_INUM 5 DPORT_APP_ROM_FO_S 1 EFUSE_BLK2_DOUT6 0xFFFFFFFF DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) RTC_IRAM_HIGH 0x400C2000 DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) RTC_CNTL_ROM0_PD_EN_M (BIT(24)) DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF SPI_RESANDRES_S 15 DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF RTC_CNTL_ENB_CK8M_DIV (BIT(7)) _MACHINE__TYPES_H DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) SPI_SLV_WR_RD_STA_EN_V 0x1 SPI_SIO_M (BIT(16)) EFUSE_BLK1_DOUT7_S 0 TIMG_T0_ALARM_LO 0xFFFFFFFF SPI_WRSR_2B (BIT(22)) SPI_OUT_DONE_INT_RAW_M (BIT(6)) SPI_BUF2_S 0 EFUSE_READ_DONE_INT_ENA (BIT(0)) TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) RTC_CNTL_RFRX_PBUS_PU_V 0x1 PERIPHS_SPI_FLASH_USRREG1 SPI_USER1(1) DPORT_APP_PWM3_INTR_MAP_S 0 EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) DPORT_APP_ROM_FO_V 0x1 SPI_FWRITE_DUAL_S 12 RTC_CNTL_DIG_DBIAS_WAK_S 11 RTC_CNTL_XPD_SDIO_REG_S 31 __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 TIMG_LACT_ALARM_HI 0xFFFFFFFF MEMCTL_ICWU_MASK 0x007C0000 RTC_MEM_CRC_START (BIT(8)) MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK) EFUSE_RD_XPD_SDIO_REG_S 14 RTC_CNTL_CKGEN_I2C_PU (BIT(30)) SPI_FLASH_RES_V 0x1 MEMCTL_INV_EN 0x00800000 FUNC_GPIO19_VSPIQ 1 RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 EXCCAUSE_CP1_DISABLED 33 RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) DPORT_APP_BT_MAC_INT_MAP 0x0000001F RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 RTC_CNTL_POWERUP_TIMER 0x0000007F DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) DPORT_SHROM_MPU_TABLE9_V 0x3 __STDC_VERSION__ 199901L EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) EFUSE_SPI_PAD_CONFIG_CS0_S 15 ESP_LOGV(tag,format,...) ESP_EARLY_LOGV(tag, format, ##__VA_ARGS__) TIMG_T0_INT_CLR (BIT(0)) _SYS_FEATURES_H RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) SPI_OUT_LOOP_TEST_M (BIT(7)) DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F RTC_CNTL_CKGEN_I2C_PU_V 0x1 RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) _VA_LIST_T_H XCHAL_HAVE_VECBASE 1 DPORT_I2S1_RST (BIT(21)) EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) DPORT_RECORD_APP_PID 0x00000007 SPI_SLV_STATUS_BITLEN_S 27 DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) DPORT_APP_AHB_SPI_REQ (BIT(12)) EFUSE_CODING_SCHEME_V 0x3 DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) FUN_IE (BIT(9)) SPI_OUT_EOF_INT_CLR_M (BIT(7)) flash_hdr RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) XCHAL_EXTINT5_NUM 5 TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) LOG_COLOR_BLACK "30" EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) SPI_BUFF_BYTE_READ_BITS 0x3f RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 DPORT_DMMU_TABLE1_S 0 SPI_INLINK_RESTART_M (BIT(30)) ULONG_LONG_MAX (LONG_LONG_MAX * 2ULL + 1ULL) DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_FORCE_PD_S 30 RTC_CNTL_DIG_CLK8M_D256_EN_S 9 TIMG_WDT_STG3_S 23 sizetype DPORT_INTERNAL_SRAM_MMU_MISS_S 0 TIMG_T1_LOAD_LO_S 0 DPORT_SPI1_DMA_CHAN_SEL_S 0 RTC_CNTL_WAKEUP_ENA_S 11 __LDBL_MAX__ 1.7976931348623157e+308L RTC_CNTL_CPUSEL_CONF_V 0x1 SPI_USR_MOSI_DBITLEN 0x00FFFFFF XCHAL_INTLEVEL5_MASK 0x84010000 FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2) SPI_OUT_RST_S 3 DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) RTC_CNTL_CPUPERIOD_SEL_S 30 SPI_USR_HOLD_POL_S 17 EXCCAUSE_CP5_DISABLED 37 RTC_CNTL_WDT_STG2_V 0x7 DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) DPORT_APP_CACHE_TAG_PD (BIT(9)) TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) MESR_MEME_SHIFT 0 DPORT_APP_SLAVE_WR_S 21 TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S)) SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) EFUSE_BLK2_DIN4_S 0 TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) TIMG_T0_LOAD_HI_V 0xFFFFFFFF DBREAKC_STOREBREAK_MASK 0x80000000 RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) ESP_PLATFORM 1 EFUSE_BLK1_DIN5_V 0xFFFFFFFF SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC) RTC_CNTL_WIFI_POWERUP_TIMER_S 9 EFUSE_SDIO_TIEH_S 15 SPI_SLV_STATUS_READBACK_M (BIT(25)) DPORT_LPCLK_SEL_XTAL_V 0x1 EFUSE_BLK2_DOUT3_S 0 SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118) ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) DPORT_SHROM_MPU_TABLE20_S 0 TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S)) PS_PROG_SHIFT PS_UM_SHIFT DPORT_APP_CACHE_MASK_DROM0_S 4 section_header RTC_DATA_HIGH 0x50002000 RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 PS_EXCM_SHIFT 4 DPORT_AHBLITE_ACCESS_DENY_V 0x1 RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) SPI_USR_ADDR_HOLD_V 0x1 RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) RTC_CNTL_DREFM_SDIO_V 0x3 XCHAL_HAVE_DEBUG_APB 1 DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F FUN_PD (BIT(7)) DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) EFUSE_DISABLE_DL_DECRYPT (BIT(8)) SPI_INLINK_AUTO_RET_M (BIT(20)) EFUSE_READ_DONE_INT_CLR (BIT(0)) RTC_CNTL_WIFI_PD_EN (BIT(30)) DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) DPORT_MASK_PRO_DRAM_V 0x1 DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) __GCC_ATOMIC_BOOL_LOCK_FREE 2 DPORT_LPCLK_SEL_8M (BIT(25)) _REENT_CHECK_EMERGENCY(ptr) DPORT_PRO_PWM0_INTR_MAP 0x0000001F RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 XCHAL_INT22_EXTNUM 17 EFUSE_ABS_DONE_0_M (BIT(4)) DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) EFUSE_RD_CHIP_VER_32PAD_S 2 SPI_FLASH_PER_M (BIT(16)) DPORT_ACCESS_CHECK_PRO_V 0x1 DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F XCHAL_DCACHE_ACCESS_SIZE 1 DPORT_PRO_OUT_VECBASE_REG_S 0 PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) DPORT_IMMU_TABLE11 0x0000007F BIT11 0x00000800 EFUSE_CHIP_VER_DIS_BT (BIT(1)) DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF XCHAL_PREFETCH_BLOCK_ENTRIES 0 SPI_MODE_DIO DPORT_PRO_IRAM0ADDR_IA_S 0 DPORT_APP_SLAVE_WDATA_V_V 0x1 MESR_WAYNUM_SHIFT 16 PART_SUBTYPE_DATA_RF 0x01 TIMG_T0_EDGE_INT_EN (BIT(12)) PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE __DEC64_MAX_EXP__ 385 EFUSE_CLK_EN_M (BIT(16)) SPI_BUF10 0xFFFFFFFF DPORT_PRO_WR_BAK_TO_READ (BIT(19)) DPORT_PRO_SLC0_INTR_MAP_S 0 RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 RTC_CNTL_CK8M_WAIT_S 6 SPI_CK_I_EDGE_M (BIT(6)) RTC_CNTL_BROWN_OUT_ENA (BIT(30)) FUNC_GPIO34_GPIO34_0 0 SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 __EXPORT SPI_FLASH_RES_S 20 DPORT_IMMU_TABLE1 0x0000007F __STDC_UTF_16__ 1 SPI_USR_MOSI_HIGHPART_M (BIT(25)) SPI_OUTDSCR_BURST_EN (BIT(10)) RTC_CNTL_SCRATCH1 0xFFFFFFFF RTC_CNTL_CK8M_DFREQ_FORCE_S 11 TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) RTC_CNTL_SCRATCH1_S 0 DPORT_MAC_DUMP_MODE_S 5 DPORT_APP_TIMER_INT2_MAP_V 0x1F DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F SPI_USR_DIN_HOLD_V 0x1 BIT30 0x40000000 DPORT_MAC_DUMP_MODE_V 0x3 RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) RTC_CNTL_SLP_VAL_HI_V 0xFFFF XCHAL_HAVE_BBE16_DESPREAD 0 SPI_SLV_CMD_DEFINE_M (BIT(27)) RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F RTC_CNTL_PD_EN_M (BIT(20)) INT16_MAX 32767 DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF DPORT_TIMERS_CLK_EN (BIT(0)) DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70) DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) EFUSE_BLK2_DOUT5 0xFFFFFFFF RTC_CNTL_WIFI_FORCE_ISO_S 28 EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) __long_double_t long double DR_REG_UART_BASE 0x3ff40000 EFUSE_BLK1_DIN6_S 0 SPI_SLV_STATUS_FAST_EN_M (BIT(26)) SPI_OUT_TOTAL_EOF_INT_RAW_S 8 RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 DPORT_SHARE_ROM_FO 0x0000003F XCHAL_HAVE_CONST16 0 DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) stricmp strcasecmp RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) DPORT_AHB_ACCESS_GRANT_1_V 0x1FF DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF __LDBL_EPSILON__ 2.2204460492503131e-16L XCHAL_HAVE_PSO 0 DPORT_WIFI_RST_V 0xFFFFFFFF RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F __ATOMIC_SEQ_CST 5 DPORT_ROM_MPU_TABLE2 0x00000003 DPORT_PRO_CACHE_TAG_PD (BIT(1)) DPORT_DMMU_TABLE8_V 0x7F SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C) DPORT_SLAVE_REQ_S 15 FUNC_GPIO21_GPIO21 2 RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) _REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf) RTC_CNTL_POWERUP_TIMER_V 0x7F DPORT_UART2_CLK_EN (BIT(23)) RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) EFUSE_BLK1_DOUT0_V 0xFFFFFFFF SPI_CLK_EQU_SYSCLK (BIT(31)) DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) SPI_INDSCR_BURST_EN (BIT(11)) DPORT_PRO_TX_END (BIT(20)) DPORT_SHARE_ROM_FO_V 0x3F RTC_CNTL_TIME_VALID_INT_ST_V 0x1 DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) TIMG_LACT_ALARM_EN_S 10 DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) XCHAL_INTTYPE_MASK_PROFILING 0x00000800 DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 RTC_CNTL_SCRATCH0 0xFFFFFFFF TIMG_T1_EDGE_INT_EN_S 12 RTC_CNTL_XTL_BUF_WAIT_S 14 RTC_CNTL_SDIO_ACT_DNUM_S 22 _LONG_DOUBLE long double SPI_OUT_RST (BIT(3)) DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) DPORT_APP_IROM0ADDR_IA_S 0 SPI_USR_ADDR_VALUE_V 0xFFFFFFFF DPORT_PRO_ROM_MPU_AD_V 0x1 DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F RTC_CNTL_WDT_EN_S 31 DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) XCHAL_INT3_EXTNUM 3 SPI_OUT_LOOP_TEST (BIT(7)) TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) DPORT_APP_CACHE_LOCK_2_EN_V 0x1 DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 TIMG_WDT_EDGE_INT_EN_V 0x1 DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) CLK_OUT2_S 4 SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) EFUSE_BLK1_DIN6 0xFFFFFFFF XCHAL_TRAX_ATB_WIDTH 32 DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) XCHAL_INSTROM0_VADDR 0x40800000 DPORT_PRO_MMU_IA_INT_MAP_V 0x1F DPORT_SHROM_MPU_TABLE7 0x00000003 XCHAL_VECBASE_RESET_PADDR 0x40000000 DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F EFUSE_BLK2_DIN1_V 0xFFFFFFFF SPI_FLASH_SE (BIT(24)) RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) RTC_CNTL_TIME_VALID_INT_ST_S 4 RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) SPI_ST_V 0x7 DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) FUNC_SD_CMD_SD_CMD 0 MEMCTL_DCWU_BITS 5 RTC_CNTL_XTL_FORCE_ISO_S 23 DPORT_PRO_CACHE_IA 0x0000003F EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) SPI_AHBM_FIFO_RST_M (BIT(4)) BIT28 0x10000000 DPORT_APP_BOOT_REMAP_V 0x1 SPI_FLASH_PER (BIT(16)) DPORT_SHROM_MPU_TABLE18_S 0 RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) SPI_SETUP_TIME 0x0000000F XCHAL_HAVE_DFPU_SINGLE_ONLY 1 SPI1_R_FAST_ADDR_BITSLEN 23 DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) TIMG_T0_ALARM_EN_M (BIT(10)) SPI_T_ERASE_SHIFT_S 16 Cache_Read_Disable __INT8_MAX__ 127 RTC_CNTL_FORCE_PU (BIT(31)) XCHAL_HAVE_HIFI_MINI 0 RTC_CNTL_SAR_INT_CLR_V 0x1 SPI_SLAVE_MODE_S 30 SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) ESP_EARLY_LOGD(tag,format,...) if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) { ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) SPI_OUTLINK_START_V 0x1 DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) __DEC64_MIN_EXP__ (-382) EFUSE_READ_CMD_S 0 XCHAL_INT12_LEVEL 1 RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) SPI_SLV_LAST_COMMAND_V 0x7 __UINT_LEAST32_TYPE__ long unsigned int RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) DPORT_APP_I2S1_INT_MAP_V 0x1F SPI_SLV_STATUS_READBACK_S 25 TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S)) SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) __UINT64_MAX__ 18446744073709551615ULL DEBUGCAUSE_BREAKN_SHIFT 4 DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 SPI_FLASH_BP1 BIT3 __INT16_C(c) c SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C) DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F RTC_CNTL_WDT_FEED_S 31 CONFIG_ESPTOOLPY_BAUD 115200 DPORT_PRO_PWM1_INTR_MAP_V 0x1F DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) ESP_EARLY_LOGV(tag,format,...) if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) { ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } SPI_SLV_WRBUF_CMD_VALUE_V 0xFF MCU_SEL_S 12 DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) __UINTPTR_TYPE__ unsigned int DPORT_APP_I2C_EXT1_INTR_MAP_S 0 TIMG_LACT_LEVEL_INT_EN (BIT(11)) RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) SPI_FWRITE_DIO_V 0x1 RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) DPORT_APP_CACHE_ENABLE_V 0x1 DPORT_LPCLK_SEL_8M_V 0x1 EFUSE_WIFI_MAC_CRC_LOW_S 0 SPI_INLINK_AUTO_RET (BIT(20)) RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) DPORT_AHBLITE_ACCESS_DENY (BIT(9)) call_start_cpu0 __SIZEOF_SIZE_T__ 4 DPORT_SPI_ENCRYPT_ENABLE_V 0x1 SPI_T_ERASE_SHIFT 0x0000000F DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) TIMG_WDT_WKEY_S 0 SPI_USR_ADDR_S 30 __WINT_MAX__ 4294967295U RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) DPORT_PRO_CPU_RECORD_ENABLE_S 0 EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 __bounded XCHAL_HAVE_USER_DPFPU 0 DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) SPI_CLKCNT_H_S 6 CHAR_BIT __CHAR_BIT__ DPORT_APP_CPU_RECORDING (BIT(0)) DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 DPORT_PRO_ROM_IA_S 1 TIMG_WDT_INT_CLR_S 2 DPORT_I2S0_RST (BIT(4)) RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL EFUSE_RD_KEY_STATUS_S 10 DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) RTC_CNTL_X32P_HOLD_FORCE_V 0x1 __LDBL_DENORM_MIN__ 4.9406564584124654e-324L DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF TIMG_WDT_INT_ST (BIT(2)) DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) __GNUC_MINOR__ 8 DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) DPORT_DMMU_TABLE2 0x0000007F XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 RTC_RODATA_ATTR __attribute__((section(".rtc.rodata"))) SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) __lock_try_acquire(lock) (_CAST_VOID 0) SPI_DMA_INLINK_DSCR_BF1_S 0 XCHAL_HAVE_MUL32 1 DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) DPORT_AHB_LITE_MASK_APP_S 4 DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 IROM_LOW 0x400D0000 SPI_OUT_EOF_INT_ENA_S 7 SPIUnlock RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) ETS_TG0_T1_LEVEL_INTR_SOURCE 15 DPORT_DMMU_TABLE10_S 0 SPI_FLASH_QE BIT9 RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) SPI_BUF4_S 0 DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) TIMG_T1_EN_M (BIT(31)) SPI_BUF5 0xFFFFFFFF EFUSE_PGM_CMD_S 1 RTC_CNTL_DIG_XTAL32K_EN_S 8 REG_SET_BITS(_r,_b,_m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) PS_EXCM PS_EXCM_MASK SPI0_R_SIO_ADDR_BITSLEN 23 XCHAL_WINDOW_UF4_VECOFS 0x00000040 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) DPORT_APP_INTR_STATUS_2_S 0 MESR_RCE 0x00000010 RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) __DBL_DECIMAL_DIG__ 17 BIT29 0x20000000 TIMG_LACT_LOAD_HI 0xFFFFFFFF DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 SPI_INT_EN_S 5 SPI_SLV_STATUS_FAST_EN_V 0x1 XCHAL_HAVE_BOOLEANS 1 RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF DPORT_IMMU_TABLE5_S 0 RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) TIMG_T0_INT_ST_S 0 SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64) DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) TIMG_WDT_STG2_HOLD_S 0 DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 __UINTPTR_MAX__ 4294967295U DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 FUNC_U0TXD_CLK_OUT3 1 SPI_OUT_LOOP_TEST_S 7 XCHAL_MMU_RING_BITS 0 XCHAL_INT19_LEVEL 2 DPORT_DMMU_TABLE10 0x0000007F TIMG_WDT_CPU_RESET_LENGTH 0x00000007 RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F DPORT_PRO_UART1_INTR_MAP_S 0 DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) XCHAL_HAVE_DFP_RECIP 0 SPI0_R_FAST_DUMMY_CYCLELEN 7 TIMG_LACT_RTC_ONLY_V 0x1 RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) SPI_CS_HOLD_DELAY_S 28 RTC_CNTL_TIME_VALID_INT_CLR_S 4 TIMG_LACT_INT_RAW_M (BIT(3)) DPORT_LPCLK_SEL_XTAL32K_V 0x1 CHAR_MIN 0 LONG_LONG_MAX __LONG_LONG_MAX__ BIT3 0x00000008 RTC_CNTL_ROM0_FORCE_PD_V 0x1 RTC_CNTL_SDIO_TIEH (BIT(23)) XCHAL_DCACHE_SIZE 0 SPI_SLV_RDSTA_CMD_VALUE 0x000000FF DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) TIMG_T1_INT_ENA_V 0x1 XCHAL_HAVE_FUSION_AES 0 RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 DPORT_APP_PWM0_INTR_MAP_S 0 RTC_CNTL_REG1P8_READY_S 24 RTC_CNTL_WIFI_WAIT_TIMER_S 0 SPI_CK_DIS_S 5 RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 RTC_CNTL_CK8M_DIV 0x00000003 RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 SPI_SLV_RD_STA_DONE_S 2 SPI_DMA_IN_STATUS 0xFFFFFFFF XCHAL_INTLEVEL6_MASK 0x00000000 EFUSE_SDIO_DREFL 0x00000003 DPORT_MMU_IA_INT_EN_S 0 SPI_CACHE_FLASH_PES_EN_S 3 SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF TIMG_T0_DIVIDER 0x0000FFFF DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) SPI_FLASH_RDID (BIT(28)) BIT(nr) (1UL << (nr)) EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) DPORT_DMMU_TABLE8_S 0 IRAM_ATTR __attribute__((section(".iram1"))) __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) irom_page_count XCHAL_CORE_ID "esp32_v3_49_prod" _ETSTR(v) #v DPORT_APP_SPI_INTR_3_MAP 0x0000001F FUNC_GPIO35_GPIO35_0 0 USHRT_MAX (SHRT_MAX * 2 + 1) SPI_USR_M (BIT(18)) DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) EFUSE_BLK1_DIN3_S 0 RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) RTC_CNTL_FASTMEM_FORCE_PD_S 12 SPI_CACHE_REQ_EN_S 0 IROM_HIGH 0x40400000 SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C) DPORT_SHROM_MPU_TABLE16 0x00000003 XCHAL_USER_VECTOR_VADDR 0x40000340 DPORT_PIDGEN_IA_S 6 XCHAL_DATARAM1_BANKS 1 SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) SPI_IN_LOOP_TEST_S 6 DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) DPORT_SHROM_MPU_TABLE17 0x00000003 FUNC_GPIO23_VSPID 1 RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) TIMG_T1_LEVEL_INT_EN (BIT(11)) XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR INT_MAX __INT_MAX__ DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 DR_REG_RTCMEM0_BASE 0x3ff61000 FIELD_TO_VALUE(_f,_v) (((_v)&(_f))<<_f ##_S) SPI_SRAM_DIO (BIT(0)) DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) DPORT_SHROM_MPU_TABLE5_S 0 DPORT_SHROM_MPU_TABLE21 0x00000003 READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) EFUSE_BLK1_DOUT6 0xFFFFFFFF EFUSE_BLK3_DIN5 0xFFFFFFFF EFUSE_READ_DONE_INT_ENA_V 0x1 EFUSE_DISABLE_JTAG_M (BIT(6)) DPORT_APP_SPI_INTR_0_MAP_V 0x1F DPORT_IMMU_TABLE6_V 0x7F SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC) DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F SPI_USR_CMD_HOLD_M (BIT(22)) XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 DPORT_IMMU_TABLE10_V 0x7F RTC_CNTL_TOUCH_INT_RAW (BIT(6)) DPORT_SHROM_MPU_TABLE16_V 0x3 DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F DPORT_SHARE_ROM_MPU_AD_V 0x3 DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) RTC_CNTL_SDIO_ACTIVE_IND_S 28 _REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next) EFUSE_DISABLE_DL_ENCRYPT_S 7 XCHAL_EXTINT24_NUM 30 bootloader_state_t EFUSE_SDIO_DREFL_S 12 DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) DPORT_PRO_CACHE_LOCK_3_EN_S 9 DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 RTC_CNTL_DBOOST_FORCE_PD_S 28 RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) _VA_LIST_DEFINED DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 TIMG_T0_INT_RAW_V 0x1 FUNC_GPIO25_GPIO25_0 0 LOG_RESET_COLOR "\033[0m" DPORT_APP_CMMU_FORCE_ON_V 0x1 DPORT_SLAVE_SPI_MASK_APP_V 0x1 ETS_WIFI_MAC_NMI_SOURCE 1 __UINT8_MAX__ 255 SPI_FLASH_PP_M (BIT(25)) BIT8 0x00000100 SPI_USR_COMMAND (BIT(31)) EFUSE_BLK3_DOUT0_V 0xFFFFFFFF DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 FUNC_GPIO22_U0RTS 3 DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) DPORT_PRO_BT_BB_INT_MAP_V 0x1F XCHAL_UNALIGNED_LOAD_EXCEPTION 0 RTC_CNTL_DBOOST_FORCE_PU_V 0x1 DPORT_APP_CACHE_MODE_M (BIT(2)) RTC_CNTL_DIG_CLK8M_EN_S 10 RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) __PTRDIFF_MAX__ 2147483647 DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) SPI_FREAD_QIO_S 24 bootloader_main RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) EFUSE_BLK1_DOUT1_S 0 EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) _NOARGS void __XSTRING(x) __STRING(x) MEMCTL_DCWA_BITS 5 DPORT_PRO_CACHE_STATE 0x00000FFF RTC_DATA_ATTR __attribute__((section(".rtc.data"))) DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) TIMG_T0_EDGE_INT_EN_M (BIT(12)) RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) __INT_LEAST8_MAX__ 127 RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 SPI_CACHE_FLASH_USR_CMD (BIT(2)) SPI_FLASH_RDID_S 28 EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) RTC_CNTL_SENSE2_HOLD_FORCE_S 5 DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) DPORT_PRO_CACHE_MMU_IA (BIT(0)) DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) RTC_CNTL_SCRATCH4 0xFFFFFFFF SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) XCHAL_CA_BITS 4 __size_t__ SPI_DMA_CONTINUE_M (BIT(16)) RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 BIT26 0x04000000 FUNC_GPIO22_GPIO22 2 _STDARG_H _HAVE_STDC XCHAL_HAVE_DCACHE_TEST 0 DPORT_LPCLK_SEL_XTAL_M (BIT(26)) FUNC_GPIO36_GPIO36 2 RTC_CNTL_WDT_EN_V 0x1 RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) EFUSE_FLASH_CRYPT_CNT_V 0xFF DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) __DEC64_MAX__ 9.999999999999999E384DD RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF EFUSE_BLK3_DOUT6_S 0 DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 DPORT_APP_UART2_INTR_MAP 0x0000001F DPORT_PRO_TRACEMEM_ENA_V 0x1 RTC_CNTL_CK8M_WAIT 0x000000FF EFUSE_CODING_SCHEME 0x00000003 RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) DPORT_RECORD_PRO_PDEBUGDATA_S 0 RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) RTC_CNTL_REJECT_CAUSE 0x0000000F RTC_CNTL_CK8M_FORCE_NOGATING_S 16 RTC_CNTL_CPU_STALL_EN_M (BIT(0)) FUNC_GPIO21_VSPIHD 1 SPI_OUT_DONE_INT_RAW_S 6 DPORT_PWM3_CLK_EN (BIT(26)) XCHAL_INTLEVEL2_MASK 0x00380000 DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) PS_RING(n) (((n)&3)<<PS_RING_SHIFT) DPORT_PRO_CPU_RECORD_DISABLE_S 4 DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) DPORT_ROM_MPU_TABLE3_V 0x3 DPORT_CACHE_MUX_MODE 0x00000003 SPI_USR_V 0x1 DPORT_UART1_RST (BIT(5)) SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S)) DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) DPORT_PRO_UHCI0_INTR_MAP_S 0 seq_label DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 XCHAL_HAVE_OCD 1 SPI1_R_QIO_DUMMY_CYCLELEN 3 DPORT_PRO_CAN_INT_MAP_S 0 DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F XCHAL_INT15_LEVEL 3 EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) EFUSE_READ_DONE_INT_ENA_M (BIT(0)) DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 _LONG_LONG_TYPE long long DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) SPI_SLV_RD_ADDR_BITLEN_S 10 TIMG_T1_EN (BIT(31)) SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24) TIMG_WDT_STG1_V 0x3 __SIZE_T EFUSE_SDIO_FORCE_S 16 DR_REG_SPI3_BASE 0x3ff65000 RTC_CNTL_WDT_INT_ENA_M (BIT(3)) DR_REG_RMT_BASE 0x3ff56000 XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) DPORT_SRAM_FO_1_S 0 ota_info ETS_WDT_INTR_SOURCE 55 RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 TIMG_WDT_WKEY_V 0xFFFFFFFF DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 TIMG_LACT_EDGE_INT_EN (BIT(12)) CLK_OUT2 0xf TIMG_WDT_EDGE_INT_EN_S 22 SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) SPI_CS2_DIS_V 0x1 PS_UM_SHIFT 5 RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) SPI_FLASH_RESULT_ERR DPORT_PRO_RWBT_NMI_MAP 0x0000001F EFUSE_BLK3_DIN6_S 0 TIMG_NTIMERS_DATE_S 0 DR_REG_UHCI0_BASE 0x3ff54000 ETS_SPI0_INTR_SOURCE 28 EFUSE_RD_ABS_DONE_0_V 0x1 XCHAL_HAVE_XLT_CACHEATTR 0 CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM DPORT_PRO_MMU_RDATA_V 0x1FF DPORT_SHARE_ROM_MPU_ENA_S 0 DPORT_ACCESS_CHECK_APP_V 0x1 RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) SPI_SRAM_DIO_V 0x1 DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) SPI_FLASH_WRSR_V 0x1 DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) __LDBL_MIN_EXP__ (-1021) RTC_CNTL_DIG_DBIAS_WAK_V 0x7 DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) EFUSE_BLK1_DOUT2_V 0xFFFFFFFF RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) EFUSE_RD_SDIO_TIEH_M (BIT(15)) BIT25 0x02000000 SPI_IN_ERR_EOF_INT_RAW (BIT(4)) RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) SPI_CS1_DIS_M (BIT(1)) DPORT_APP_CACHE_TAG_PD_S 9 DPORT_MASK_AHB (BIT(4)) DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 DPORT_UART_MEM_RST (BIT(24)) RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 TIMG_WDT_CPU_RESET_LENGTH_S 18 DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) __LDBL_HAS_INFINITY__ 1 SPI_BUF5_V 0xFFFFFFFF RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) EFUSE_SPI_PAD_CONFIG_CLK_S 0 DPORT_APP_TRACEMEM_ENA_V 0x1 SPI_SLV_WR_BUF_DONE_S 1 RTC_CNTL_PVTMON_PU_M (BIT(26)) RTC_CNTL_DBOOST_FORCE_PD_V 0x1 DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) INT_FAST16_MIN (-__STDINT_EXP(INT_MAX)-1) DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF SPI_USR_MISO_M (BIT(28)) DR_REG_RTCIO_BASE 0x3ff48400 DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 DPORT_PRO_MMU_RDATA 0x000001FF XCHAL_HAVE_BE 0 SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 SPI_OUT_DONE_INT_CLR_S 6 RTC_CNTL_PLL_FORCE_NOISO_V 0x1 SPI_DMA_RX_STOP_S 14 RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 TIMG_WDT_EN (BIT(31)) SPI_CK_OUT_HIGH_MODE_S 12 XCHAL_HAVE_CALL4AND12 1 RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 TIMG_T0_AUTORELOAD (BIT(29)) EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) _ROM_SPI_FLASH_H_ PS_CALLINC_MASK 0x00030000 DPORT_APP_UHCI0_INTR_MAP_S 0 SW_RESET SPI_MISO_DELAY_NUM_V 0x7 DPORT_APP_RWBLE_NMI_MAP_V 0x1F RTC_CNTL_BROWN_OUT_INT_ST_S 7 SPI_FLASH_PES_S 17 RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) FUNC_MTCK_EMAC_RX_ER 5 DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) RTC_CNTL_DIG_ISO_FORCE_ON_S 8 TIMG_LACT_EN_V 0x1 SPI_OUTLINK_START_M (BIT(29)) DPORT_PRO_DROM0ADDR0_IA_S 0 EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) DPORT_IMMU_TABLE13 0x0000007F DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 FUNC_GPIO16_HS1_DATA4 3 EFUSE_BLK2_DOUT5_V 0xFFFFFFFF OWDT_RESET SPI_DMA_OUTLINK_DSCR_BF0_S 0 PERIPHS_SPI_FLASH_ADDR SPI_ADDR(1) __va_list__ RTC_CNTL_BB_I2C_FORCE_PD_S 6 __SIZE_T__ __INT_LEAST64_MAX__ 9223372036854775807LL DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) DPORT_DMMU_TABLE12 0x0000007F RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) SPI_CACHE_FLASH_PES_EN (BIT(3)) DR_REG_SPI1_BASE 0x3ff42000 SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C) RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 SPI_SLV_WR_STA_DONE_V 0x1 SPI_SIZE_MAX DPORT_APP_I2S1_INT_MAP_S 0 RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F DPORT_IMMU_TABLE3 0x0000007F SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) DPORT_APP_CACHE_VADDR_V 0x7FFFFFF SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF _REENT_EMERGENCY_SIZE 25 DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) XCHAL_INT27_EXTNUM 22 TIMG_WDT_STG1_HOLD_S 0 EFUSE_BLK2_DOUT2_S 0 RTC_CNTL_SLP_WAKEUP_M (BIT(29)) DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) SPI_OUT_RST_M (BIT(3)) DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) RTC_CNTL_XTAL_FORCE_NOGATING_S 15 SPI_W_SIO_ADDR_BITSLEN 23 RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) XCHAL_HAVE_PSO_FULL_RETENTION 0 SPI_T_PP_TIME_V 0xFFF SPI_OUTDSCR_BURST_EN_V 0x1 FUN_DRV 0x3 ETS_SPI1_INTR_SOURCE 29 RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) DPORT_SHROM_MPU_TABLE7_V 0x3 SPI_FWRITE_QIO_M (BIT(15)) RTC_CNTL_MIN_SLP_VAL 0x000000FF DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) SPI_FLASH_RDSR_S 27 RTC_CNTL_SCRATCH2 0xFFFFFFFF SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) PS_UM PS_UM_MASK DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) ETS_BT_BB_NMI_SOURCE 5 DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) DPORT_SRAM_PD_0 0xFFFFFFFF RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 test RTC_CNTL_WDT_INT_CLR_S 3 XCHAL_EXTINT3_NUM 3 __int_fast16_t_defined 1 RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) DPORT_PRO_BT_BB_NMI_MAP_S 0 SPI_BUF12 0xFFFFFFFF RTC_CNTL_SCRATCH1_V 0xFFFFFFFF RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF _DEFUN_VOID(name) name(_NOARGS) DPORT_ROM_MPU_TABLE1_V 0x3 RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) __FLT_DIG__ 6 TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090) RTC_MEM_CRC_ADDR_S (9) SPI_FLASH_PP_S 25 RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) SPI_STATUS_EXT 0x000000FF SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60) RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF EFUSE_INST_CONFIG 0x000000FF EFUSE_INST_CONFIG_S 20 DPORT_CACHE_IA_INT_EN 0x0FFFFFFF RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 SPI_T_ERASE_ENA_S 31 RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 RTC_CNTL_DG_WRAP_FORCE_PD_S 19 RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) RTC_CNTL_WDT_FEED_V 0x1 ETS_UART1_INTR_SOURCE 35 SPI_FLASH_RESULT_TIMEOUT __xtensa__ 1 DPORT_APP_RSA_INTR_MAP 0x0000001F SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 DPORT_APP_ROM_MPU_ENA_S 2 RTC_CNTL_RST_BIAS_I2C (BIT(31)) DPORT_PRO_EFUSE_INT_MAP_V 0x1F DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) RTC_CNTL_WDT_STG0_V 0x7 DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF RTC_CNTL_WIFI_FORCE_PD (BIT(17)) RTC_CNTL_DIG_DBIAS_SLP_S 8 __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 SPI_BUF9_V 0xFFFFFFFF RTC_CNTL_CK8M_DIV_SEL_S 12 SPI_CLKDIV_PRE 0x00001FFF PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 DPORT_AHBLITE_ACCESS_DENY_S 9 SPI_SLV_WR_ADDR_BITLEN_V 0x3F SPI_SRAM_ADDR_BITLEN_V 0x3F _MACHINE__DEFAULT_TYPES_H SPI_FREAD_QUAD (BIT(20)) DPORT_UART_RST (BIT(2)) DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) SHRT_MIN RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) DPORT_PRO_I2S0_INT_MAP_S 0 XCHAL_WINDOW_OF4_VECOFS 0x00000000 ETS_RMT_INTR_SOURCE 47 SPI_FLASH_READ_S 31 DPORT_APP_UART2_INTR_MAP_V 0x1F SPI_MODE_DOUT SPI_DOUTDIN (BIT(0)) RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 DPORT_SHROM_MPU_TABLE9 0x00000003 ETS_TG1_T0_EDGE_INTR_SOURCE 62 EFUSE_RD_SDIO_DREFM_V 0x3 DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) FUNC_GPIO33_GPIO33 2 RTC_CNTL_WIFI_FORCE_PD_V 0x1 DPORT_APP_MPU_IA_INT_MAP 0x0000001F EFUSE_READ_DONE_INT_CLR_V 0x1 FUNC_GPIO38_GPIO38_0 0 XCHAL_HW_VERSION_MINOR 3 DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) _T_SIZE_ DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) DPORT_SPI_RST_1 (BIT(1)) DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) SPI_SLV_RD_STA_DONE (BIT(2)) PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F DPORT_PRO_UHCI1_INTR_MAP_S 0 RTC_CNTL_TOUCH_INT_RAW_V 0x1 TIMG_LACT_HI_S 0 SPI_USR_DUMMY_V 0x1 RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8) SPI_CS_SETUP_V 0x1 SPI_OUT_EOF_INT_RAW_V 0x1 __FINITE_MATH_ONLY__ 0 TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) MEMCTL_ICWU_BITS 5 XCHAL_EXTINT19_NUM 24 XCHAL_INSTRAM0_VADDR 0x40000000 PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 __GCC_ATOMIC_INT_LOCK_FREE 2 SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F EFUSE_OP_CODE 0x0000FFFF RTC_CNTL_ROM0_FORCE_ISO_S 16 XCHAL_HAVE_DFP_RSQRT 0 DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) SPI_SRAM_RSTIO_S 4 RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 EFUSE_BLK1_DIN6_V 0xFFFFFFFF INT_FAST16_MAX __STDINT_EXP(INT_MAX) DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) UINT_LEAST32_MAX 4294967295UL EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F EFUSE_BLK3_DOUT0 0xFFFFFFFF DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 __ORDER_LITTLE_ENDIAN__ 1234 DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) DPORT_APP_UHCI1_INTR_MAP_V 0x1F DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) _REENT_INIT(var) { 0, &(var).__sf[0], &(var).__sf[1], &(var).__sf[2], 0, "", 0, "C", 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _NULL, {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}, _NULL, {_NULL, 0, _NULL} } DPORT_APP_BB_INT_MAP_V 0x1F TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S)) DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 EFUSE_RD_SPI_PAD_CONFIG_D_S 10 RTC_CNTL_PLL_BUF_WAIT_S 24 DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) __INT_LEAST64_TYPE__ long long int DPORT_SHROM_MPU_TABLE12_S 0 XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) LOG_COLOR_D EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) RTC_CNTL_RESET_CAUSE_PROCPU_S 0 _POINTER_INT long DPORT_PRO_RSA_INTR_MAP 0x0000001F RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 RTC_CNTL_CPU_STALL_EN_S 0 TIMG_LACT_EDGE_INT_EN_V 0x1 __UINT_LEAST8_MAX__ 255 RTC_CNTL_WDT_INT_RAW_V 0x1 DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) ESP_EARLY_LOGI(tag,format,...) if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } __UINTMAX_MAX__ 18446744073709551615ULL SPI_BUF14_S 0 TIMG_T1_INT_RAW (BIT(1)) TIMG_WDT_LEVEL_INT_EN (BIT(21)) FUNC_MTDO_HS2_CMD 3 TIMG_LACT_ALARM_EN_M (BIT(10)) TIMG_RTC_CALI_CLK_SEL 0x00000003 DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) EFUSE_RD_CK8M_FREQ_V 0xFF FUNC_MTCK_MTCK 0 DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) SPI_SLV_STATUS_READBACK (BIT(25)) TIMG_T1_LO_V 0xFFFFFFFF EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) __FLT_MAX_10_EXP__ 38 EFUSE_SPI_PAD_CONFIG_Q_S 5 RTC_CNTL_XTL_FORCE_PD_V 0x1 SPI_OUTLINK_RESTART_V 0x1 XCHAL_INT18_LEVEL 1 EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) DPORT_APP_SLAVE_WDATA_V (BIT(22)) SPI_OUT_DONE_INT_ST_M (BIT(6)) PTRDIFF_MAX __PTRDIFF_MAX__ DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 DPORT_BTEXTWAKEUP_REQ_V 0x1 XCHAL_DEBUGLEVEL 6 __INT32_C(c) c ## L SPIWrite SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) FUNC_GPIO5_EMAC_RX_CLK 5 DPORT_PRO_TX_END_S 20 DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) DPORT_SLAVE_REQ (BIT(15)) FUNC_GPIO23_GPIO23 2 SPI_USR_RD_SRAM_DUMMY (BIT(4)) EXCCAUSE_LOAD_PROHIBITED 28 RTC_CNTL_ROM0_PD_EN_V 0x1 DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF DPORT_TRACEMEM_MUX_MODE_S 0 DPORT_ARB_IA 0x00000003 DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) FUNC_MTCK_SD_DATA3 4 UINT_LEAST8_MAX 255 PERIPHS_SPI_FLASH_CTRL SPI_CTRL(1) DPORT_PRO_DRAM_SPLIT (BIT(11)) RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) RTC_CNTL_WDT_FEED_M (BIT(31)) RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) SPI_BUF3_S 0 EFUSE_RD_SDIO_FORCE_M (BIT(16)) EFUSE_CHIP_VER_RESERVE_S 9 DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) DPORT_PIDGEN_IA_V 0x3 __lock_acquire_recursive(lock) (_CAST_VOID 0) DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF XCHAL_INTLEVEL3_MASK 0x28C08800 DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) XCHAL_HAVE_DFP_SQRT 0 RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) __CONCAT(x,y) __CONCAT1(x,y) RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) SPI_AHBM_RST (BIT(5)) DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 SPI_DOUTDIN_M (BIT(0)) EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) SPI_IN_SUC_EOF_INT_ENA_S 5 RTC_CNTL_XTL_FORCE_PU (BIT(13)) TG1WDT_SYS_RESET RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F TIMG_RTC_CALI_MAX_V 0x7FFF ROM_CRC_H XCHAL_INT21_LEVEL 2 DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 __SIG_ATOMIC_MAX__ 2147483647 SPI_TX_CRC_EN (BIT(11)) RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 SPI_FLASH_CE_M (BIT(22)) EFUSE_DAC_CLK_PAD_SEL_S 8 RTC_CNTL_SLP_REJECT_INT_CLR_S 1 SPI_RESANDRES (BIT(15)) DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 TIMG_LACT_DIVIDER_S 13 RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 SPI_USR_SRAM_DIO_M (BIT(1)) DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF DPORT_APP_TX_END (BIT(20)) DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF DPORT_APP_ROM_MPU_ENA_V 0x1 DR_REG_UHCI1_BASE 0x3ff4C000 TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) SPI_OUT_DONE_INT_ST (BIT(6)) DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) RTC_CNTL_SCRATCH7_S 0 DPORT_DMMU_TABLE2_S 0 ETS_MPU_IA_INTR_SOURCE 67 FUNC_U0RXD_CLK_OUT2 1 DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F SPI_BUF7 0xFFFFFFFF ETS_SLC1_INTR_SOURCE 11 TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c) DPORT_APP_ROM_MPU_AD_V 0x1 RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) DPORT_PRO_MMU_RDATA_S 0 RTC_CNTL_PLL_FORCE_ISO (BIT(24)) RTC_CNTL_TOUCH_INT_ST_V 0x1 RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) DPORT_PRO_SINGLE_IRAM_ENA_S 10 DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) DPORT_PRO_SLAVE_WDATA_V (BIT(22)) SPI_OUT_AUTO_WRBACK_S 8 RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) DPORT_SHARE_ROM_MPU_AD_S 4 TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) GNU C 4.8.5 -mlongcalls -g3 -Og -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields __volatile volatile RTC_CNTL_REJECT_CAUSE_S 28 EFUSE_BLK2_DIN5_S 0 DPORT_MASK_PRO_IRAM_M (BIT(0)) RTC_CNTL_DG_WRAP_PD_EN_S 31 RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 DPORT_AGC_MEM_FORCE_PU_V 0x1 DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F BIT23 0x00800000 DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) EFUSE_BLK2_DOUT4_S 0 DPORT_PRO_MPU_IA_INT_MAP_V 0x1F RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 SPI_OUT_EOF_INT_RAW_M (BIT(7)) DPORT_SHROM_MPU_TABLE21_S 0 EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) DPORT_APP_CACHE_FLUSH_ENA_S 4 __ptrvalue RTC_IRAM_ATTR __attribute__((section(".rtc.text"))) EFUSE_PGM_DONE_INT_ST_M (BIT(1)) TIMG_WDT_WKEY 0xFFFFFFFF DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) __FBSDID(x) DPORT_APP_SPI2_DMA_INT_MAP_S 0 DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) DEEPSLEEP_RESET SPI_USR_ADDR_BITLEN 0x0000003F DPORT_PRO_RWBLE_NMI_MAP_S 0 EFUSE_PGM_DONE_INT_ST_S 1 SPI_USR_MOSI_V 0x1 ESP_EARLY_LOGW(tag,format,...) if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) { ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 SPI_MASTER_CK_SEL_S 11 SPI_CS0_DIS_M (BIT(0)) DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) SPI_OUT_EOF_INT_CLR (BIT(7)) DPORT_SHROM_MPU_TABLE18 0x00000003 RTC_CNTL_ENB_SCK_XTAL_V 0x1 RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) EFUSE_RD_EFUSE_WR_DIS_S 0 SPI_SIO (BIT(16)) DPORT_APP_CMMU_PD_S 12 DPORT_PRO_WR_BAK_TO_READ_S 19 DPORT_TIMERGROUP_CLK_EN (BIT(13)) DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) TIMG_CLK_EN_M (BIT(31)) EFUSE_CHIP_VER_DIS_APP_CPU_S 0 SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C) DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) SPI_TRANS_DONE_V 0x1 RTC_CNTL_DBROWN_OUT_THRES_S 27 TWO_BYTE_STATUS_EN SPI_WRSR_2B DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F DPORT_TRACEMEM_MUX_MODE 0x00000003 ETS_TG0_LACT_EDGE_INTR_SOURCE 61 RTC_CNTL_SW_STALL_APPCPU_C1_S 20 DPORT_APP_IRAM0ADDR_IA_S 0 SPI_USR_MISO_DBITLEN 0x00FFFFFF DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) RTC_CNTL_RFRX_PBUS_PU_S 28 SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF XCHAL_DATAROM0_PADDR 0x3F400000 SPI_WR_BYTE_ORDER_V 0x1 _bss_start RTC_CNTL_BIAS_FORCE_SLEEP_S 15 CPU_CLK_FREQ APB_CLK_FREQ DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) EFUSE_RD_SDIO_TIEH_V 0x1 RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) SPI_INLINK_ADDR_V 0xFFFFF EXCCAUSE_EXCCAUSE_SHIFT 0 SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) FUNC_GPIO17_EMAC_CLK_OUT_180 5 BIT6 0x00000040 DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) SPI_OUT_DONE_INT_ST_V 0x1 ETS_TG0_T1_EDGE_INTR_SOURCE 59 _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; __asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" : "=a" (__tmp) : : "memory" ); }) DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110) DPORT_PRO_ROM_FO (BIT(0)) DPORT_SHROM_MPU_TABLE12 0x00000003 RTC_CNTL_FORCE_NOISO_M (BIT(5)) DPORT_IMMU_TABLE12_V 0x7F SPI_INLINK_DSCR_ERROR_INT_ST_S 2 BIT5 0x00000020 EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) SPI_MOSI_DELAY_MODE 0x00000003 DPORT_ACCESS_CHECK_PRO_S 0 __PTRDIFF_TYPE__ int XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 XCHAL_HAVE_TRAX 1 SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) EFUSE_BLK3_DOUT0_S 0 DPORT_PRO_TIMER_INT2_MAP 0x0000001F DPORT_APP_RWBT_IRQ_MAP_S 0 SPI_FLASH_READ_M (BIT(31)) SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) DPORT_PRO_UHCI1_INTR_MAP 0x0000001F DPORT_APP_CACHE_FLUSH_ENA_V 0x1 DPORT_APP_ROM_PD_S 1 DPORT_SHROM_MPU_TABLE23 0x00000003 DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) ESP_EARLY_LOGE(tag,format,...) if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) { ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } DPORT_DMMU_TABLE15_V 0x7F RTC_CNTL_WDT_INT_ST_V 0x1 RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 DPORT_APP_SPI_INTR_2_MAP_V 0x1F DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) SPI_T_PP_TIME 0x00000FFF DPORT_SPI2_DMA_CHAN_SEL 0x00000003 DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) EFUSE_BLK2_DIN3 0xFFFFFFFF EFUSE_BLK2_DOUT2_V 0xFFFFFFFF SPI_USR_WR_SRAM_DUMMY (BIT(3)) DR_REG_HINF_BASE 0x3ff4B000 DPORT_MASK_APP_IRAM_M (BIT(1)) DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) RTC_CNTL_FORCE_PD_M (BIT(30)) XCHAL_NUM_AREGS 64 SPI_IN_SUC_EOF_INT_CLR_V 0x1 SPI_FWRITE_QUAD_M (BIT(13)) _BSD_SIZE_T_DEFINED_ DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 _RAND48_MULT_1 (0xdeec) XCHAL_HAVE_VECTOR_SELECT 1 SPI_SRAM_DUMMY_CYCLELEN_V 0xFF RTC_CNTL_SCRATCH4_S 0 TIMG_LACT_INT_CLR_M (BIT(3)) EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) SPI_FASTRD_MODE_S 13 DPORT_ARB_IA_V 0x3 RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 DPORT_I2S1_CLK_EN (BIT(21)) TIMG_T1_ALARM_HI 0xFFFFFFFF SPI_T_ERASE_ENA_M (BIT(31)) RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 FUNC_MTCK_GPIO13 2 DPORT_PRO_CACHE_ENABLE (BIT(3)) SPI_SLV_WRSTA_CMD_VALUE_S 24 DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) DPORT_AHB_LITE_MASK_APPDPORT_S 10 DPORT_LPCLK_SEL_RTC_SLOW_S 24 DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F XCHAL_HAVE_HIFI4 0 RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 __INT_FAST8_TYPE__ int DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) EFUSE_BLK3_DIN0_S 0 DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) DPORT_AHB_LITE_SDHOST_PID_REG_S 11 XCHAL_INTLEVEL4_VECOFS 0x00000200 RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) load_partition_table DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) XCHAL_NUM_LOADSTORE_UNITS 1 SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C) SPI_SLV_RDATA_BIT_V 0xFFFFFF DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 XCHAL_DCACHE_WAYS 1 TIMG_LACT_INT_RAW_S 3 DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) CLK_OUT3_S 8 SPI_OUTLINK_STOP (BIT(28)) RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) XCHAL_INT18_EXTNUM 13 ESP_LOGD(tag,format,...) ESP_EARLY_LOGD(tag, format, ##__VA_ARGS__) SPI_BUFF_BYTE_WRITE_NUM 32 EFUSE_SDIO_DREFH_S 8 RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F DPORT_PRO_SPI_INTR_1_MAP_S 0 SPI_OUT_DONE_INT_ENA (BIT(6)) FUNC_GPIO34_GPIO34 2 __INT_FAST32_TYPE__ int RTC_CNTL_XTL_EXT_CTR_EN_S 31 ETS_FROM_CPU_INTR2_SOURCE 26 TIMG_T1_INT_ENA_S 1 RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) DPORT_APP_CACHE_MASK_DRAM1_V 0x1 SPI_FLASH_WRENABLE_FLAG BIT1 TIMG_WDT_STG1_HOLD 0xFFFFFFFF RTC_CNTL_PWC_FORCE_PD (BIT(18)) RTC_CNTL_ROM0_FORCE_PD_S 5 DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF RTC_CNTL_FORCE_NOISO_S 5 RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 DPORT_IMMU_TABLE12_S 0 SPI_AHBM_FIFO_RST (BIT(4)) DPORT_AHB_SPI_REQ_S 14 SPI_SLAVE_MODE_V 0x1 SPI_DMA_TX_EN_S 1 TIMG_T1_LOAD_S 0 TIMG_T0_LOAD_LO 0xFFFFFFFF SPI_FLASH_PER_V 0x1 DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) DR_REG_IO_MUX_BASE 0x3ff49000 SPI_BUF15_V 0xFFFFFFFF DPORT_SHROM_MPU_TABLE19_S 0 DPORT_SHROM_MPU_TABLE0 0x00000003 RTCWDT_SYS_RESET RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) DPORT_APP_RWBLE_IRQ_MAP 0x0000001F drom_size RTC_CNTL_WDT_INT_ST_M (BIT(3)) DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) ___int32_t_defined 1 uint32_t EFUSE_RD_CK8M_FREQ 0x000000FF _REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state) CLK_OUT1 0xf blocks RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) DPORT_APP_CACHE_IA_INT_MAP 0x0000001F REG_SET_BIT(_r,_b) (*(volatile uint32_t*)(_r) |= (_b)) DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) XCHAL_INT13_EXTNUM 10 TIMG_WDT_STG0 0x00000003 XCHAL_HAVE_FUSION_AVS 0 RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) SPI_TRANS_DONE (BIT(4)) SPI_BUF6_V 0xFFFFFFFF SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) LOG_COLOR_E LOG_COLOR(LOG_COLOR_RED) RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) cache_flash_mmu_set SPI_CACHE_FLASH_USR_CMD_S 2 GET_PERI_REG_MASK(reg,mask) (READ_PERI_REG(reg) & (mask)) SPI_OUT_DONE_INT_CLR (BIT(6)) RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 XCHAL_INT4_LEVEL 1 DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 SPI_FLASH_WRSR_S 26 RESET_REASON DPORT_DMMU_TABLE1_V 0x7F RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 SPI_DOUTDIN_S 0 SPI_CS2_DIS (BIT(2)) RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) ETS_SLC_INUM 1 DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) ETS_RSA_INTR_SOURCE 51 RTC_CNTL_SAR_INT_ST (BIT(5)) SPI_IN_ERR_EOF_INT_RAW_V 0x1 SPI_FREAD_QIO_M (BIT(24)) DPORT_SHARE_ROM_MPU_AD 0x00000003 XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF SPI_OUTLINK_START_S 29 DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) _ATEXIT_DYNAMIC_ALLOC 1 SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) DPORT_APP_SPI_INTR_0_MAP 0x0000001F RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) LOG_BOLD(COLOR) "\033[1;" COLOR "m" RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) SPI_FLASH_PES (BIT(17)) RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 EFUSE_PGM_DONE_INT_ENA_S 1 PERIPHS_SPI_FLASH_C7 SPI_W7(1) __ESP_ATTR_H__ SPI_MISO_DELAY_NUM 0x00000007 MESR_DME 0x00000002 RTC_CNTL_WDT_WKEY_S 0 XSR(reg,swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval)); XCHAL_EXTINT10_NUM 13 DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 SPI_FLASH_WRSR_M (BIT(26)) RTC_CNTL_ULP_CP_INT_ENA_S 5 FUNC_SD_CMD_GPIO11 2 DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF DPORT_PRO_I2S0_INT_MAP_V 0x1F DPORT_SRAM_PD_0_S 0 DR_REG_SARADC_BASE 0x3ff48800 SPI_SLV_WR_ST_S 0 DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) SPI_USR_DUMMY_HOLD_V 0x1 drom_load_addr DPORT_IMMU_TABLE15 0x0000007F SHRT_MAX __SHRT_MAX__ XCHAL_INT24_LEVEL 4 DPORT_APP_PWM3_INTR_MAP_V 0x1F __SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1) __CONCAT1(x,y) x ## y EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) DPORT_MASK_PRO_DRAM (BIT(2)) XCHAL_DATA_PIPE_DELAY 2 SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) FUNC_GPIO24_GPIO24 2 SPI_IN_RST_S 2 SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) DPORT_RECORD_APP_PDEBUGINST_S 0 __UINT_LEAST16_TYPE__ short unsigned int __SIZEOF_LONG_LONG__ 8 DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F _SOC_IO_MUX_REG_H_ DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) XCHAL_HAVE_SEXT 1 UINT16_MAX 65535 RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 SPI_FREAD_DUAL_M (BIT(14)) DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) TIMG_LACT_RTC_STEP_LEN_S 6 RTC_CNTL_ENB_CK8M_DIV_V 0x1 DPORT_PRO_SLAVE_WR_S 21 XCHAL_KERNEL_VECTOR_VADDR 0x40000300 XCHAL_DATARAM1_SIZE 4194304 EFUSE_BLK1_DIN2_S 0 ETS_SPI1_DMA_INTR_SOURCE 52 SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) DR_REG_I2S_BASE 0x3ff4F000 DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F SPI_FLASH_RDSR_M (BIT(27)) EFUSE_RD_ABS_DONE_1_M (BIT(5)) EFUSE_BLK1_DOUT7_V 0xFFFFFFFF MEMCTL_DCWU_SHIFT 8 DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF DPORT_WDG_CLK_EN (BIT(3)) EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF SPI_DMA_CONTINUE_V 0x1 FUNC_SD_DATA3_GPIO10 2 DPORT_AHB_ACCESS_DENY (BIT(8)) SPI_MISO_DELAY_NUM_S 18 EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) RTC_CNTL_DBIAS_WAK_S 25 EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) SPI_CS_HOLD_DELAY_RES_V 0xFFF PTRDIFF_MIN (-PTRDIFF_MAX - 1) DPORT_IMMU_TABLE6_S 0 XCHAL_KERNEL_VECOFS 0x00000300 DPORT_APP_ROM_FO_M (BIT(1)) DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F BIT20 0x00100000 DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) SPI_SLV_RD_ADDR_BITLEN_V 0x3F RTCWDT_CPU_RESET EFUSE_BLK1_DOUT4_S 0 RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 LOG_COLOR_V DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) SPI_FASTRD_MODE_V 0x1 RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) RTC_CNTL_WAKEUP_CAUSE_V 0x7FF _ROM_CACHE_H_ EXCCAUSE_ITLB_MULTIHIT 17 SPI_BUF14 0xFFFFFFFF PS_WOE PS_WOE_MASK CLEAR_PERI_REG_MASK(reg,mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) DPORT_DMMU_TABLE11_S 0 __UINT_FAST32_TYPE__ unsigned int EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) TIMG_T1_UPDATE_V 0xFFFFFFFF SPI_CS0_DIS_S 0 PART_SUBTYPE_OTA_MASK 0x0f XCHAL_HAVE_FP_DIV 1 XCHAL_NMILEVEL 7 RTC_CNTL_WDT_EN (BIT(31)) _ROM_RTC_H_ DPORT_PRO_AHB_SPI_REQ (BIT(12)) DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F DPORT_IMMU_TABLE5 0x0000007F RTC_CNTL_WIFI_PD_EN_V 0x1 RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 INTPTR_MAX PTRDIFF_MAX DBREAKC_LOADBREAK_SHIFT 30 __ATOMIC_ACQ_REL 4 DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 __IEEE_LITTLE_ENDIAN DPORT_PBUS_MEM_FORCE_PD (BIT(3)) DPORT_PCNT_RST (BIT(10)) RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) RTC_CNTL_CK8M_FORCE_PU (BIT(26)) DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) __int_least8_t_defined 1 DPORT_PRO_OUT_VECBASE_SEL_S 0 EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 RTC_CNTL_BBPLL_CAL_SLP_START_S 25 DPORT_APP_I2S0_INT_MAP_V 0x1F DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) TIMG_WDT_SYS_RESET_LENGTH_V 0x7 _Kmax (sizeof (size_t) << 3) EXCCAUSE_UNALIGNED 9 DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) __SIZEOF_LONG__ 4 EFUSE_CLK_EN_V 0x1 SPI_SLV_WR_RD_BUF_EN_V 0x1 EFUSE_CLK_SEL1 0x000000FF SPI_IN_DONE_INT_ENA_S 3 MESR_LCE_L DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) TIMG_T1_HI_S 0 RTC_CNTL_TOUCH_INT_ST_S 6 SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF XCHAL_RESET_VECTOR1_VADDR 0x40000400 XCHAL_HAVE_WINDOWED 1 DR_REG_EFUSE_BASE 0x3ff5A000 DPORT_DMMU_TABLE9_S 0 DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F __ATOMIC_ACQUIRE 2 strcmpi strcasecmp TIMG_T1_DIVIDER_V 0xFFFF TIMG_WDT_STG2 0x00000003 SPI_SLV_RDATA_BIT_S 0 DPORT_PRO_SLC0_INTR_MAP 0x0000001F secury_boot_flag DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) DPORT_PRO_INTRUSION_RECORD_S 0 SPI_DMA_CONTINUE_S 16 __INT_FAST32_MAX__ 2147483647 DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) BOOTLOADER_BUILD 1 INT_MIN (-INT_MAX - 1) EFUSE_BLK1_DIN4_S 0 LOG_COLOR_BROWN "33" DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) SPI_IN_SUC_EOF_INT_ST_S 5 RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34) RTC_CNTL_WDT_STG3_HOLD_S 0 EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) __weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym) MEMCTL_L0IBUF_EN_SHIFT 0 DEBUGCAUSE_IBREAK_MASK 0x02 ETS_I2C_EXT1_INTR_SOURCE 50 DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 DPORT_PRO_WDG_INT_MAP 0x0000001F SPI_USR_CMD_HOLD_V 0x1 DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S)) TIMG_WDT_EDGE_INT_EN_M (BIT(22)) SPI_OUT_DATA_BURST_EN (BIT(12)) SPI_CLK_EQU_SYSCLK_M (BIT(31)) SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 DPORT_ACCESS_CHECK_APP_S 8 DPORT_ACCESS_CHECK_PRO_M (BIT(0)) RTC_CNTL_XTL_FORCE_NOISO_V 0x1 PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) SPI_INLINK_START_M (BIT(29)) SPI_RD_BIT_ORDER_V 0x1 RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) DPORT_SHROM_MPU_TABLE6_S 0 EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) EFUSE_DATE 0xFFFFFFFF EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) XCHAL_NUM_XLMI 1 SPI_USR_ADDR_BITLEN_S 26 DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) DPORT_PERI_CLK_EN_S 0 DPORT_APP_ROM_FO (BIT(1)) ETS_SPI2_INTR_SOURCE 30 __have_longlong64 1 _N_LISTS 30 DR_REG_RTCMEM1_BASE 0x3ff62000 RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) EFUSE_RD_CK8M_FREQ_S 0 DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) RTC_CNTL_CK8M_FORCE_PD (BIT(25)) DBREAKC_LOADBREAK_MASK 0x40000000 DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) VALUE_SET_FIELD(_r,_f,_v) ((_r)=(((_r) & ~((_f) << (_f ##_S)))|((_v)<<(_f ##_S)))) SPI_SLV_WRSTA_CMD_VALUE_V 0xFF TIMG_RTC_CALI_RDY_M (BIT(15)) DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c) DPORT_DMMU_TABLE11_V 0x7F RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 ETS_I2S0_INTR_SOURCE 32 INTPTR_MIN PTRDIFF_MIN DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 DPORT_TRACEMEM_MUX_MODE_V 0x3 TIMG_T1_INT_CLR_S 1 RTC_CNTL_FASTMEM_FORCE_PU_S 13 RTC_CNTL_PLL_FORCE_ISO_S 24 __USER_LABEL_PREFIX__ XCHAL_PROFILING_INTERRUPT 11 DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) DPORT_MASK_APP_DRAM_S 3 TIMG_T0_HI_S 0 DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF XCHAL_HAVE_HALT 0 __SIZEOF_WCHAR_T__ 2 DPORT_PRO_TIMER_INT2_MAP_V 0x1F RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) __UINT_LEAST64_TYPE__ long long unsigned int XCHAL_DATARAM0_BANKS 1 __SIZEOF_WINT_T__ 4 SPI_OUT_DONE_INT_RAW_V 0x1 SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) ETS_WBB_INUM 4 RTC_CNTL_RST_BIAS_I2C_S 31 RTC_CNTL_SLP_REJECT (BIT(30)) DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 XCHAL_HAVE_ABSOLUTE_LITERALS 0 RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) EFUSE_RD_SDIO_DREFH 0x00000003 XCHAL_EXTINT1_NUM 1 EFUSE_BLK2_DIN4 0xFFFFFFFF INT_LEAST8_MIN -128 FUNC_GPIO5_VSPICS0 1 XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL _BSD_SIZE_T_ SPI_INT_EN 0x0000001F DPORT_IMMU_TABLE14_V 0x7F /home/gus/esp/32/idf/components/bootloader/src/main/./bootloader_start.c XCHAL_HAVE_FP_RSQRT 1 EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) SPI_INDSCR_BURST_EN_S 11 DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) __DOTS , ... EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) esp_log_timestamp SPI_OUT_LOOP_TEST_V 0x1 RTC_CNTL_DBOOST_FORCE_PU_S 29 SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) RTC_MEM_CRC_LEN_V (0x7ff) DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) PS_WOE_MASK 0x00040000 DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) MEMCTL_DCWA_MASK 0x0003E000 SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) XCHAL_RESET_VECTOR0_VADDR 0x50000000 SPI_FWRITE_QIO_S 15 EFUSE_BLK3_DOUT7_S 0 DPORT_APP_CAN_INT_MAP_S 0 EFUSE_READ_DONE_INT_ST_M (BIT(0)) DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF DPORT_PRO_INTRUSION_RECORD 0x0000000F RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) RTC_CNTL_FORCE_ISO_M (BIT(4)) DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 DPORT_PRO_PWM0_INTR_MAP_V 0x1F DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) RTC_CNTL_ROM0_PD_EN (BIT(24)) DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_TOUCH_INT_ENA_S 6 RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) SPI_DMA_OUTLINK_DSCR_BF1_S 0 drom_addr ETS_PWM0_INTR_SOURCE 39 DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) EXCCAUSE_CP6_DISABLED 38 EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) FUNC_GPIO2_GPIO2_0 0 DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF INT_LEAST8_MAX 127 DPORT_PBUS_MEM_FORCE_PU_S 2 LONG_LONG_MIN SPI_USR_DIN_HOLD_M (BIT(19)) FUN_DRV_S 10 DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) XCHAL_INT7_LEVEL 1 FUNC_GPIO35_GPIO35 2 DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 DPORT_DMMU_TABLE6 0x0000007F TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S)) SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) DPORT_AHBLITE_IA_S 10 SPI_SEC_SIZE 0x1000 DPORT_APP_DRAM_SPLIT_M (BIT(11)) DPORT_PWM2_RST (BIT(25)) DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) entry SPI_SRAM_RSTIO_V 0x1 CLK_OUT3 0xf XCHAL_HAVE_BSP3 0 DPORT_APP_CACHE_MODE_S 2 PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90) RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) SPI_IN_ERR_EOF_INT_ST (BIT(4)) SPI_INLINK_RESTART_V 0x1 XCHAL_INT2_EXTNUM 2 SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) FUNC_GPIO18_VSPICLK 1 RTC_CNTL_ENB_CK8M_V 0x1 EFUSE_BLK3_DIN7_S 0 DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) _RAND48_SEED_2 (0x1234) EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) EFUSE_SDIO_TIEH (BIT(15)) SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100) EFUSE_BLK2_DOUT1 0xFFFFFFFF EXCCAUSE_LOAD_STORE_RING 26 EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 _RAND48_MULT_2 (0x0005) DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F DPORT_PBUS_MEM_FORCE_PU_V 0x1 SPI_DMA_OUT_STATUS 0xFFFFFFFF TIMG_T1_INT_CLR_V 0x1 SPI_BUF9 0xFFFFFFFF EFUSE_SDIO_FORCE (BIT(16)) XCHAL_WINDOW_VECTORS_VADDR 0x40000000 DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 DPORT_AHB_LITE_MASK_SDIO_S 8 FUNC_GPIO18_GPIO18_0 0 SPI_TX_CRC_DATA_S 0 RTC_CNTL_WDT_INT_ST (BIT(3)) EFUSE_PGM_DONE_INT_RAW_S 1 DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 TIMG_T0_LOAD_LO_S 0 DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF DPORT_APP_I2S0_INT_MAP_S 0 DPORT_APP_OUT_VECBASE_REG 0x003FFFFF DPORT_SRAM_PD_0_V 0xFFFFFFFF XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF ETS_RWBT_NMI_SOURCE 8 DPORT_APP_TRACEMEM_ENA_M (BIT(0)) RTC_CNTL_FASTMEM_FORCE_LPU_S 8 RTC_CNTL_TOUCH_INT_CLR_S 6 EXCCAUSE_CP4_DISABLED 36 XCHAL_INT27_LEVEL 3 MESR_MEMTYPE_SHIFT 24 SPI_CK_I_EDGE_V 0x1 RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) XCHAL_TIMER2_INTERRUPT 16 INT_MIN RTC_CNTL_FORCE_PU_M (BIT(31)) EXCCAUSE_CP0_DISABLED 32 DPORT_APP_CACHE_MASK_IRAM0_S 0 XCHAL_INT30_LEVEL 4 TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF XCHAL_TRAX_TIME_WIDTH 0 PS_OWB_MASK 0x00000F00 _NOINLINE_STATIC _NOINLINE static SPI_OUT_EOF_MODE_M (BIT(9)) RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 DPORT_PRO_MMU_IA_INT_MAP_S 0 DPORT_APP_UART1_INTR_MAP_S 0 PARTITION_ADD 0x4000 SPI_BUF3_V 0xFFFFFFFF SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) SPI_USR_DUMMY_CYCLELEN_V 0xFF RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) XCHAL_HAVE_XEA1 0 DPORT_PBUS_MEM_FORCE_PD_S 3 DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F PERIPHS_SPI_FLASH_C6 SPI_W6(1) XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) SPI_USR_ADDR_BITLEN_V 0x3F EFUSE_FORCE_NO_WR_RD_DIS_S 16 DPORT_DMMU_TABLE14 0x0000007F SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 __FLT_HAS_QUIET_NAN__ 1 DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) SPI_OUT_EOF_INT_CLR_S 7 DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) SPI_AHBM_RST_S 5 RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 EFUSE_OP_CODE_S 0 EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) TIMG_T1_EN_V 0x1 DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 RTC_CNTL_SLOWMEM_PD_EN_S 17 RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 SPI_FREAD_QIO_V 0x1 SPI_BUF12_V 0xFFFFFFFF SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) SPI_WAIT_FLASH_IDLE_EN_V 0x1 EFUSE_BLK1_DIN7_V 0xFFFFFFFF SPI_SLV_WR_BUF_DONE_V 0x1 DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) XCHAL_HW_REL_LX6 1 RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 EFUSE_PGM_DONE_INT_RAW_V 0x1 RTC_CNTL_SDIO_IDLE_INT_ST_S 2 DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) SPI_SLV_WRBUF_CMD_VALUE_S 8 EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) __lock_init_recursive(lock) (_CAST_VOID 0) TIMG_LACT_LOAD_S 0 DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 VALUE_GET_FIELD2(_r,_f) (((_r) & (_f))>> (_f ##_S)) __DEC128_MAX_EXP__ 6145 DPORT_PRO_RWBT_IRQ_MAP_V 0x1F FUNC_GPIO25_GPIO25 2 DPORT_MASK_PRO_DRAM_M (BIT(2)) SPI_FLASH_READ_V 0x1 DPORT_APP_CACHE_LOCK_1_EN_S 7 _SYS_SIZE_T_H FUNC_GPIO2_SD_DATA0 4 SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 DR_REG_SDMMC_BASE 0x3ff68000 DPORT_PRO_OUT_VECBASE_SEL 0x00000003 __DEC32_EPSILON__ 1E-6DF DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) FUNC_MTMS_HSPICLK 1 DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF SPI_SLV_WR_BUF_DONE (BIT(1)) va_start(v,l) __builtin_va_start(v,l) DPORT_RECORD_PRO_PDEBUGINST_S 0 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F FUNC_SD_DATA0_HS1_DATA0 3 DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF DPORT_APP_MAC_NMI_MAP_S 0 SPI_DMA_TX_EN (BIT(1)) RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) EFUSE_CLK_SEL0_V 0xFF DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) RTC_CNTL_SLP_VAL_HI_S 0 DPORT_APP_CACHE_MASK_IROM0_V 0x1 ETS_I2S1_INTR_SOURCE 33 DPORT_TIMERGROUP1_RST (BIT(15)) SPI_USR_PREP_HOLD (BIT(23)) EFUSE_SDIO_DREFM_S 10 DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF XCHAL_DCACHE_LINEWIDTH 2 ETS_SPI3_DMA_INTR_SOURCE 54 RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) XCHAL_EXTINT8_NUM 10 EFUSE_BLK3_DOUT7_V 0xFFFFFFFF _EXFUN(name,proto) name proto DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) DPORT_PCNT_CLK_EN (BIT(10)) SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF RTC_CNTL_WAKEUP_ENA 0x000007FF EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 TIMG_T0_ALARM_LO_V 0xFFFFFFFF TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) EFUSE_BLK1_DOUT4_V 0xFFFFFFFF RTC_CNTL_TIME_LO_S 0 SPI_SRAM_DUMMY_CYCLELEN 0x000000FF __INTPTR_MAX__ 2147483647 __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) DPORT_APP_MMU_IA_INT_MAP_S 0 DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F TIMG_WDT_CLK_PRESCALE 0x0000FFFF DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 FUNC_MTCK_HS2_DATA3 3 SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) DPORT_ROM_MPU_TABLE0 0x00000003 DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) DPORT_APPCPU_RESETTING_M (BIT(0)) SPI_SLV_STATUS_FAST_EN (BIT(26)) DR_REG_BT_BASE 0x3ff51000 DPORT_PRO_LEDC_INT_MAP_V 0x1F DPORT_PWM3_RST (BIT(26)) RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) DPORT_APPCPU_CLKGATE_EN_V 0x1 DPORT_I2C_EXT1_RST (BIT(18)) SPI_USR_SRAM_DIO_V 0x1 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) secure_boot DPORT_PRO_INTRUSION_RECORD_V 0xF RTC_MEM_CRC_FINISH_S (31) EFUSE_BLK3_DIN6_V 0xFFFFFFFF RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) RTC_CNTL_INTER_RAM0_PD_EN_S 25 RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF PERIPHS_SPI_FLASH_C5 SPI_W5(1) DPORT_APP_RWBT_NMI_MAP 0x0000001F DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) SPI_DMA_IN_STATUS_S 0 MESR_INSEXC_SHIFT 11 SPI_FLASH_HPM_S 19 RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) __WCHAR_MAX__ 65535 DPORT_PRO_AHB_SPI_REQ_S 12 RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) SPI_USR_RD_SRAM_DUMMY_V 0x1 TIMG_WDT_SYS_RESET_LENGTH_S 15 SPI_FLASH_BP0 BIT2 XCHAL_HAVE_DEBUG_JTAG 1 XCHAL_HAVE_PTP_MMU 0 DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148) CONFIG_ESPTOOLPY_FLASHFREQ "40m" RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 DPORT_APP_RTC_CORE_INTR_MAP_S 0 WDT_CLK_FREQ APB_CLK_FREQ DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF RTC_CNTL_DG_WRAP_FORCE_PU_S 20 BIT18 0x00040000 unpack_load_app DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 XCHAL_HAVE_MX 0 DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) DPORT_SHROM_MPU_TABLE13_S 0 RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) SPI_IN_SUC_EOF_INT_ST (BIT(5)) ETS_RWBLE_INTR_SOURCE 7 SPI_FLASH_RESULT_OK DPORT_MASK_APP_DRAM (BIT(3)) EFUSE_BLK1_DOUT0 0xFFFFFFFF EXT_CPU_RESET SPI_WB_MODE_S 16 SPI_CS_HOLD_M (BIT(4)) XCHAL_HAVE_HIFI3_VFPU 0 DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF __SIZE_TYPE__ unsigned int DPORT_IMMU_TABLE11_S 0 DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) DPORT_AHB_ACCESS_DENY_M (BIT(8)) RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) TIMG_T1_INT_RAW_M (BIT(1)) DPORT_PRO_TIMER_INT2_MAP_S 0 XCHAL_HAVE_PIF_REQ_ATTR 0 DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 RTC_CNTL_CK8M_DFREQ_S 17 EFUSE_BLK2_DIN5 0xFFFFFFFF DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF __FLT_HAS_DENORM__ 1 SPI_FLASH_WREN_S 30 RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) DPORT_MASK_APP_DRAM_M (BIT(3)) RTC_MEM_CRC_START_S (8) RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 RTC_CNTL_POWERUP_TIMER_S 9 SPI_FREAD_QUAD_V 0x1 DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F XCHAL_ICACHE_ECC_PARITY 0 RTC_CNTL_DBIAS_SLP_V 0x7 RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 __DBL_EPSILON__ ((double)2.2204460492503131e-16L) RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) SPI0_R_QIO_DUMMY_CYCLELEN 3 EFUSE_BLK2_DIN5_V 0xFFFFFFFF DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 RTC_CNTL_CK8M_DIV_V 0x3 FUNC_GPIO21_GPIO21_0 0 DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) DPORT_APP_CACHE_MASK_IRAM1_V 0x1 SPI_IN_DONE_INT_CLR_M (BIT(3)) EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) DPORT_SPI_RST_2 (BIT(6)) EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) SPI_OUTLINK_START (BIT(29)) DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) FUNC_SD_CMD_HS1_CMD 3 EFUSE_PGM_CMD_M (BIT(1)) EFUSE_READ_DONE_INT_CLR_M (BIT(0)) DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) SPI_BUF13 0xFFFFFFFF DPORT_ACCESS_CHECK_APP (BIT(8)) SPI_STATUS_EXT_V 0xFF MALLOC_ALIGNMENT ((XCHAL_DATA_WIDTH) < 16 ? 16 : (XCHAL_DATA_WIDTH)) DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) DPORT_APP_OUT_VECBASE_REG_S 0 DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) RTC_CNTL_SENSE3_HOLD_FORCE_S 6 EFUSE_RD_INST_CONFIG_S 20 DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) app_count RTC_MEM_CRC_LEN_S (20) XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 XCHAL_EXTINT12_NUM 17 SPI_USR_DUMMY_IDLE_M (BIT(26)) RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) XCHAL_HAVE_MIMIC_CACHEATTR 1 DPORT_PBUS_MEM_FORCE_PU (BIT(2)) __FLT_MAX__ 3.4028234663852886e+38F PERIPHS_SPI_FLASH_C4 SPI_W4(1) TIMG_T0_AUTORELOAD_S 29 TIMG_WDT_INT_CLR (BIT(2)) RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 DPORT_SPI_DMA_RST (BIT(22)) __INT_LEAST16_MAX__ 32767 RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) SPI_USR_DIN_HOLD (BIT(19)) SPI_OUT_TOTAL_EOF_INT_ST_S 8 SPI_SYNC_RESET_S 31 DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) print_flash_info EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) EFUSE_BLK1_DIN1 0xFFFFFFFF TIMG_WDT_STG3_HOLD 0xFFFFFFFF DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) SPI_SLV_RD_BUF_DONE_S 0 XCHAL_RESET_VECTOR_PADDR 0x40000400 BIT7 0x00000080 DPORT_SHROM_MPU_TABLE2 0x00000003 SPI_BUF15_S 0 FUNC_SD_DATA1_HS1_DATA1 3 DPORT_BT_LPCK_DIV_B_V 0xFFF RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) DPORT_FAST_CLK_RTC_SEL_S 3 RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30) DPORT_DMMU_TABLE3_V 0x7F TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F DPORT_APP_RX_END_V 0x1 SPI_SPEED_40M SPI_SIO_S 16 EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) XCHAL_TRAX_MEM_SHAREABLE 1 RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 FUNC_SD_CMD_U1RTS 4 __SIZEOF_LONG_DOUBLE__ 8 SPI_USR_DUMMY_CYCLELEN 0x000000FF SPI_CLKCNT_H_V 0x3F EFUSE_BLK1_DIN4_V 0xFFFFFFFF DPORT_SLAVE_REQ_V 0x1 RTC_CNTL_WDT_INT_CLR_M (BIT(3)) DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 XTENSA_COREBITS_H DPORT_APP_TIMER_INT2_MAP_S 0 DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) NL_ARGMAX 32 DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) SPI_USR_ADDR_HOLD_S 21 DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) SPI_USR_MOSI_HIGHPART_S 25 DPORT_MMU_IA_INT_EN_V 0xFFFFFF DPORT_PRO_SPI_INTR_0_MAP_V 0x1F RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 DPORT_DMMU_TABLE5_S 0 SET_PERI_REG_MASK(reg,mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) DPORT_APP_WDG_INT_MAP_S 0 SPI_IN_ERR_EOF_INT_ST_S 4 __UINT_FAST8_MAX__ 4294967295U DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F RTC_MEM_CRC_START_V 0x1 DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) _ELIDABLE_INLINE static __inline__ SPI_WP_REG_M (BIT(21)) SPI_USR_SRAM_QIO_S 2 DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F DPORT_BT_LPCK_DIV_A 0x00000FFF MESR_ERRTEST_SHIFT 9 PS_CALLINC_SHIFT 16 XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F RTC_CNTL_SCK_DCAP 0x000000FF DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) __REGISTER_PREFIX__ entry_addr TIMG_T1_EDGE_INT_EN_V 0x1 XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) DPORT_PRO_LEDC_INT_MAP_S 0 DPORT_APP_BB_INT_MAP_S 0 load_part_pos /home/gus/esp/32/idf-template/build/bootloader/main DPORT_RECORD_APP_PID_V 0x7 RTC_CNTL_WDT_STG0_S 28 SPI_CACHE_USR_CMD_4BYTE_S 1 TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088) RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) XCHAL_INSTRAM1_VADDR 0x40400000 DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) RTC_IRAM_LOW 0x400C0000 DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) SPI_CS_HOLD_DELAY_RES_S 16 DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F EFUSE_BLK1_DOUT2_S 0 DPORT_APPCPU_RESETTING (BIT(0)) DR_REG_PWM2_BASE 0x3ff6F000 XCHAL_INT10_EXTNUM 8 DPORT_APP_SLC1_INTR_MAP 0x0000001F XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) SPI_CK_OUT_LOW_MODE_V 0xF INT_FAST32_MIN (-__STDINT_EXP(INT_MAX)-1) EFUSE_RD_ABS_DONE_0_S 4 DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F DPORT_APP_CPU_RECORDING_S 0 DPORT_PRO_ROM_MPU_AD_M (BIT(0)) DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084) RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) DPORT_PRO_INTR_STATUS_1_S 0 RTC_CNTL_WDT_LEVEL_INT_EN_S 17 RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F __THROW RTC_CNTL_WDT_INT_ENA_V 0x1 DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 XCHAL_HAVE_SSP16 0 DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) FUNC_GPIO16_GPIO16 2 SPI_OUTLINK_RESTART (BIT(30)) DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) _REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf) RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) DPORT_IMMU_TABLE7 0x0000007F XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 XCHAL_HAVE_FUSION_LOW_POWER 0 SPI_SIZE_4MB TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4) DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F DPORT_APP_UART_INTR_MAP_S 0 SPI_SLV_LAST_COMMAND 0x00000007 DPORT_APP_CPU_RECORDING_M (BIT(0)) RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) XCHAL_DATARAM1_VADDR 0x3F800000 DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F EFUSE_RD_CODING_SCHEME 0x00000003 DPORT_APP_CACHE_IA 0x0000003F DPORT_APP_CACHE_FLUSH_DONE_V 0x1 RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) EXCCAUSE_INSTR_ERROR 2 DPORT_SHROM_MPU_TABLE12_V 0x3 EFUSE_DEC_WARNINGS_V 0xFFF DPORT_APP_PCNT_INTR_MAP 0x0000001F RTC_CNTL_DREFL_SDIO_S 25 PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74) SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) EFUSE_PGM_CMD (BIT(1)) FUNC_SD_DATA2_HS1_DATA2 3 DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0) DPORT_PRO_BOOT_REMAP_S 0 EFUSE_BLK2_DIN6_S 0 XCHAL_NMI_INTERRUPT 14 SPI_BUF0 0xFFFFFFFF EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) __WCHAR_TYPE__ short unsigned int SPI_IN_ERR_EOF_INT_ENA_S 4 RTC_CNTL_SCRATCH6 0xFFFFFFFF SPI_USR_COMMAND_VALUE 0x0000FFFF DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) SPI_USR_HOLD_POL_M (BIT(17)) EFUSE_BLK2_DOUT5_S 0 DPORT_INTERNAL_SRAM_IA 0x00000FFF DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 DPORT_PRO_ROM_IA (BIT(1)) DPORT_SHROM_MPU_TABLE22_S 0 DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) XCHAL_DATARAM0_PADDR 0x3FF80000 Cache_Read_Enable DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) DPORT_SHROM_MPU_TABLE0_S 0 SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40) RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) TIMG_RTC_CALI_START_V 0x1 RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) _REENT_CHECK_MP(ptr) XCHAL_NUM_DATARAM 2 SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) FUNC_SD_DATA1_SD_DATA1 0 EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F DPORT_MASK_APP_IRAM_V 0x1 DPORT_APP_TIMER_INT1_MAP 0x0000001F DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF DPORT_SW_BOOTLOADER_SEL_S 0 _REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf) RTC_CNTL_SAR_INT_CLR_S 5 __DEC128_MIN__ 1E-6143DL RTC_CNTL_SENSE1_HOLD_FORCE_S 4 DPORT_SPI2_DMA_CHAN_SEL_V 0x3 RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) RTC_CNTL_SAR_INT_CLR_M (BIT(5)) DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) EXCCAUSE_PRIVILEGED 8 DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F _WCHAR_T_DEFINED __need_wchar_t _T_WCHAR_ _WCHAR_T_DEFINED_ ets_secure_boot_obtain _T_PTRDIFF_ _WCHAR_T_DECLARED ets_secure_boot_hash ___int_ptrdiff_t_h ets_secure_boot_rd_iv LOCAL static _BSD_PTRDIFF_T_ _STDDEF_H_ CONFIG_ESPTOOLPY_BAUD_230400B 1 offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) _ROM_SECURE_BOOT_H_ ASSERT(x) do { if (!(x)) { printf("%s %u\n", __FILE__, __LINE__); while (1) { asm volatile("nop"); }; } } while (0) _BSD_WCHAR_T_ /home/gus/esp/32/idf/components/bootloader/src/main/./secure_boot.c __WCHAR_T__ _ANSI_STDDEF_H container_of(ptr,type,member) ({ const typeof( ((type *)0)->member ) *__mptr = (ptr); (type *)( (char *)__mptr - __offsetof(type,member) );}) __INT_WCHAR_T_H spiRet ets_secure_boot_finish __ESP_TYPES_H__ howmany(x,y) (((x)+((y)-1))/(y)) INLINE __inline__ __wchar_t__ __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) secure_boot_generate ets_secure_boot_rd_abstract CONFIG_ESPTOOLPY_COMPRESSED 1 ets_secure_boot_start _BSD_WCHAR_T_ _GCC_WCHAR_T __need_ptrdiff_t __ATTRIB_NORETURN __attribute__ ((noreturn)) __ATTRIB_ALIGN(x) __attribute__ ((aligned((x)))) _GCC_PTRDIFF_T __PTRDIFF_T __WCHAR_T _T_PTRDIFF __ATTRIB_PACK __attribute__ ((packed)) ___int_wchar_t_h CONFIG_ESPTOOLPY_BAUD 230400 _T_WCHAR SPIRead bitcount flash_crypt_cnt flash_encrypt_write SPI_Encrypt_Write /home/gus/esp/32/idf/components/bootloader/src/main/./flash_encrypt.c XTHAL_DCACHE_PREFETCH_L1_OFF 0x90000000 XCHAL_CA_RX (0xD0 | 0x40000000) XTHAL_FAM_CACHED 0x006 __SWID 0x2000 XTHAL_REL_GE(maja,mina,majb,minb) ((maja) > (majb) || ((maja) == (majb) && (mina) >= (minb))) _SYS_TYPES_H XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE) SEEK_SET 0 XTHAL_DISASM_OPT_OPHEX 0x0002 XTHAL_AMB_GUARD 5 XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR XTHAL_AMB_ALLOCATE 2 __need_inttypes fropen(__cookie,__fn) funopen(__cookie, __fn, (int (*)())0, (fpos_t (*)())0, (int (*)())0) XTHAL_MAX_INTERRUPTS 32 _ST_INT32 stdin (_REENT->_stdin) __sfeof(p) (((p)->_flags & __SEOF) != 0) XTHAL_MEMEP_F_CORRECTABLE 16 XTHAL_FAM_EXCEPTION 0x001 XTHAL_LAM_CACHED_NOALLOC 0x002 __need___va_list XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED stderr (_REENT->_stderr) XTHAL_REL_LE(maja,mina,majb,minb) ((maja) < (majb) || ((maja) == (majb) && (mina) <= (minb))) XTHAL_ICACHE_PREFETCH_MEDIUM XTHAL_ICACHE_PREFETCH(5) XTHAL_REL_GT(maja,mina,majb,minb) ((maja) > (majb) || ((maja) == (majb) && (mina) > (minb))) feof(p) __sfeof(p) __sferror(p) (((p)->_flags & __SERR) != 0) XTHAL_SAM_BYPASS 0x028 __SMBF 0x0080 XTHAL_MEMEP_F_DCACHE_TAG 5 XTHAL_LAM_BYPASS 0x000 XTHAL_FAM_BYPASS 0x000 L_cuserid 9 SEEK_END 2 _NEWLIB_STDIO_H __timespec_defined XTHAL_INTTYPE_PROFILING 7 XTHAL_REL_11_0_3 1 XCHAL_ADDRESS_MISALIGNED -1 XTHAL_MAYBE -1 XTHAL_INTTYPE_SOFTWARE 1 XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE) XCHAL_CA_RW (0xE0 | 0x40000000) XTHAL_SAM_EXCEPTION 0x001 SEEK_CUR 1 XTHAL_DCACHE_PREFETCH_LOW XTHAL_DCACHE_PREFETCH(4) XTHAL_LAM_BYPASSG 0x020 FD_SETSIZE 64 XTHAL_AMB_COHERENT 6 _MACHTYPES_H_ XTHAL_MAX_CPS 8 getchar() getc(stdin) XTHAL_INTTYPE_TIMER 4 XTHAL_SAM_WRITEBACK 0x026 XTHAL_PREFETCH_DISABLE 0xFFFF0000 XTHAL_DCACHE_PREFETCH_L1 0x90001000 XTHAL_NO_MAPPING -6 putchar(x) putc(x, stdout) XTHAL_MEMEP_F_ICACHE_DATA 6 __sputc_r(__ptr,__c,__p) __sputc_raw_r(__ptr, __c, __p) XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE) XTHAL_SAM_COHWRITEBACK 0x066 putc(x,fp) __sputc_r(_REENT, x, fp) XTHAL_INTTYPE_UNCONFIGURED 0 _CLOCK_T_ unsigned long XTHAL_MEMEP_F_LOCAL 0 XTHAL_MINOR_REV XTHAL_RELEASE_MINOR L_tmpnam FILENAME_MAX __SOFF 0x1000 XTHAL_PAM_BYPASS_BUF 0x010 __SL64 0x8000 XTHAL_RELEASE_NAME "11.0.3" __MS_types__ alloca(size) __builtin_alloca(size) _stderr_r(x) ((x)->_stderr) /home/gus/esp/32/idf/components/log/./log.c __VALIST __gnuc_va_list __SLBF 0x0001 xthal_set_cache_prefetch xthal_set_cache_prefetch_long XTHAL_MAX_INTTYPES 8 __SRW 0x0010 __SAPP 0x0100 __SNPT 0x0800 __SERR 0x0040 xthal_set_cache_prefetch_nw xthal_set_cache_prefetch_long_nw XTHAL_ICACHE_PREFETCH_OFF XTHAL_ICACHE_PREFETCH(0) XTHAL_LAM_CACHED 0x006 XTHAL_DISASM_BUFSIZE 80 XTHAL_CAFLAG_NO_AUTO_WB 0x000800 _XTHAL_PREFETCH_BLOCKS(n) ((n)<0?0:(n)<5?(n):(n)<15?((n)>>1)+2:9) XTHAL_CAFLAG_NO_AUTO_INV 0x001000 __sgetc_raw_r(__ptr,__f) (--(__f)->_r < 0 ? __srget_r(__ptr, __f) : (int)(*(__f)->_p++)) ferror(p) __sferror(p) __SRD 0x0004 XTHAL_CAFLAG_EXACT 0x000200 XTHAL_AMB_EXCEPTION 0 getc(fp) __sgetc_r(_REENT, fp) _funlockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_release_recursive((fp)->_lock)) XTHAL_PAM_BYPASS 0x000 XCHAL_UNSUPPORTED_ON_THIS_ARCH -4 XTHAL_SAM_WRITEBACK_NOALLOC 0x022 RAND_MAX __RAND_MAX XTHAL_ICACHE_PREFETCH_L1_OFF 0xA0000000 XTHAL_MEMEP_ECC 2 __timer_t_defined XTHAL_MEMEP_F_ICACHE_TAG 7 XTHAL_LAM_COHCACHED 0x046 XTHAL_DISASM_OPT_ALL 0x0FFF _IOFBF 0 fast_putc(x,p) (--(p)->_w < 0 ? __swbuf_r(_REENT, (int)(x), p) == EOF : (*(p)->_p = (x), (p)->_p++, 0)) XTHAL_MEMEP_F_DCACHE_DATA 4 __need_wchar_t XCHAL_CA_RWX (0xF0 | 0x40000000) XTHAL_MAX_TIMERS 4 MB_CUR_MAX __locale_mb_cur_max() __clock_t_defined assert XTHAL_RELEASE_MAJOR 11000 XTHAL_PREFETCH_BLOCKS(n) (0x0000000F80000000ULL + (((unsigned long long)_XTHAL_PREFETCH_BLOCKS(n))<<48)) XTHAL_ICACHE_PREFETCH(n) (0x80F00000+(((n)&0xF)<<4)) XTHAL_LITTLEENDIAN 0 _ST_INT32 __attribute__ ((__mode__ (__SI__))) XTHAL_LAM_NACACHED XTHAL_LAM_CACHED_NOALLOC clearerr(p) __sclearerr(p) XTHAL_PAM_WRITETHRU 0x0B0 XCHAL_NO_PAGES_MAPPED -5 __SEOF 0x0020 XTHAL_PAM_WRITEBACK_NOALLOC 0x0F0 NFDBITS (sizeof (fd_mask) * NBBY) XTHAL_LAM_NACACHEDG 0x022 alloca xthal_get_ccount XTHAL_DISASM_OPT_OPCODE 0x0004 FILENAME_MAX 1024 XTHAL_DISASM_OPT_PARMS 0x0008 XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE) XTHAL_ICACHE_PREFETCH_HIGH XTHAL_ICACHE_PREFETCH(8) XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD) XTHAL_DCACHE_PREFETCH(n) (0x800F0000+((n)&0xF)) /home/gus/esp/32/idf-template/build/bootloader/log XTENSA_HAL_H _IOLBF 1 __time_t_defined XTHAL_DCACHE_PREFETCH_MEDIUM XTHAL_DCACHE_PREFETCH(5) _TIMER_T_ unsigned long __sputc_raw_r(__ptr,__c,__p) (--(__p)->_w < 0 ? (__p)->_w >= (__p)->_lbfsize ? (*(__p)->_p = (__c)), *(__p)->_p != '\n' ? (int)*(__p)->_p++ : __swbuf_r(__ptr, '\n', __p) : __swbuf_r(__ptr, (int)(__c), __p) : (*(__p)->_p = (__c), (int)*(__p)->_p++)) XTHAL_ICACHE_PREFETCH_LOW XTHAL_ICACHE_PREFETCH(4) __SNBF 0x0002 __ASSERT_FUNC __func__ XTHAL_RELEASE_MINOR 3 XTHAL_REL_11_0 1 __SSTR 0x0200 XTHAL_AMB_HITCACHE 1 _IONBF 2 _stdout_r(x) ((x)->_stdout) physadr physadr_t __sgetc_r(__ptr,__p) __sgetc_raw_r(__ptr, __p) XTHAL_INTTYPE_EXTERN_LEVEL 3 __SOPT 0x0400 XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT) XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION) XTHAL_MEMEP_PARITY 1 TMP_MAX 26 XTHAL_LAM_ISOLATE 0x012 XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE) _FSTDIO XCHAL_SUCCESS 0 XTHAL_PAM_CACHED_NOALLOC 0x030 __SORD 0x2000 XTHAL_MAX_INTLEVELS 16 _STDIO_H_ assert(__e) ((__e) ? (void)0 : __assert_func (__FILE__, __LINE__, __ASSERT_FUNC, #__e)) XTHAL_BIGENDIAN 1 XTHAL_PREFETCH_ENABLE -1 XTHAL_CAFLAG_NO_PARTIAL 0x000400 stdout (_REENT->_stdout) FD_ZERO(p) (__extension__ (void)({ size_t __i; char *__tmp = (char *)p; for (__i = 0; __i < sizeof (*(p)); ++__i) *__tmp++ = 0; })) XTHAL_LAM_EXCEPTION 0x001 fd_set _types_fd_set XTHAL_AMB_WRITETHRU 3 FOPEN_MAX 20 XTHAL_PAM_WRITEBACK 0x1F0 XTHAL_INTTYPE_EXTERN_EDGE 2 __sclearerr(p) ((void)((p)->_flags &= ~(__SERR|__SEOF))) FD_CLR(n,p) ((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS))) XTHAL_SAM_ISOLATE 0x032 _CLOCKID_T_ unsigned long NBBY 8 XTHAL_AMB_ISOLATE 4 xthal_get_intread xthal_get_interrupt _TIME_T_ long XTHAL_REL_EQ(maja,mina,majb,minb) ((maja) == (majb) && (mina) == (minb)) XTHAL_INTTYPE_NMI 5 XTHAL_TIMER_UNCONFIGURED -1 _MACHSTDLIB_H_ XCHAL_INEXACT -2 BUFSIZ 1024 XTHAL_DISASM_OPT_ADDR 0x0001 __sfileno(p) ((p)->_file) _NEWLIB_ALLOCA_H XCHAL_CA_R (0xC0 | 0x40000000) strtodf strtof __SWR 0x0008 XTHAL_SAM_WRITETHRU 0x02A _BSDTYPES_DEFINED FD_ISSET(n,p) ((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS))) __INTTYPES_DEFINED__ XTHAL_CAFLAG_EXPAND 0x000100 XTHAL_DCACHE_PREFETCH_HIGH XTHAL_DCACHE_PREFETCH(8) EXIT_SUCCESS 0 _stdin_r(x) ((x)->_stdin) P_tmpdir "/tmp" XTHAL_DCACHE_PREFETCH_OFF XTHAL_DCACHE_PREFETCH(0) XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE) fwopen(__cookie,__fn) funopen(__cookie, (int (*)())0, __fn, (fpos_t (*)())0, (int (*)())0) XTHAL_REL_LT(maja,mina,majb,minb) ((maja) < (majb) || ((maja) == (majb) && (mina) < (minb))) EXIT_FAILURE 1 esp_log_early_timestamp XTHAL_REL_11 1 EOF (-1) _SYS_TYPES_FD_SET _flockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_acquire_recursive((fp)->_lock)) FD_SET(n,p) ((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS))) XTHAL_ICACHE_PREFETCH_L1 0xA0002000 XCHAL_INVALID_ADDRESS -3 __clockid_t_defined XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU) _STDLIB_H_ XTHAL_INTTYPE_WRITE_ERROR 6 quad quad_t 
GCC: (crosstool-NG 8d95cad) 4.8.5
.symtab .strtab .shstrtab .iram1.text .dram0.bss .dram0.data .dram0.rodata .iram_pool_1.text .debug_frame .debug_info .debug_abbrev .debug_loc .debug_aranges .debug_ranges .debug_macro .debug_line .debug_str .comment .xtensa.info
bootloader_start.c ota_select_crc ota_select_valid log.c secure_boot.c flash_encrypt.c call_user_start_cpu0 unpack_load_app ets_secure_boot_finish ets_secure_boot_rd_iv SPI_Encrypt_Write load_partition_table _lit4_end _text_end _lit4_start ets_secure_boot_hash _etext bootloader_main memcpy set_cache_and_start_app _rodata_end _iram_text_start rtc_get_reset_reason SPIEraseSector _bss_start _text_start SPIWrite _bss_end _heap_start SPIRead __XT_EXCEPTION_DESCS_END__ call_start_cpu0 xthal_get_ccount _data_start crc32_le ets_secure_boot_start bitcount secure_boot_generate get_bin_len esp_log_timestamp _data_end memset ets_secure_boot_rd_abstract __init_array_end flash_encrypt_write SPIUnlock Cache_Read_Enable _iram_text_end cache_flash_mmu_set __XT_EXCEPTION_DESCS_ mmu_init _init_end flash_encrypt ets_printf Cache_Read_Disable secure_boot ets_secure_boot_obtain boot_cache_redirect _rodata_start Cache_Flush _init_start __init_array_start _stext __XT_EXCEPTION_TABLE_