1# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2#
3# SPDX-License-Identifier: GPL-2.0-or-later
4
5import struct
6import time
7from typing import Dict
8
9from .esp32c6 import ESP32C6ROM
10from ..loader import ESPLoader
11from ..reset import HardReset
12from ..util import FatalError
13
14
15class ESP32C5ROM(ESP32C6ROM):
16    CHIP_NAME = "ESP32-C5"
17    IMAGE_CHIP_ID = 23
18
19    EFUSE_BASE = 0x600B4800
20    EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044
21    MAC_EFUSE_REG = EFUSE_BASE + 0x044
22
23    EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030  # BLOCK0 read base address
24
25    EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
26    EFUSE_PURPOSE_KEY0_SHIFT = 24
27    EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
28    EFUSE_PURPOSE_KEY1_SHIFT = 28
29    EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38
30    EFUSE_PURPOSE_KEY2_SHIFT = 0
31    EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38
32    EFUSE_PURPOSE_KEY3_SHIFT = 4
33    EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38
34    EFUSE_PURPOSE_KEY4_SHIFT = 8
35    EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38
36    EFUSE_PURPOSE_KEY5_SHIFT = 12
37
38    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
39    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20
40
41    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034
42    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
43
44    EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038
45    EFUSE_SECURE_BOOT_EN_MASK = 1 << 20
46
47    IROM_MAP_START = 0x42000000
48    IROM_MAP_END = 0x42800000
49    DROM_MAP_START = 0x42800000
50    DROM_MAP_END = 0x43000000
51
52    PCR_SYSCLK_CONF_REG = 0x60096110
53    PCR_SYSCLK_XTAL_FREQ_V = 0x7F << 24
54    PCR_SYSCLK_XTAL_FREQ_S = 24
55
56    UARTDEV_BUF_NO = 0x4085F51C  # Variable in ROM .bss which indicates the port in use
57
58    # Magic value for ESP32C5
59    CHIP_DETECT_MAGIC_VALUE = [0x1101406F]
60
61    FLASH_FREQUENCY = {
62        "80m": 0xF,
63        "40m": 0x0,
64        "20m": 0x2,
65    }
66
67    MEMORY_MAP = [
68        [0x00000000, 0x00010000, "PADDING"],
69        [0x42800000, 0x43000000, "DROM"],
70        [0x40800000, 0x40860000, "DRAM"],
71        [0x40800000, 0x40860000, "BYTE_ACCESSIBLE"],
72        [0x4003A000, 0x40040000, "DROM_MASK"],
73        [0x40000000, 0x4003A000, "IROM_MASK"],
74        [0x42000000, 0x42800000, "IROM"],
75        [0x40800000, 0x40860000, "IRAM"],
76        [0x50000000, 0x50004000, "RTC_IRAM"],
77        [0x50000000, 0x50004000, "RTC_DRAM"],
78        [0x600FE000, 0x60100000, "MEM_INTERNAL2"],
79    ]
80
81    UF2_FAMILY_ID = 0xF71C0343
82
83    EFUSE_MAX_KEY = 5
84    KEY_PURPOSES: Dict[int, str] = {
85        0: "USER/EMPTY",
86        1: "ECDSA_KEY",
87        2: "XTS_AES_256_KEY_1",
88        3: "XTS_AES_256_KEY_2",
89        4: "XTS_AES_128_KEY",
90        5: "HMAC_DOWN_ALL",
91        6: "HMAC_DOWN_JTAG",
92        7: "HMAC_DOWN_DIGITAL_SIGNATURE",
93        8: "HMAC_UP",
94        9: "SECURE_BOOT_DIGEST0",
95        10: "SECURE_BOOT_DIGEST1",
96        11: "SECURE_BOOT_DIGEST2",
97        12: "KM_INIT_KEY",
98    }
99
100    def get_pkg_version(self):
101        num_word = 2
102        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 26) & 0x07
103
104    def get_minor_chip_version(self):
105        num_word = 2
106        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F
107
108    def get_major_chip_version(self):
109        num_word = 2
110        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 4) & 0x03
111
112    def get_chip_description(self):
113        chip_name = {
114            0: "ESP32-C5",
115        }.get(self.get_pkg_version(), "unknown ESP32-C5")
116        major_rev = self.get_major_chip_version()
117        minor_rev = self.get_minor_chip_version()
118        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
119
120    def get_crystal_freq(self):
121        # The crystal detection algorithm of ESP32/ESP8266
122        # works for ESP32-C5 as well.
123        return ESPLoader.get_crystal_freq(self)
124
125    def get_crystal_freq_rom_expect(self):
126        return (
127            self.read_reg(self.PCR_SYSCLK_CONF_REG) & self.PCR_SYSCLK_XTAL_FREQ_V
128        ) >> self.PCR_SYSCLK_XTAL_FREQ_S
129
130    def hard_reset(self):
131        print("Hard resetting via RTS pin...")
132        HardReset(self._port, self.uses_usb_jtag_serial())()
133
134    def change_baud(self, baud):
135        if not self.IS_STUB:
136            crystal_freq_rom_expect = self.get_crystal_freq_rom_expect()
137            crystal_freq_detect = self.get_crystal_freq()
138            print(
139                f"ROM expects crystal freq: {crystal_freq_rom_expect} MHz, detected {crystal_freq_detect} MHz"
140            )
141            baud_rate = baud
142            # If detect the XTAL is 48MHz, but the ROM code expects it to be 40MHz
143            if crystal_freq_detect == 48 and crystal_freq_rom_expect == 40:
144                baud_rate = baud * 40 // 48
145            # If detect the XTAL is 40MHz, but the ROM code expects it to be 48MHz
146            elif crystal_freq_detect == 40 and crystal_freq_rom_expect == 48:
147                baud_rate = baud * 48 // 40
148            else:
149                ESPLoader.change_baud(self, baud_rate)
150                return
151
152            print(f"Changing baud rate to {baud_rate}")
153            self.command(self.ESP_CHANGE_BAUDRATE, struct.pack("<II", baud_rate, 0))
154            print("Changed.")
155            self._set_port_baudrate(baud)
156            time.sleep(0.05)  # get rid of garbage sent during baud rate change
157            self.flush_input()
158        else:
159            ESPLoader.change_baud(self, baud)
160
161    def check_spi_connection(self, spi_connection):
162        if not set(spi_connection).issubset(set(range(0, 29))):
163            raise FatalError("SPI Pin numbers must be in the range 0-28.")
164        if any([v for v in spi_connection if v in [13, 14]]):
165            print(
166                "WARNING: GPIO pins 13 and 14 are used by USB-Serial/JTAG, "
167                "consider using other pins for SPI flash connection."
168            )
169
170
171class ESP32C5StubLoader(ESP32C5ROM):
172    """Access class for ESP32C5 stub loader, runs on top of ROM.
173
174    (Basically the same as ESP32StubLoader, but different base class.
175    Can possibly be made into a mixin.)
176    """
177
178    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
179    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
180    IS_STUB = True
181
182    def __init__(self, rom_loader):
183        self.secure_download_mode = rom_loader.secure_download_mode
184        self._port = rom_loader._port
185        self._trace_enabled = rom_loader._trace_enabled
186        self.cache = rom_loader.cache
187        self.flush_input()  # resets _slip_reader
188
189
190ESP32C5ROM.STUB_CLASS = ESP32C5StubLoader
191