1# This file describes eFuses fields and registers for ESP32-S3 chip 2# 3# SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 4# 5# SPDX-License-Identifier: GPL-2.0-or-later 6 7import os 8 9import yaml 10 11from ..mem_definition_base import ( 12 EfuseBlocksBase, 13 EfuseFieldsBase, 14 EfuseRegistersBase, 15 Field, 16) 17 18 19class EfuseDefineRegisters(EfuseRegistersBase): 20 EFUSE_ADDR_MASK = 0x00000FFF 21 EFUSE_MEM_SIZE = 0x01FC + 4 22 23 # EFUSE registers & command/conf values 24 DR_REG_EFUSE_BASE = 0x60007000 25 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 26 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 27 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 28 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 29 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 30 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 31 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 32 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 33 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C 34 EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 35 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 36 EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 37 EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C 38 EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 39 EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC 40 EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F4 41 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F8 42 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC 43 EFUSE_WRITE_OP_CODE = 0x5A5A 44 EFUSE_READ_OP_CODE = 0x5AA5 45 EFUSE_PGM_CMD_MASK = 0x3 46 EFUSE_PGM_CMD = 0x2 47 EFUSE_READ_CMD = 0x1 48 49 BLOCK_ERRORS = [ 50 # error_reg, err_num_mask, err_num_offs, fail_bit 51 (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 52 (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 53 (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA 54 (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA 55 (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 56 (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 57 (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 58 (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 59 (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 60 (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 61 (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 62 ] 63 64 # EFUSE_WR_TIM_CONF2_REG 65 EFUSE_PWR_OFF_NUM_S = 0 66 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S 67 68 # EFUSE_WR_TIM_CONF1_REG 69 EFUSE_PWR_ON_NUM_S = 8 70 EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S 71 72 # EFUSE_DAC_CONF_REG 73 EFUSE_DAC_CLK_DIV_S = 0 74 EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S 75 76 # EFUSE_DAC_CONF_REG 77 EFUSE_DAC_NUM_S = 9 78 EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S 79 80 81class EfuseDefineBlocks(EfuseBlocksBase): 82 __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE 83 __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG 84 # List of efuse blocks 85 # fmt: off 86 BLOCKS = [ 87 # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose 88 ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), 89 ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), 90 ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), 91 ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), 92 ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), 93 ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), 94 ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), 95 ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), 96 ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), 97 ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), 98 ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), 99 ] 100 # fmt: on 101 102 def get_burn_block_data_names(self): 103 list_of_names = [] 104 for block in self.BLOCKS: 105 blk = self.get(block) 106 if blk.name: 107 list_of_names.append(blk.name) 108 if blk.alias: 109 for alias in blk.alias: 110 list_of_names.append(alias) 111 return list_of_names 112 113 114class EfuseDefineFields(EfuseFieldsBase): 115 def __init__(self, extend_efuse_table) -> None: 116 # List of efuse fields from TRM the chapter eFuse Controller. 117 self.EFUSES = [] 118 119 self.KEYBLOCKS = [] 120 121 # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 122 self.BLOCK2_CALIBRATION_EFUSES = [] 123 124 self.CALC = [] 125 126 dir_name = os.path.dirname(os.path.abspath(__file__)) 127 dir_name, file_name = os.path.split(dir_name) 128 file_name = file_name + ".yaml" 129 dir_name, _ = os.path.split(dir_name) 130 efuse_file = os.path.join(dir_name, "efuse_defs", file_name) 131 with open(f"{efuse_file}", "r") as r_file: 132 e_desc = yaml.safe_load(r_file) 133 super().__init__(e_desc, extend_efuse_table) 134 135 for i, efuse in enumerate(self.ALL_EFUSES): 136 if efuse.name in [ 137 "BLOCK_USR_DATA", 138 "BLOCK_KEY0", 139 "BLOCK_KEY1", 140 "BLOCK_KEY2", 141 "BLOCK_KEY3", 142 "BLOCK_KEY4", 143 "BLOCK_KEY5", 144 "BLOCK_SYS_DATA2", 145 ]: 146 if efuse.name == "BLOCK_USR_DATA": 147 efuse.bit_len = 256 148 efuse.type = "bytes:32" 149 self.KEYBLOCKS.append(efuse) 150 self.ALL_EFUSES[i] = None 151 152 elif efuse.category == "calibration": 153 self.BLOCK2_CALIBRATION_EFUSES.append(efuse) 154 self.ALL_EFUSES[i] = None 155 156 f = Field() 157 f.name = "WAFER_VERSION_MINOR" 158 f.block = 0 159 f.bit_len = 4 160 f.type = f"uint:{f.bit_len}" 161 f.category = "identity" 162 f.class_type = "wafer" 163 f.description = "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)" 164 self.CALC.append(f) 165 166 for efuse in self.ALL_EFUSES: 167 if efuse is not None: 168 self.EFUSES.append(efuse) 169 170 self.ALL_EFUSES = [] 171