1 /*
2  * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "sdkconfig.h"
8 #include "esp_flash.h"
9 #include "memspi_host_driver.h"
10 #include "esp_flash_spi_init.h"
11 #include "driver/gpio.h"
12 #include "esp_rom_gpio.h"
13 #include "esp_rom_efuse.h"
14 #include "esp_log.h"
15 #include "esp_heap_caps.h"
16 #include "hal/spi_types.h"
17 #include "esp_private/spi_common_internal.h"
18 #include "hal/spi_flash_hal.h"
19 #include "hal/gpio_hal.h"
20 #include "esp_flash_internal.h"
21 #include "esp_rom_gpio.h"
22 #include "esp_private/spi_flash_os.h"
23 #include "esp_private/cache_utils.h"
24 #include "esp_spi_flash_counters.h"
25 #include "esp_rom_spiflash.h"
26 #include "bootloader_flash.h"
27 #include "esp_rom_caps.h"
28 
29 __attribute__((unused)) static const char TAG[] = "spi_flash";
30 
31 /* This pointer is defined in ROM and extern-ed on targets where CONFIG_SPI_FLASH_ROM_IMPL = y*/
32 #if !CONFIG_SPI_FLASH_ROM_IMPL
33 esp_flash_t *esp_flash_default_chip = NULL;
34 #endif
35 
36 #if defined CONFIG_ESPTOOLPY_FLASHFREQ_120M
37 #define DEFAULT_FLASH_SPEED 120
38 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_80M
39 #define DEFAULT_FLASH_SPEED 80
40 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_64M
41 #define DEFAULT_FLASH_SPEED 64
42 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_60M
43 #define DEFAULT_FLASH_SPEED 60
44 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_48M
45 #define DEFAULT_FLASH_SPEED 48
46 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_40M
47 #define DEFAULT_FLASH_SPEED 40
48 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_32M
49 #define DEFAULT_FLASH_SPEED 32
50 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_30M
51 #define DEFAULT_FLASH_SPEED 30
52 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_26M
53 #define DEFAULT_FLASH_SPEED 26
54 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_24M
55 #define DEFAULT_FLASH_SPEED 24
56 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_20M
57 #define DEFAULT_FLASH_SPEED 20
58 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_16M
59 #define DEFAULT_FLASH_SPEED 16
60 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_15M
61 #define DEFAULT_FLASH_SPEED 15
62 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_12M
63 #define DEFAULT_FLASH_SPEED 12
64 #else
65 #error Flash frequency not defined! Check the ``CONFIG_ESPTOOLPY_FLASHFREQ_*`` options.
66 #endif
67 
68 #if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO)
69 #define DEFAULT_FLASH_MODE  SPI_FLASH_QIO
70 #define FLASH_MODE_STRING   "qio"
71 #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
72 #define DEFAULT_FLASH_MODE  SPI_FLASH_QOUT
73 #define FLASH_MODE_STRING   "qout"
74 #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO)
75 #define DEFAULT_FLASH_MODE  SPI_FLASH_DIO
76 #define FLASH_MODE_STRING   "dio"
77 #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
78 #define DEFAULT_FLASH_MODE  SPI_FLASH_DOUT
79 #define FLASH_MODE_STRING   "dout"
80 #elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR)
81 #define DEFAULT_FLASH_MODE SPI_FLASH_OPI_STR
82 #define FLASH_MODE_STRING   "opi_str"
83 #elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR)
84 #define DEFAULT_FLASH_MODE SPI_FLASH_OPI_DTR
85 #define FLASH_MODE_STRING   "opi_dtr"
86 #else
87 #define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD
88 #define FLASH_MODE_STRING   "fast_rd"
89 #endif
90 
91 //TODO: modify cs hold to meet requirements of all chips!!!
92 #if CONFIG_IDF_TARGET_ESP32
93 #define ESP_FLASH_HOST_CONFIG_DEFAULT()  (memspi_host_config_t){ \
94     .host_id = SPI1_HOST,\
95     .freq_mhz = DEFAULT_FLASH_SPEED, \
96     .cs_num = 0, \
97     .iomux = false, \
98     .input_delay_ns = 0,\
99     .cs_setup = 1,\
100 }
101 #elif CONFIG_IDF_TARGET_ESP32S2
102 #define ESP_FLASH_HOST_CONFIG_DEFAULT()  (memspi_host_config_t){ \
103     .host_id = SPI1_HOST,\
104     .freq_mhz = DEFAULT_FLASH_SPEED, \
105     .cs_num = 0, \
106     .iomux = true, \
107     .input_delay_ns = 0,\
108     .cs_setup = 1,\
109 }
110 #elif CONFIG_IDF_TARGET_ESP32S3
111 #include "esp32s3/rom/efuse.h"
112 #define ESP_FLASH_HOST_CONFIG_DEFAULT()  (memspi_host_config_t){ \
113     .host_id = SPI1_HOST,\
114     .freq_mhz = DEFAULT_FLASH_SPEED, \
115     .cs_num = 0, \
116     .iomux = true, \
117     .input_delay_ns = 0,\
118     .cs_setup = 1,\
119 }
120 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
121 #if !CONFIG_SPI_FLASH_AUTO_SUSPEND
122 #define ESP_FLASH_HOST_CONFIG_DEFAULT()  (memspi_host_config_t){ \
123     .host_id = SPI1_HOST,\
124     .freq_mhz = DEFAULT_FLASH_SPEED, \
125     .cs_num = 0, \
126     .iomux = true, \
127     .input_delay_ns = 0,\
128     .cs_setup = 1,\
129 }
130 #else
131 #define ESP_FLASH_HOST_CONFIG_DEFAULT()  (memspi_host_config_t){ \
132     .host_id = SPI1_HOST,\
133     .freq_mhz = DEFAULT_FLASH_SPEED, \
134     .cs_num = 0, \
135     .iomux = true, \
136     .input_delay_ns = 0,\
137     .auto_sus_en = true,\
138     .cs_setup = 1,\
139 }
140 #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
141 #endif
142 
cs_initialize(esp_flash_t * chip,const esp_flash_spi_device_config_t * config,bool use_iomux,int cs_id)143 static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux, int cs_id)
144 {
145     //Not using spicommon_cs_initialize since we don't want to put the whole
146     //spi_periph_signal into the DRAM. Copy these data from flash before the
147     //cache disabling
148     int cs_io_num = config->cs_io_num;
149     int spics_in = spi_periph_signal[config->host_id].spics_in;
150     int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id];
151     int spics_func = spi_periph_signal[config->host_id].func;
152     uint32_t iomux_reg = GPIO_PIN_MUX_REG[cs_io_num];
153     gpio_hal_context_t gpio_hal = {
154         .dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
155     };
156 
157     //To avoid the panic caused by flash data line conflicts during cs line
158     //initialization, disable the cache temporarily
159     chip->os_func->start(chip->os_func_data);
160     PIN_INPUT_ENABLE(iomux_reg);
161     if (use_iomux) {
162         gpio_hal_iomux_func_sel(iomux_reg, spics_func);
163     } else {
164         gpio_hal_output_enable(&gpio_hal, cs_io_num);
165         gpio_hal_od_disable(&gpio_hal, cs_io_num);
166         esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
167         if (cs_id == 0) {
168             esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);
169         }
170         gpio_hal_iomux_func_sel(iomux_reg, PIN_FUNC_GPIO);
171     }
172     chip->os_func->end(chip->os_func_data);
173 }
174 
use_bus_lock(int host_id)175 static bool use_bus_lock(int host_id)
176 {
177     if (host_id != SPI1_HOST) {
178         return true;
179     }
180 #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
181     return true;
182 #else
183     return false;
184 #endif
185 }
186 
acquire_spi_device(const esp_flash_spi_device_config_t * config,int * out_dev_id,spi_bus_lock_dev_handle_t * out_dev_handle)187 static esp_err_t acquire_spi_device(const esp_flash_spi_device_config_t *config, int* out_dev_id, spi_bus_lock_dev_handle_t* out_dev_handle)
188 {
189     esp_err_t ret = ESP_OK;
190     int dev_id = -1;
191     spi_bus_lock_dev_handle_t dev_handle = NULL;
192 
193     if (use_bus_lock(config->host_id)) {
194         spi_bus_lock_handle_t lock = spi_bus_lock_get_by_id(config->host_id);
195         spi_bus_lock_dev_config_t config = {.flags = SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED};
196 
197         ret = spi_bus_lock_register_dev(lock, &config, &dev_handle);
198         if (ret == ESP_OK) {
199             dev_id = spi_bus_lock_get_dev_id(dev_handle);
200         } else if (ret == ESP_ERR_NOT_SUPPORTED) {
201             ESP_LOGE(TAG, "No free CS.");
202         } else if (ret == ESP_ERR_INVALID_ARG) {
203             ESP_LOGE(TAG, "Bus lock not initialized (check CONFIG_SPI_FLASH_SHARE_SPI1_BUS).");
204         }
205     } else {
206         const bool is_main_flash = (config->host_id == SPI1_HOST && config->cs_id == 0);
207         if (config->cs_id >= SOC_SPI_PERIPH_CS_NUM(config->host_id) || config->cs_id < 0 || is_main_flash) {
208             ESP_LOGE(TAG, "Not valid CS.");
209             ret = ESP_ERR_INVALID_ARG;
210         } else {
211             dev_id = config->cs_id;
212             assert(dev_handle == NULL);
213         }
214     }
215 
216     *out_dev_handle = dev_handle;
217     *out_dev_id = dev_id;
218     return ret;
219 }
220 
spi_bus_add_flash_device(esp_flash_t ** out_chip,const esp_flash_spi_device_config_t * config)221 esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_device_config_t *config)
222 {
223     if (out_chip == NULL) {
224         return ESP_ERR_INVALID_ARG;
225     }
226     if (!GPIO_IS_VALID_OUTPUT_GPIO(config->cs_io_num)) {
227         return ESP_ERR_INVALID_ARG;
228     }
229     esp_flash_t *chip = NULL;
230     memspi_host_inst_t *host = NULL;
231     esp_err_t ret = ESP_OK;
232 
233     uint32_t caps = MALLOC_CAP_DEFAULT;
234     if (config->host_id == SPI1_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
235 
236     chip = (esp_flash_t*)heap_caps_malloc(sizeof(esp_flash_t), caps);
237     if (!chip) {
238         ret = ESP_ERR_NO_MEM;
239         goto fail;
240     }
241 
242     host = (memspi_host_inst_t*)heap_caps_malloc(sizeof(memspi_host_inst_t), caps);
243     *chip = (esp_flash_t) {
244         .read_mode = config->io_mode,
245         .host = (spi_flash_host_inst_t*)host,
246     };
247     if (!host) {
248         ret = ESP_ERR_NO_MEM;
249         goto fail;
250     }
251 
252     int dev_id;
253     spi_bus_lock_dev_handle_t dev_handle;
254     esp_err_t err = acquire_spi_device(config, &dev_id, &dev_handle);
255     if (err != ESP_OK) {
256         ret = err;
257         goto fail;
258     }
259 
260     err = esp_flash_init_os_functions(chip, config->host_id, dev_handle);
261     if (err != ESP_OK) {
262         ret = err;
263         goto fail;
264     }
265 
266     //avoid conflicts with main flash
267     assert(config->host_id != SPI1_HOST || dev_id != 0);
268     bool use_iomux = spicommon_bus_using_iomux(config->host_id);
269     memspi_host_config_t host_cfg = {
270         .host_id = config->host_id,
271         .cs_num = dev_id,
272         .iomux = use_iomux,
273         .input_delay_ns = config->input_delay_ns,
274         .freq_mhz = config->freq_mhz,
275     };
276 
277     host_cfg.clock_src_freq = spi_flash_ll_get_source_clock_freq_mhz(host_cfg.host_id);
278 
279     err = memspi_host_init_pointers(host, &host_cfg);
280     if (err != ESP_OK) {
281         ret = err;
282         goto fail;
283     }
284 
285     // The cs_id inside `config` is deprecated, use the `dev_id` provided by the bus lock instead.
286     cs_initialize(chip, config, use_iomux, dev_id);
287     *out_chip = chip;
288     return ret;
289 fail:
290     // The memory allocated are free'd in the `spi_bus_remove_flash_device`.
291     spi_bus_remove_flash_device(chip);
292     return ret;
293 }
294 
spi_bus_remove_flash_device(esp_flash_t * chip)295 esp_err_t spi_bus_remove_flash_device(esp_flash_t *chip)
296 {
297     if (chip == NULL) {
298         return ESP_ERR_INVALID_ARG;
299     }
300 
301     spi_bus_lock_dev_handle_t dev_handle = NULL;
302     esp_flash_deinit_os_functions(chip, &dev_handle);
303     if (dev_handle) {
304         spi_bus_lock_unregister_dev(dev_handle);
305     }
306     free(chip->host);
307     free(chip);
308     return ESP_OK;
309 }
310 
311 /* The default (ie initial boot) no-OS ROM esp_flash_os_functions_t */
312 extern const esp_flash_os_functions_t esp_flash_noos_functions;
313 
314 static DRAM_ATTR memspi_host_inst_t esp_flash_default_host;
315 
316 static DRAM_ATTR esp_flash_t default_chip = {
317     .read_mode = DEFAULT_FLASH_MODE,
318     .host = (spi_flash_host_inst_t*)&esp_flash_default_host,
319     .os_func = &esp_flash_noos_functions,
320 };
321 
322 #if CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
323 /* This function is used to correct flash mode if config option is not consistent with efuse information */
s_esp_flash_choose_correct_mode(memspi_host_config_t * cfg)324 static void s_esp_flash_choose_correct_mode(memspi_host_config_t *cfg)
325 {
326     static const char *mode = FLASH_MODE_STRING;
327     if (bootloader_flash_is_octal_mode_enabled()) {
328     #if !CONFIG_ESPTOOLPY_FLASHMODE_OPI
329         ESP_EARLY_LOGW(TAG, "Octal flash chip is using but %s mode is selected, will automatically swich to Octal mode", mode);
330         cfg->octal_mode_en = 1;
331         cfg->default_io_mode = SPI_FLASH_OPI_STR;
332         default_chip.read_mode = SPI_FLASH_OPI_STR;
333     #endif
334     } else {
335     #if CONFIG_ESPTOOLPY_FLASHMODE_OPI
336         ESP_EARLY_LOGW(TAG, "Quad flash chip is using but %s flash mode is selected, will automatically swich to DIO mode", mode);
337         cfg->octal_mode_en = 0;
338         cfg->default_io_mode = SPI_FLASH_DIO;
339         default_chip.read_mode = SPI_FLASH_DIO;
340     #endif
341     }
342 }
343 #endif // CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
344 
345 extern esp_err_t esp_flash_suspend_cmd_init(esp_flash_t* chip);
esp_flash_init_default_chip(void)346 esp_err_t esp_flash_init_default_chip(void)
347 {
348     const esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
349     memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
350 
351     #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
352     // Only these chips have efuses for spi pin configuration.
353     cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ?  true : false;
354     #endif
355 
356     #if CONFIG_ESPTOOLPY_OCT_FLASH
357     // Default value. When `CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT` selected, if the selected mode not consistent with
358     // hardware, will be overwritten in s_esp_flash_choose_correct_mode.
359     cfg.octal_mode_en = 1;
360     cfg.default_io_mode = DEFAULT_FLASH_MODE;
361     #endif
362 
363     #if CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
364     // Automatically detect flash mode in run time
365     s_esp_flash_choose_correct_mode(&cfg);
366     #endif
367 
368 
369     // For chips need time tuning, get value directely from system here.
370     #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
371     if (spi_timing_is_tuned()) {
372         cfg.using_timing_tuning = 1;
373         spi_timing_get_flash_timing_param(&cfg.timing_reg);
374     }
375     #endif // SOC_SPI_MEM_SUPPORT_TIME_TUNING
376 
377     cfg.clock_src_freq = spi_flash_ll_get_source_clock_freq_mhz(cfg.host_id);
378 
379     //the host is already initialized, only do init for the data and load it to the host
380     esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
381     if (err != ESP_OK) {
382         return err;
383     }
384 
385     // ROM TODO: account for non-standard default pins in efuse
386     // ROM TODO: to account for chips which are slow to power on, maybe keep probing in a loop here
387 
388     err = esp_flash_init_main(&default_chip);
389     if (err != ESP_OK) {
390         return err;
391     }
392     /* TODO: Zephyr workaroud to fix start-up issues
393      * if case there is no bootloader involved */
394 #ifdef CONFIG_BOOTLOADER_MCUBOOT
395     if (default_chip.size < legacy_chip->chip_size) {
396         ESP_EARLY_LOGE(TAG, "Detected size(%dk) smaller than the size in the binary image header(%dk). Probe failed.", default_chip.size/1024, legacy_chip->chip_size/1024);
397         return ESP_ERR_FLASH_SIZE_NOT_MATCH;
398     }
399 #endif
400     if (default_chip.size > legacy_chip->chip_size) {
401         ESP_EARLY_LOGW(TAG, "Detected size(%dk) larger than the size in the binary image header(%dk). Using the size in the binary image header.", default_chip.size/1024, legacy_chip->chip_size/1024);
402     }
403     // Set chip->size equal to ROM flash size(also equal to the size in binary image header), which means the available size that can be used
404     default_chip.size = legacy_chip->chip_size;
405 
406     esp_flash_default_chip = &default_chip;
407 #ifdef CONFIG_SPI_FLASH_AUTO_SUSPEND
408     err = esp_flash_suspend_cmd_init(&default_chip);
409     if (err != ESP_OK) {
410         return err;
411     }
412 #endif
413 
414 #if CONFIG_SPI_FLASH_HPM_DC_ON
415     if (spi_flash_hpm_dummy_adjust()) {
416         default_chip.hpm_dummy_ena = 1;
417     }
418 #endif
419 
420     return ESP_OK;
421 }
422 
esp_flash_app_init(void)423 esp_err_t esp_flash_app_init(void)
424 {
425     esp_err_t err = ESP_OK;
426     spi_flash_init_lock();
427     spi_flash_guard_set(&g_flash_guard_default_ops);
428 #if CONFIG_SPI_FLASH_ENABLE_COUNTERS
429     esp_flash_reset_counters();
430 #endif
431 #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
432     err = esp_flash_init_main_bus_lock();
433     if (err != ESP_OK) return err;
434 #endif
435     err = esp_flash_app_enable_os_functions(&default_chip);
436     return err;
437 }
438