1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include "soc/interrupts.h" 8 9 const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = { 10 [0] = "WIFI_MAC", 11 [1] = "WIFI_NMI", 12 [2] = "WIFI_PWR", 13 [3] = "WIFI_BB", 14 [4] = "BT_MAC", 15 [5] = "BT_BB", 16 [6] = "BT_BB_NMI", 17 [7] = "RWBT", 18 [8] = "RWBLE", 19 [9] = "RWBT_NMI", 20 [10] = "RWBLE_NMI", 21 [11] = "I2C_MASTER", 22 [12] = "SLC0", 23 [13] = "SLC1", 24 [14] = "UHCI0", 25 [15] = "UHCI1", 26 [16] = "GPIO", 27 [17] = "GPIO_NMI", 28 [18] = "GPIO_INTR_2", 29 [19] = "GPIO_NMI_2", 30 [20] = "SPI1", 31 [21] = "SPI2", 32 [22] = "SPI3", 33 [24] = "LCD_CAM", 34 [25] = "I2S0", 35 [26] = "I2S1", 36 [27] = "UART0", 37 [28] = "UART1", 38 [29] = "UART2", 39 [30] = "SDIO_HOST", 40 [31] = "PWM0", 41 [32] = "PWM1", 42 [35] = "LEDC", 43 [36] = "EFUSE", 44 [37] = "TWAI", 45 [38] = "USB", 46 [39] = "RTC_CORE", 47 [40] = "RMT", 48 [41] = "PCNT", 49 [42] = "I2C_EXT0", 50 [43] = "I2C_EXT1", 51 [44] = "SPI2_DMA", 52 [45] = "SPI3_DMA", 53 [47] = "WDT", 54 [48] = "TIMER1", 55 [49] = "TIMER2", 56 [50] = "TG0_T0_LEVEL", 57 [51] = "TG0_T1_LEVEL", 58 [52] = "TG0_WDT_LEVEL", 59 [53] = "TG1_T0_LEVEL", 60 [54] = "TG1_T1_LEVEL", 61 [55] = "TG1_WDT_LEVEL", 62 [56] = "CACHE_IA", 63 [57] = "SYSTIMER_TARGET0", 64 [58] = "SYSTIMER_TARGET1", 65 [59] = "SYSTIMER_TARGET2", 66 [60] = "SPI_MEM_REJECT_CACHE", 67 [61] = "DCACHE_PRELOAD0", 68 [62] = "ICACHE_PRELOAD0", 69 [63] = "DCACHE_SYNC0", 70 [64] = "ICACHE_SYNC0", 71 [65] = "APB_ADC", 72 [66] = "DMA_IN_CH0", 73 [67] = "DMA_IN_CH1", 74 [68] = "DMA_IN_CH2", 75 [69] = "DMA_IN_CH3", 76 [70] = "DMA_IN_CH4", 77 [71] = "DMA_OUT_CH0", 78 [72] = "DMA_OUT_CH1", 79 [73] = "DMA_OUT_CH2", 80 [74] = "DMA_OUT_CH3", 81 [75] = "DMA_OUT_CH4", 82 [76] = "RSA", 83 [77] = "AES", 84 [78] = "SHA", 85 [79] = "FROM_CPU_INTR0", 86 [80] = "FROM_CPU_INTR1", 87 [81] = "FROM_CPU_INTR2", 88 [82] = "FROM_CPU_INTR3", 89 [83] = "ASSIST_DEBUG", 90 [84] = "DMA_APBPERI_PMS", 91 [85] = "CORE0_IRAM0_PMS", 92 [86] = "CORE0_DRAM0_PMS", 93 [87] = "CORE0_PIF_PMS", 94 [88] = "CORE0_PIF_PMS_SIZE", 95 [89] = "CORE1_IRAM0_PMS", 96 [90] = "CORE1_DRAM0_PMS", 97 [91] = "CORE1_PIF_PMS", 98 [92] = "CORE1_PIF_PMS_SIZE", 99 [93] = "BACKUP_PMS_VIOLATE", 100 [94] = "CACHE_CORE0_ACS", 101 [95] = "CACHE_CORE1_ACS", 102 [96] = "USB_SERIAL_JTAG", 103 [97] = "PERI_BACKUP", 104 [98] = "DMA_EXTMEM_REJECT", 105 }; 106