1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_UHCI_REG_H_ 15 #define _SOC_UHCI_REG_H_ 16 17 18 #include "soc.h" 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) 24 /* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 25 /*description: .*/ 26 #define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) 27 #define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12)) 28 #define UHCI_UART_RX_BRK_EOF_EN_V 0x1 29 #define UHCI_UART_RX_BRK_EOF_EN_S 12 30 /* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 31 /*description: .*/ 32 #define UHCI_CLK_EN (BIT(11)) 33 #define UHCI_CLK_EN_M (BIT(11)) 34 #define UHCI_CLK_EN_V 0x1 35 #define UHCI_CLK_EN_S 11 36 /* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 37 /*description: .*/ 38 #define UHCI_ENCODE_CRC_EN (BIT(10)) 39 #define UHCI_ENCODE_CRC_EN_M (BIT(10)) 40 #define UHCI_ENCODE_CRC_EN_V 0x1 41 #define UHCI_ENCODE_CRC_EN_S 10 42 /* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 43 /*description: .*/ 44 #define UHCI_LEN_EOF_EN (BIT(9)) 45 #define UHCI_LEN_EOF_EN_M (BIT(9)) 46 #define UHCI_LEN_EOF_EN_V 0x1 47 #define UHCI_LEN_EOF_EN_S 9 48 /* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 49 /*description: .*/ 50 #define UHCI_UART_IDLE_EOF_EN (BIT(8)) 51 #define UHCI_UART_IDLE_EOF_EN_M (BIT(8)) 52 #define UHCI_UART_IDLE_EOF_EN_V 0x1 53 #define UHCI_UART_IDLE_EOF_EN_S 8 54 /* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 55 /*description: .*/ 56 #define UHCI_CRC_REC_EN (BIT(7)) 57 #define UHCI_CRC_REC_EN_M (BIT(7)) 58 #define UHCI_CRC_REC_EN_V 0x1 59 #define UHCI_CRC_REC_EN_S 7 60 /* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 61 /*description: .*/ 62 #define UHCI_HEAD_EN (BIT(6)) 63 #define UHCI_HEAD_EN_M (BIT(6)) 64 #define UHCI_HEAD_EN_V 0x1 65 #define UHCI_HEAD_EN_S 6 66 /* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 67 /*description: .*/ 68 #define UHCI_SEPER_EN (BIT(5)) 69 #define UHCI_SEPER_EN_M (BIT(5)) 70 #define UHCI_SEPER_EN_V 0x1 71 #define UHCI_SEPER_EN_S 5 72 /* UHCI_UART2_CE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 73 /*description: .*/ 74 #define UHCI_UART2_CE (BIT(4)) 75 #define UHCI_UART2_CE_M (BIT(4)) 76 #define UHCI_UART2_CE_V 0x1 77 #define UHCI_UART2_CE_S 4 78 /* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 79 /*description: .*/ 80 #define UHCI_UART1_CE (BIT(3)) 81 #define UHCI_UART1_CE_M (BIT(3)) 82 #define UHCI_UART1_CE_V 0x1 83 #define UHCI_UART1_CE_S 3 84 /* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */ 85 /*description: .*/ 86 #define UHCI_UART0_CE (BIT(2)) 87 #define UHCI_UART0_CE_M (BIT(2)) 88 #define UHCI_UART0_CE_V 0x1 89 #define UHCI_UART0_CE_S 2 90 /* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 91 /*description: .*/ 92 #define UHCI_RX_RST (BIT(1)) 93 #define UHCI_RX_RST_M (BIT(1)) 94 #define UHCI_RX_RST_V 0x1 95 #define UHCI_RX_RST_S 1 96 /* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ 97 /*description: .*/ 98 #define UHCI_TX_RST (BIT(0)) 99 #define UHCI_TX_RST_M (BIT(0)) 100 #define UHCI_TX_RST_V 0x1 101 #define UHCI_TX_RST_S 0 102 103 #define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) 104 /* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */ 105 /*description: .*/ 106 #define UHCI_APP_CTRL1_INT_RAW (BIT(8)) 107 #define UHCI_APP_CTRL1_INT_RAW_M (BIT(8)) 108 #define UHCI_APP_CTRL1_INT_RAW_V 0x1 109 #define UHCI_APP_CTRL1_INT_RAW_S 8 110 /* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */ 111 /*description: .*/ 112 #define UHCI_APP_CTRL0_INT_RAW (BIT(7)) 113 #define UHCI_APP_CTRL0_INT_RAW_M (BIT(7)) 114 #define UHCI_APP_CTRL0_INT_RAW_V 0x1 115 #define UHCI_APP_CTRL0_INT_RAW_S 7 116 /* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 117 /*description: .*/ 118 #define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(6)) 119 #define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(6)) 120 #define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1 121 #define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 6 122 /* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 123 /*description: .*/ 124 #define UHCI_SEND_A_Q_INT_RAW (BIT(5)) 125 #define UHCI_SEND_A_Q_INT_RAW_M (BIT(5)) 126 #define UHCI_SEND_A_Q_INT_RAW_V 0x1 127 #define UHCI_SEND_A_Q_INT_RAW_S 5 128 /* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 129 /*description: .*/ 130 #define UHCI_SEND_S_Q_INT_RAW (BIT(4)) 131 #define UHCI_SEND_S_Q_INT_RAW_M (BIT(4)) 132 #define UHCI_SEND_S_Q_INT_RAW_V 0x1 133 #define UHCI_SEND_S_Q_INT_RAW_S 4 134 /* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 135 /*description: .*/ 136 #define UHCI_TX_HUNG_INT_RAW (BIT(3)) 137 #define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) 138 #define UHCI_TX_HUNG_INT_RAW_V 0x1 139 #define UHCI_TX_HUNG_INT_RAW_S 3 140 /* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 141 /*description: .*/ 142 #define UHCI_RX_HUNG_INT_RAW (BIT(2)) 143 #define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) 144 #define UHCI_RX_HUNG_INT_RAW_V 0x1 145 #define UHCI_RX_HUNG_INT_RAW_S 2 146 /* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 147 /*description: .*/ 148 #define UHCI_TX_START_INT_RAW (BIT(1)) 149 #define UHCI_TX_START_INT_RAW_M (BIT(1)) 150 #define UHCI_TX_START_INT_RAW_V 0x1 151 #define UHCI_TX_START_INT_RAW_S 1 152 /* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 153 /*description: .*/ 154 #define UHCI_RX_START_INT_RAW (BIT(0)) 155 #define UHCI_RX_START_INT_RAW_M (BIT(0)) 156 #define UHCI_RX_START_INT_RAW_V 0x1 157 #define UHCI_RX_START_INT_RAW_S 0 158 159 #define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) 160 /* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 161 /*description: .*/ 162 #define UHCI_APP_CTRL1_INT_ST (BIT(8)) 163 #define UHCI_APP_CTRL1_INT_ST_M (BIT(8)) 164 #define UHCI_APP_CTRL1_INT_ST_V 0x1 165 #define UHCI_APP_CTRL1_INT_ST_S 8 166 /* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 167 /*description: .*/ 168 #define UHCI_APP_CTRL0_INT_ST (BIT(7)) 169 #define UHCI_APP_CTRL0_INT_ST_M (BIT(7)) 170 #define UHCI_APP_CTRL0_INT_ST_V 0x1 171 #define UHCI_APP_CTRL0_INT_ST_S 7 172 /* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 173 /*description: .*/ 174 #define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) 175 #define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(6)) 176 #define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1 177 #define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 178 /* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 179 /*description: .*/ 180 #define UHCI_SEND_A_Q_INT_ST (BIT(5)) 181 #define UHCI_SEND_A_Q_INT_ST_M (BIT(5)) 182 #define UHCI_SEND_A_Q_INT_ST_V 0x1 183 #define UHCI_SEND_A_Q_INT_ST_S 5 184 /* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 185 /*description: .*/ 186 #define UHCI_SEND_S_Q_INT_ST (BIT(4)) 187 #define UHCI_SEND_S_Q_INT_ST_M (BIT(4)) 188 #define UHCI_SEND_S_Q_INT_ST_V 0x1 189 #define UHCI_SEND_S_Q_INT_ST_S 4 190 /* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 191 /*description: .*/ 192 #define UHCI_TX_HUNG_INT_ST (BIT(3)) 193 #define UHCI_TX_HUNG_INT_ST_M (BIT(3)) 194 #define UHCI_TX_HUNG_INT_ST_V 0x1 195 #define UHCI_TX_HUNG_INT_ST_S 3 196 /* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 197 /*description: .*/ 198 #define UHCI_RX_HUNG_INT_ST (BIT(2)) 199 #define UHCI_RX_HUNG_INT_ST_M (BIT(2)) 200 #define UHCI_RX_HUNG_INT_ST_V 0x1 201 #define UHCI_RX_HUNG_INT_ST_S 2 202 /* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 203 /*description: .*/ 204 #define UHCI_TX_START_INT_ST (BIT(1)) 205 #define UHCI_TX_START_INT_ST_M (BIT(1)) 206 #define UHCI_TX_START_INT_ST_V 0x1 207 #define UHCI_TX_START_INT_ST_S 1 208 /* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 209 /*description: .*/ 210 #define UHCI_RX_START_INT_ST (BIT(0)) 211 #define UHCI_RX_START_INT_ST_M (BIT(0)) 212 #define UHCI_RX_START_INT_ST_V 0x1 213 #define UHCI_RX_START_INT_ST_S 0 214 215 #define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) 216 /* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 217 /*description: .*/ 218 #define UHCI_APP_CTRL1_INT_ENA (BIT(8)) 219 #define UHCI_APP_CTRL1_INT_ENA_M (BIT(8)) 220 #define UHCI_APP_CTRL1_INT_ENA_V 0x1 221 #define UHCI_APP_CTRL1_INT_ENA_S 8 222 /* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 223 /*description: .*/ 224 #define UHCI_APP_CTRL0_INT_ENA (BIT(7)) 225 #define UHCI_APP_CTRL0_INT_ENA_M (BIT(7)) 226 #define UHCI_APP_CTRL0_INT_ENA_V 0x1 227 #define UHCI_APP_CTRL0_INT_ENA_S 7 228 /* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 229 /*description: .*/ 230 #define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) 231 #define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(6)) 232 #define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1 233 #define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 234 /* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 235 /*description: .*/ 236 #define UHCI_SEND_A_Q_INT_ENA (BIT(5)) 237 #define UHCI_SEND_A_Q_INT_ENA_M (BIT(5)) 238 #define UHCI_SEND_A_Q_INT_ENA_V 0x1 239 #define UHCI_SEND_A_Q_INT_ENA_S 5 240 /* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 241 /*description: .*/ 242 #define UHCI_SEND_S_Q_INT_ENA (BIT(4)) 243 #define UHCI_SEND_S_Q_INT_ENA_M (BIT(4)) 244 #define UHCI_SEND_S_Q_INT_ENA_V 0x1 245 #define UHCI_SEND_S_Q_INT_ENA_S 4 246 /* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 247 /*description: .*/ 248 #define UHCI_TX_HUNG_INT_ENA (BIT(3)) 249 #define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) 250 #define UHCI_TX_HUNG_INT_ENA_V 0x1 251 #define UHCI_TX_HUNG_INT_ENA_S 3 252 /* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 253 /*description: .*/ 254 #define UHCI_RX_HUNG_INT_ENA (BIT(2)) 255 #define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) 256 #define UHCI_RX_HUNG_INT_ENA_V 0x1 257 #define UHCI_RX_HUNG_INT_ENA_S 2 258 /* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 259 /*description: .*/ 260 #define UHCI_TX_START_INT_ENA (BIT(1)) 261 #define UHCI_TX_START_INT_ENA_M (BIT(1)) 262 #define UHCI_TX_START_INT_ENA_V 0x1 263 #define UHCI_TX_START_INT_ENA_S 1 264 /* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 265 /*description: .*/ 266 #define UHCI_RX_START_INT_ENA (BIT(0)) 267 #define UHCI_RX_START_INT_ENA_M (BIT(0)) 268 #define UHCI_RX_START_INT_ENA_V 0x1 269 #define UHCI_RX_START_INT_ENA_S 0 270 271 #define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) 272 /* UHCI_APP_CTRL1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 273 /*description: .*/ 274 #define UHCI_APP_CTRL1_INT_CLR (BIT(8)) 275 #define UHCI_APP_CTRL1_INT_CLR_M (BIT(8)) 276 #define UHCI_APP_CTRL1_INT_CLR_V 0x1 277 #define UHCI_APP_CTRL1_INT_CLR_S 8 278 /* UHCI_APP_CTRL0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 279 /*description: .*/ 280 #define UHCI_APP_CTRL0_INT_CLR (BIT(7)) 281 #define UHCI_APP_CTRL0_INT_CLR_M (BIT(7)) 282 #define UHCI_APP_CTRL0_INT_CLR_V 0x1 283 #define UHCI_APP_CTRL0_INT_CLR_S 7 284 /* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 285 /*description: .*/ 286 #define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) 287 #define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(6)) 288 #define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1 289 #define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 290 /* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 291 /*description: .*/ 292 #define UHCI_SEND_A_Q_INT_CLR (BIT(5)) 293 #define UHCI_SEND_A_Q_INT_CLR_M (BIT(5)) 294 #define UHCI_SEND_A_Q_INT_CLR_V 0x1 295 #define UHCI_SEND_A_Q_INT_CLR_S 5 296 /* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 297 /*description: .*/ 298 #define UHCI_SEND_S_Q_INT_CLR (BIT(4)) 299 #define UHCI_SEND_S_Q_INT_CLR_M (BIT(4)) 300 #define UHCI_SEND_S_Q_INT_CLR_V 0x1 301 #define UHCI_SEND_S_Q_INT_CLR_S 4 302 /* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 303 /*description: .*/ 304 #define UHCI_TX_HUNG_INT_CLR (BIT(3)) 305 #define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) 306 #define UHCI_TX_HUNG_INT_CLR_V 0x1 307 #define UHCI_TX_HUNG_INT_CLR_S 3 308 /* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 309 /*description: .*/ 310 #define UHCI_RX_HUNG_INT_CLR (BIT(2)) 311 #define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) 312 #define UHCI_RX_HUNG_INT_CLR_V 0x1 313 #define UHCI_RX_HUNG_INT_CLR_S 2 314 /* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 315 /*description: .*/ 316 #define UHCI_TX_START_INT_CLR (BIT(1)) 317 #define UHCI_TX_START_INT_CLR_M (BIT(1)) 318 #define UHCI_TX_START_INT_CLR_V 0x1 319 #define UHCI_TX_START_INT_CLR_S 1 320 /* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 321 /*description: .*/ 322 #define UHCI_RX_START_INT_CLR (BIT(0)) 323 #define UHCI_RX_START_INT_CLR_M (BIT(0)) 324 #define UHCI_RX_START_INT_CLR_V 0x1 325 #define UHCI_RX_START_INT_CLR_S 0 326 327 #define UHCI_APP_INT_SET_REG(i) (REG_UHCI_BASE(i) + 0x14) 328 /* UHCI_APP_CTRL1_INT_SET : WO ;bitpos:[1] ;default: 1'b0 ; */ 329 /*description: .*/ 330 #define UHCI_APP_CTRL1_INT_SET (BIT(1)) 331 #define UHCI_APP_CTRL1_INT_SET_M (BIT(1)) 332 #define UHCI_APP_CTRL1_INT_SET_V 0x1 333 #define UHCI_APP_CTRL1_INT_SET_S 1 334 /* UHCI_APP_CTRL0_INT_SET : WO ;bitpos:[0] ;default: 1'b0 ; */ 335 /*description: .*/ 336 #define UHCI_APP_CTRL0_INT_SET (BIT(0)) 337 #define UHCI_APP_CTRL0_INT_SET_M (BIT(0)) 338 #define UHCI_APP_CTRL0_INT_SET_V 0x1 339 #define UHCI_APP_CTRL0_INT_SET_S 0 340 341 #define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x18) 342 /* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ 343 /*description: .*/ 344 #define UHCI_SW_START (BIT(8)) 345 #define UHCI_SW_START_M (BIT(8)) 346 #define UHCI_SW_START_V 0x1 347 #define UHCI_SW_START_S 8 348 /* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */ 349 /*description: .*/ 350 #define UHCI_WAIT_SW_START (BIT(7)) 351 #define UHCI_WAIT_SW_START_M (BIT(7)) 352 #define UHCI_WAIT_SW_START_V 0x1 353 #define UHCI_WAIT_SW_START_S 7 354 /* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */ 355 /*description: .*/ 356 #define UHCI_TX_ACK_NUM_RE (BIT(5)) 357 #define UHCI_TX_ACK_NUM_RE_M (BIT(5)) 358 #define UHCI_TX_ACK_NUM_RE_V 0x1 359 #define UHCI_TX_ACK_NUM_RE_S 5 360 /* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */ 361 /*description: .*/ 362 #define UHCI_TX_CHECK_SUM_RE (BIT(4)) 363 #define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) 364 #define UHCI_TX_CHECK_SUM_RE_V 0x1 365 #define UHCI_TX_CHECK_SUM_RE_S 4 366 /* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 367 /*description: .*/ 368 #define UHCI_SAVE_HEAD (BIT(3)) 369 #define UHCI_SAVE_HEAD_M (BIT(3)) 370 #define UHCI_SAVE_HEAD_V 0x1 371 #define UHCI_SAVE_HEAD_S 3 372 /* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 373 /*description: .*/ 374 #define UHCI_CRC_DISABLE (BIT(2)) 375 #define UHCI_CRC_DISABLE_M (BIT(2)) 376 #define UHCI_CRC_DISABLE_V 0x1 377 #define UHCI_CRC_DISABLE_S 2 378 /* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 379 /*description: .*/ 380 #define UHCI_CHECK_SEQ_EN (BIT(1)) 381 #define UHCI_CHECK_SEQ_EN_M (BIT(1)) 382 #define UHCI_CHECK_SEQ_EN_V 0x1 383 #define UHCI_CHECK_SEQ_EN_S 1 384 /* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 385 /*description: .*/ 386 #define UHCI_CHECK_SUM_EN (BIT(0)) 387 #define UHCI_CHECK_SUM_EN_M (BIT(0)) 388 #define UHCI_CHECK_SUM_EN_V 0x1 389 #define UHCI_CHECK_SUM_EN_S 0 390 391 #define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x1C) 392 /* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 393 /*description: .*/ 394 #define UHCI_DECODE_STATE 0x00000007 395 #define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S)) 396 #define UHCI_DECODE_STATE_V 0x7 397 #define UHCI_DECODE_STATE_S 3 398 /* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 399 /*description: .*/ 400 #define UHCI_RX_ERR_CAUSE 0x00000007 401 #define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S)) 402 #define UHCI_RX_ERR_CAUSE_V 0x7 403 #define UHCI_RX_ERR_CAUSE_S 0 404 405 #define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x20) 406 /* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 407 /*description: .*/ 408 #define UHCI_ENCODE_STATE 0x00000007 409 #define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S)) 410 #define UHCI_ENCODE_STATE_V 0x7 411 #define UHCI_ENCODE_STATE_S 0 412 413 #define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) 414 /* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 415 /*description: .*/ 416 #define UHCI_RX_13_ESC_EN (BIT(7)) 417 #define UHCI_RX_13_ESC_EN_M (BIT(7)) 418 #define UHCI_RX_13_ESC_EN_V 0x1 419 #define UHCI_RX_13_ESC_EN_S 7 420 /* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 421 /*description: .*/ 422 #define UHCI_RX_11_ESC_EN (BIT(6)) 423 #define UHCI_RX_11_ESC_EN_M (BIT(6)) 424 #define UHCI_RX_11_ESC_EN_V 0x1 425 #define UHCI_RX_11_ESC_EN_S 6 426 /* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 427 /*description: .*/ 428 #define UHCI_RX_DB_ESC_EN (BIT(5)) 429 #define UHCI_RX_DB_ESC_EN_M (BIT(5)) 430 #define UHCI_RX_DB_ESC_EN_V 0x1 431 #define UHCI_RX_DB_ESC_EN_S 5 432 /* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 433 /*description: .*/ 434 #define UHCI_RX_C0_ESC_EN (BIT(4)) 435 #define UHCI_RX_C0_ESC_EN_M (BIT(4)) 436 #define UHCI_RX_C0_ESC_EN_V 0x1 437 #define UHCI_RX_C0_ESC_EN_S 4 438 /* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 439 /*description: .*/ 440 #define UHCI_TX_13_ESC_EN (BIT(3)) 441 #define UHCI_TX_13_ESC_EN_M (BIT(3)) 442 #define UHCI_TX_13_ESC_EN_V 0x1 443 #define UHCI_TX_13_ESC_EN_S 3 444 /* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 445 /*description: .*/ 446 #define UHCI_TX_11_ESC_EN (BIT(2)) 447 #define UHCI_TX_11_ESC_EN_M (BIT(2)) 448 #define UHCI_TX_11_ESC_EN_V 0x1 449 #define UHCI_TX_11_ESC_EN_S 2 450 /* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 451 /*description: .*/ 452 #define UHCI_TX_DB_ESC_EN (BIT(1)) 453 #define UHCI_TX_DB_ESC_EN_M (BIT(1)) 454 #define UHCI_TX_DB_ESC_EN_V 0x1 455 #define UHCI_TX_DB_ESC_EN_S 1 456 /* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 457 /*description: .*/ 458 #define UHCI_TX_C0_ESC_EN (BIT(0)) 459 #define UHCI_TX_C0_ESC_EN_M (BIT(0)) 460 #define UHCI_TX_C0_ESC_EN_V 0x1 461 #define UHCI_TX_C0_ESC_EN_S 0 462 463 #define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x28) 464 /* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */ 465 /*description: .*/ 466 #define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) 467 #define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) 468 #define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 469 #define UHCI_RXFIFO_TIMEOUT_ENA_S 23 470 /* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ 471 /*description: .*/ 472 #define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 473 #define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S)) 474 #define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 475 #define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 476 /* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */ 477 /*description: .*/ 478 #define UHCI_RXFIFO_TIMEOUT 0x000000FF 479 #define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S)) 480 #define UHCI_RXFIFO_TIMEOUT_V 0xFF 481 #define UHCI_RXFIFO_TIMEOUT_S 12 482 /* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ 483 /*description: .*/ 484 #define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) 485 #define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) 486 #define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 487 #define UHCI_TXFIFO_TIMEOUT_ENA_S 11 488 /* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ 489 /*description: .*/ 490 #define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 491 #define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S)) 492 #define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 493 #define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 494 /* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ 495 /*description: .*/ 496 #define UHCI_TXFIFO_TIMEOUT 0x000000FF 497 #define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S)) 498 #define UHCI_TXFIFO_TIMEOUT_V 0xFF 499 #define UHCI_TXFIFO_TIMEOUT_S 0 500 501 #define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x2C) 502 /* UHCI_ACK_NUM_LOAD : WO ;bitpos:[3] ;default: 1'b1 ; */ 503 /*description: .*/ 504 #define UHCI_ACK_NUM_LOAD (BIT(3)) 505 #define UHCI_ACK_NUM_LOAD_M (BIT(3)) 506 #define UHCI_ACK_NUM_LOAD_V 0x1 507 #define UHCI_ACK_NUM_LOAD_S 3 508 /* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 509 /*description: .*/ 510 #define UHCI_ACK_NUM 0x00000007 511 #define UHCI_ACK_NUM_M ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S)) 512 #define UHCI_ACK_NUM_V 0x7 513 #define UHCI_ACK_NUM_S 0 514 515 #define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x30) 516 /* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 517 /*description: .*/ 518 #define UHCI_RX_HEAD 0xFFFFFFFF 519 #define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S)) 520 #define UHCI_RX_HEAD_V 0xFFFFFFFF 521 #define UHCI_RX_HEAD_S 0 522 523 #define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x34) 524 /* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 525 /*description: .*/ 526 #define UHCI_ALWAYS_SEND_EN (BIT(7)) 527 #define UHCI_ALWAYS_SEND_EN_M (BIT(7)) 528 #define UHCI_ALWAYS_SEND_EN_V 0x1 529 #define UHCI_ALWAYS_SEND_EN_S 7 530 /* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ 531 /*description: .*/ 532 #define UHCI_ALWAYS_SEND_NUM 0x00000007 533 #define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S)) 534 #define UHCI_ALWAYS_SEND_NUM_V 0x7 535 #define UHCI_ALWAYS_SEND_NUM_S 4 536 /* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 537 /*description: .*/ 538 #define UHCI_SINGLE_SEND_EN (BIT(3)) 539 #define UHCI_SINGLE_SEND_EN_M (BIT(3)) 540 #define UHCI_SINGLE_SEND_EN_V 0x1 541 #define UHCI_SINGLE_SEND_EN_S 3 542 /* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 543 /*description: .*/ 544 #define UHCI_SINGLE_SEND_NUM 0x00000007 545 #define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S)) 546 #define UHCI_SINGLE_SEND_NUM_V 0x7 547 #define UHCI_SINGLE_SEND_NUM_S 0 548 549 #define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x38) 550 /* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 551 /*description: .*/ 552 #define UHCI_SEND_Q0_WORD0 0xFFFFFFFF 553 #define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S)) 554 #define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF 555 #define UHCI_SEND_Q0_WORD0_S 0 556 557 #define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x3C) 558 /* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 559 /*description: .*/ 560 #define UHCI_SEND_Q0_WORD1 0xFFFFFFFF 561 #define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S)) 562 #define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF 563 #define UHCI_SEND_Q0_WORD1_S 0 564 565 #define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x40) 566 /* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 567 /*description: .*/ 568 #define UHCI_SEND_Q1_WORD0 0xFFFFFFFF 569 #define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S)) 570 #define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF 571 #define UHCI_SEND_Q1_WORD0_S 0 572 573 #define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x44) 574 /* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 575 /*description: .*/ 576 #define UHCI_SEND_Q1_WORD1 0xFFFFFFFF 577 #define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S)) 578 #define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF 579 #define UHCI_SEND_Q1_WORD1_S 0 580 581 #define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x48) 582 /* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 583 /*description: .*/ 584 #define UHCI_SEND_Q2_WORD0 0xFFFFFFFF 585 #define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S)) 586 #define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF 587 #define UHCI_SEND_Q2_WORD0_S 0 588 589 #define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x4C) 590 /* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 591 /*description: .*/ 592 #define UHCI_SEND_Q2_WORD1 0xFFFFFFFF 593 #define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S)) 594 #define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF 595 #define UHCI_SEND_Q2_WORD1_S 0 596 597 #define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x50) 598 /* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 599 /*description: .*/ 600 #define UHCI_SEND_Q3_WORD0 0xFFFFFFFF 601 #define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S)) 602 #define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF 603 #define UHCI_SEND_Q3_WORD0_S 0 604 605 #define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x54) 606 /* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 607 /*description: .*/ 608 #define UHCI_SEND_Q3_WORD1 0xFFFFFFFF 609 #define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S)) 610 #define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF 611 #define UHCI_SEND_Q3_WORD1_S 0 612 613 #define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x58) 614 /* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 615 /*description: .*/ 616 #define UHCI_SEND_Q4_WORD0 0xFFFFFFFF 617 #define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S)) 618 #define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF 619 #define UHCI_SEND_Q4_WORD0_S 0 620 621 #define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x5C) 622 /* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 623 /*description: .*/ 624 #define UHCI_SEND_Q4_WORD1 0xFFFFFFFF 625 #define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S)) 626 #define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF 627 #define UHCI_SEND_Q4_WORD1_S 0 628 629 #define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x60) 630 /* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 631 /*description: .*/ 632 #define UHCI_SEND_Q5_WORD0 0xFFFFFFFF 633 #define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S)) 634 #define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF 635 #define UHCI_SEND_Q5_WORD0_S 0 636 637 #define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x64) 638 /* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 639 /*description: .*/ 640 #define UHCI_SEND_Q5_WORD1 0xFFFFFFFF 641 #define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S)) 642 #define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF 643 #define UHCI_SEND_Q5_WORD1_S 0 644 645 #define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x68) 646 /* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 647 /*description: .*/ 648 #define UHCI_SEND_Q6_WORD0 0xFFFFFFFF 649 #define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S)) 650 #define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF 651 #define UHCI_SEND_Q6_WORD0_S 0 652 653 #define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x6C) 654 /* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 655 /*description: .*/ 656 #define UHCI_SEND_Q6_WORD1 0xFFFFFFFF 657 #define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S)) 658 #define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF 659 #define UHCI_SEND_Q6_WORD1_S 0 660 661 #define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x70) 662 /* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */ 663 /*description: .*/ 664 #define UHCI_SEPER_ESC_CHAR1 0x000000FF 665 #define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S)) 666 #define UHCI_SEPER_ESC_CHAR1_V 0xFF 667 #define UHCI_SEPER_ESC_CHAR1_S 16 668 /* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ 669 /*description: .*/ 670 #define UHCI_SEPER_ESC_CHAR0 0x000000FF 671 #define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S)) 672 #define UHCI_SEPER_ESC_CHAR0_V 0xFF 673 #define UHCI_SEPER_ESC_CHAR0_S 8 674 /* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ 675 /*description: .*/ 676 #define UHCI_SEPER_CHAR 0x000000FF 677 #define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S)) 678 #define UHCI_SEPER_CHAR_V 0xFF 679 #define UHCI_SEPER_CHAR_S 0 680 681 #define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x74) 682 /* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */ 683 /*description: .*/ 684 #define UHCI_ESC_SEQ0_CHAR1 0x000000FF 685 #define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S)) 686 #define UHCI_ESC_SEQ0_CHAR1_V 0xFF 687 #define UHCI_ESC_SEQ0_CHAR1_S 16 688 /* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ 689 /*description: .*/ 690 #define UHCI_ESC_SEQ0_CHAR0 0x000000FF 691 #define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S)) 692 #define UHCI_ESC_SEQ0_CHAR0_V 0xFF 693 #define UHCI_ESC_SEQ0_CHAR0_S 8 694 /* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */ 695 /*description: .*/ 696 #define UHCI_ESC_SEQ0 0x000000FF 697 #define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S)) 698 #define UHCI_ESC_SEQ0_V 0xFF 699 #define UHCI_ESC_SEQ0_S 0 700 701 #define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x78) 702 /* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */ 703 /*description: .*/ 704 #define UHCI_ESC_SEQ1_CHAR1 0x000000FF 705 #define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S)) 706 #define UHCI_ESC_SEQ1_CHAR1_V 0xFF 707 #define UHCI_ESC_SEQ1_CHAR1_S 16 708 /* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ 709 /*description: .*/ 710 #define UHCI_ESC_SEQ1_CHAR0 0x000000FF 711 #define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S)) 712 #define UHCI_ESC_SEQ1_CHAR0_V 0xFF 713 #define UHCI_ESC_SEQ1_CHAR0_S 8 714 /* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */ 715 /*description: .*/ 716 #define UHCI_ESC_SEQ1 0x000000FF 717 #define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S)) 718 #define UHCI_ESC_SEQ1_V 0xFF 719 #define UHCI_ESC_SEQ1_S 0 720 721 #define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x7C) 722 /* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */ 723 /*description: .*/ 724 #define UHCI_ESC_SEQ2_CHAR1 0x000000FF 725 #define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S)) 726 #define UHCI_ESC_SEQ2_CHAR1_V 0xFF 727 #define UHCI_ESC_SEQ2_CHAR1_S 16 728 /* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ 729 /*description: .*/ 730 #define UHCI_ESC_SEQ2_CHAR0 0x000000FF 731 #define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S)) 732 #define UHCI_ESC_SEQ2_CHAR0_V 0xFF 733 #define UHCI_ESC_SEQ2_CHAR0_S 8 734 /* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */ 735 /*description: .*/ 736 #define UHCI_ESC_SEQ2 0x000000FF 737 #define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S)) 738 #define UHCI_ESC_SEQ2_V 0xFF 739 #define UHCI_ESC_SEQ2_S 0 740 741 #define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x80) 742 /* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */ 743 /*description: .*/ 744 #define UHCI_PKT_THRS 0x00001FFF 745 #define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S)) 746 #define UHCI_PKT_THRS_V 0x1FFF 747 #define UHCI_PKT_THRS_S 0 748 749 #define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x84) 750 /* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2010090 ; */ 751 /*description: .*/ 752 #define UHCI_DATE 0xFFFFFFFF 753 #define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S)) 754 #define UHCI_DATE_V 0xFFFFFFFF 755 #define UHCI_DATE_S 0 756 757 758 #ifdef __cplusplus 759 } 760 #endif 761 762 763 764 #endif /*_SOC_UHCI_REG_H_ */ 765
