1 /* 2 * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 // The long term plan is to have a single soc_caps.h for all peripherals. 8 // During the refactoring and multichip support development process, we 9 // separate these information into periph_caps.h for each peripheral and 10 // include them here to avoid developing conflicts. 11 12 /* 13 * These defines are parsed and imported as kconfig variables via the script 14 * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` 15 * 16 * If this file is changed the script will automatically run the script 17 * and generate the kconfig variables as part of the pre-commit hooks. 18 * 19 * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32s3/include/soc/'` 20 * 21 * For more information see `tools/gen_soc_caps_kconfig/README.md` 22 * 23 */ 24 25 #pragma once 26 27 /*-------------------------- COMMON CAPS ---------------------------------------*/ 28 #define SOC_ADC_SUPPORTED 1 29 #define SOC_UART_SUPPORTED 1 30 #define SOC_PCNT_SUPPORTED 1 31 #define SOC_WIFI_SUPPORTED 1 32 #define SOC_TWAI_SUPPORTED 1 33 #define SOC_GDMA_SUPPORTED 1 34 #define SOC_GPTIMER_SUPPORTED 1 35 #define SOC_LCDCAM_SUPPORTED 1 36 #define SOC_MCPWM_SUPPORTED 1 37 #define SOC_DEDICATED_GPIO_SUPPORTED 1 38 #define SOC_CACHE_SUPPORT_WRAP 1 39 #define SOC_ULP_SUPPORTED 1 40 #define SOC_ULP_FSM_SUPPORTED 1 41 #define SOC_RISCV_COPROC_SUPPORTED 1 42 #define SOC_BT_SUPPORTED 1 43 #define SOC_USB_OTG_SUPPORTED 1 44 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 45 #define SOC_CCOMP_TIMER_SUPPORTED 1 46 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 47 #define SOC_SUPPORTS_SECURE_DL_MODE 1 48 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 49 #define SOC_SDMMC_HOST_SUPPORTED 1 50 #define SOC_RTC_FAST_MEM_SUPPORTED 1 51 #define SOC_RTC_SLOW_MEM_SUPPORTED 1 52 #define SOC_RTC_MEM_SUPPORTED 1 53 #define SOC_PSRAM_DMA_CAPABLE 1 54 #define SOC_XT_WDT_SUPPORTED 1 55 #define SOC_I2S_SUPPORTED 1 56 #define SOC_RMT_SUPPORTED 1 57 #define SOC_SDM_SUPPORTED 1 58 #define SOC_GPSPI_SUPPORTED 1 59 #define SOC_LEDC_SUPPORTED 1 60 #define SOC_I2C_SUPPORTED 1 61 #define SOC_SYSTIMER_SUPPORTED 1 62 #define SOC_SUPPORT_COEXISTENCE 1 63 #define SOC_TEMP_SENSOR_SUPPORTED 1 64 #define SOC_AES_SUPPORTED 1 65 #define SOC_MPI_SUPPORTED 1 66 #define SOC_SHA_SUPPORTED 1 67 #define SOC_HMAC_SUPPORTED 1 68 #define SOC_DIG_SIGN_SUPPORTED 1 69 #define SOC_FLASH_ENC_SUPPORTED 1 70 #define SOC_SECURE_BOOT_SUPPORTED 1 71 #define SOC_MEMPROT_SUPPORTED 1 72 #define SOC_TOUCH_SENSOR_SUPPORTED 1 73 #define SOC_BOD_SUPPORTED 1 74 75 /*-------------------------- XTAL CAPS ---------------------------------------*/ 76 #define SOC_XTAL_SUPPORT_40M 1 77 78 /*-------------------------- SOC CAPS ----------------------------------------*/ 79 #define SOC_APPCPU_HAS_CLOCK_GATING_BUG (1) 80 81 /*-------------------------- ADC CAPS ----------------------------------------*/ 82 /*!< SAR ADC Module*/ 83 #define SOC_ADC_RTC_CTRL_SUPPORTED 1 84 #define SOC_ADC_DIG_CTRL_SUPPORTED 1 85 #define SOC_ADC_ARBITER_SUPPORTED 1 86 #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 87 #define SOC_ADC_MONITOR_SUPPORTED 1 88 #define SOC_ADC_DMA_SUPPORTED 1 89 #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0) //Digital controller supported ADC unit 90 #define SOC_ADC_PERIPH_NUM (2) 91 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) 92 #define SOC_ADC_MAX_CHANNEL_NUM (10) 93 #define SOC_ADC_ATTEN_NUM (4) 94 95 /*!< Digital */ 96 #define SOC_ADC_DIGI_CONTROLLER_NUM (2) 97 #define SOC_ADC_PATT_LEN_MAX (24) //Two pattern table, each contains 12 items. Each item takes 1 byte 98 #define SOC_ADC_DIGI_MIN_BITWIDTH (12) 99 #define SOC_ADC_DIGI_MAX_BITWIDTH (12) 100 #define SOC_ADC_DIGI_RESULT_BYTES (4) 101 #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) 102 #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) 103 /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */ 104 #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 105 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 106 107 /*!< RTC */ 108 #define SOC_ADC_RTC_MIN_BITWIDTH (12) 109 #define SOC_ADC_RTC_MAX_BITWIDTH (12) 110 111 /*!< Calibration */ 112 #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ 113 #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ 114 115 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ 116 #define SOC_APB_BACKUP_DMA (1) 117 118 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ 119 #define SOC_BROWNOUT_RESET_SUPPORTED 1 120 121 /*-------------------------- CACHE CAPS --------------------------------------*/ 122 #define SOC_CACHE_WRITEBACK_SUPPORTED 1 123 #define SOC_CACHE_FREEZE_SUPPORTED 1 124 125 /*-------------------------- CPU CAPS ----------------------------------------*/ 126 #define SOC_CPU_CORES_NUM 2 127 #define SOC_CPU_INTR_NUM 32 128 #define SOC_CPU_HAS_FPU 1 129 130 #define SOC_CPU_BREAKPOINTS_NUM 2 131 #define SOC_CPU_WATCHPOINTS_NUM 2 132 #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes 133 134 /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ 135 /** The maximum length of a Digital Signature in bits. */ 136 #define SOC_DS_SIGNATURE_MAX_BIT_LEN (4096) 137 138 /** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ 139 #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) 140 141 /** Maximum wait time for DS parameter decryption key. If overdue, then key error. 142 See TRM DS chapter for more details */ 143 #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) 144 145 /*-------------------------- GDMA CAPS ---------------------------------------*/ 146 #define SOC_GDMA_GROUPS (1) // Number of GDMA groups 147 #define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group 148 #define SOC_GDMA_SUPPORT_PSRAM (1) // GDMA can access external PSRAM 149 150 /*-------------------------- GPIO CAPS ---------------------------------------*/ 151 // ESP32-S3 has 1 GPIO peripheral 152 #define SOC_GPIO_PORT 1U 153 #define SOC_GPIO_PIN_COUNT 49 154 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 155 #define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 156 157 // On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. 158 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) 159 // Force hold is a new function of ESP32-S3 160 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) 161 162 // 0~48 valid except 22~25 163 #define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) 164 // No GPIO is input only 165 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK) 166 167 #define SOC_GPIO_IN_RANGE_MAX 48 168 #define SOC_GPIO_OUT_RANGE_MAX 48 169 170 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_48) 171 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000ULL 172 173 174 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ 175 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ 176 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ 177 #define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */ 178 179 /*-------------------------- I2C CAPS ----------------------------------------*/ 180 // ESP32-S3 has 2 I2C 181 #define SOC_I2C_NUM (2) 182 183 #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ 184 #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */ 185 #define SOC_I2C_SUPPORT_SLAVE (1) 186 187 // FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined. 188 //ESP32-S3 support hardware clear bus 189 #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) 190 191 #define SOC_I2C_SUPPORT_XTAL (1) 192 #define SOC_I2C_SUPPORT_RTC (1) 193 194 /*-------------------------- I2S CAPS ----------------------------------------*/ 195 #define SOC_I2S_NUM (2U) 196 #define SOC_I2S_HW_VERSION_2 (1) 197 #define SOC_I2S_SUPPORTS_XTAL (1) 198 #define SOC_I2S_SUPPORTS_PLL_F160M (1) 199 #define SOC_I2S_SUPPORTS_PCM (1) 200 #define SOC_I2S_SUPPORTS_PDM (1) 201 #define SOC_I2S_SUPPORTS_PDM_TX (1) 202 #define SOC_I2S_PDM_MAX_TX_LINES (2) 203 #define SOC_I2S_SUPPORTS_PDM_RX (1) 204 #define SOC_I2S_PDM_MAX_RX_LINES (4) 205 #define SOC_I2S_SUPPORTS_TDM (1) 206 207 /*-------------------------- LEDC CAPS ---------------------------------------*/ 208 #define SOC_LEDC_SUPPORT_APB_CLOCK (1) 209 #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) 210 #define SOC_LEDC_CHANNEL_NUM (8) 211 #define SOC_LEDC_TIMER_BIT_WIDTH (14) 212 #define SOC_LEDC_SUPPORT_FADE_STOP (1) 213 214 /*-------------------------- MCPWM CAPS --------------------------------------*/ 215 #define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) 216 #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has 217 #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has 218 #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has 219 #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has 220 #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has 221 #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has 222 #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has 223 #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has 224 #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has 225 #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output 226 227 /*-------------------------- MMU CAPS ----------------------------------------*/ 228 #define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U) 229 #define SOC_MMU_PERIPH_NUM (1U) 230 231 /*-------------------------- MPU CAPS ----------------------------------------*/ 232 #include "mpu_caps.h" 233 234 /*-------------------------- PCNT CAPS ---------------------------------------*/ 235 #define SOC_PCNT_GROUPS (1U) 236 #define SOC_PCNT_UNITS_PER_GROUP (4) 237 #define SOC_PCNT_CHANNELS_PER_UNIT (2) 238 #define SOC_PCNT_THRES_POINT_PER_UNIT (2) 239 240 /*-------------------------- RMT CAPS ----------------------------------------*/ 241 #define SOC_RMT_GROUPS 1U /*!< One RMT group */ 242 #define SOC_RMT_TX_CANDIDATES_PER_GROUP 4 /*!< Number of channels that capable of Transmit in each group */ 243 #define SOC_RMT_RX_CANDIDATES_PER_GROUP 4 /*!< Number of channels that capable of Receive in each group */ 244 #define SOC_RMT_CHANNELS_PER_GROUP 8 /*!< Total 8 channels */ 245 #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ 246 #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */ 247 #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */ 248 #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */ 249 #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */ 250 #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */ 251 #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */ 252 #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ 253 #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ 254 #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */ 255 #define SOC_RMT_SUPPORT_APB 1 /*!< Support set APB as the RMT clock source */ 256 #define SOC_RMT_SUPPORT_DMA 1 /*!< RMT peripheral can connect to DMA channel */ 257 258 /*-------------------------- LCD CAPS ----------------------------------------*/ 259 /* Notes: On esp32-s3, I80 bus and RGB timing generator can't work at the same time */ 260 #define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */ 261 #define SOC_LCD_RGB_SUPPORTED (1) /*!< RGB LCD is supported */ 262 #define SOC_LCD_I80_BUSES (1U) /*!< Has one LCD Intel 8080 bus */ 263 #define SOC_LCD_RGB_PANELS (1U) /*!< Support one RGB LCD panel */ 264 #define SOC_LCD_I80_BUS_WIDTH (16) /*!< Intel 8080 bus width */ 265 #define SOC_LCD_RGB_DATA_WIDTH (16) /*!< Number of LCD data lines */ 266 #define SOC_LCD_SUPPORT_RGB_YUV_CONV (1) /*!< Support color format conversion between RGB and YUV */ 267 268 /*-------------------------- RTC CAPS --------------------------------------*/ 269 #define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128) 270 #define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (549) 271 #define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) 272 #define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) 273 274 #define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) 275 276 /* I/D Cache tag memory retention hardware parameters */ 277 #define SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH (128) 278 #define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3) 279 280 /*-------------------------- RTCIO CAPS --------------------------------------*/ 281 #define SOC_RTCIO_PIN_COUNT 22 282 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, 283 * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.) 284 * when the pins are switched to RTC function. 285 */ 286 #define SOC_RTCIO_HOLD_SUPPORTED 1 287 #define SOC_RTCIO_WAKE_SUPPORTED 1 288 289 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ 290 #define SOC_SDM_GROUPS 1 291 #define SOC_SDM_CHANNELS_PER_GROUP 8 292 #define SOC_SDM_CLK_SUPPORT_APB 1 293 294 /*-------------------------- SPI CAPS ----------------------------------------*/ 295 #define SOC_SPI_PERIPH_NUM 3 296 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) 297 #define SOC_SPI_MAX_CS_NUM 6 298 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 299 #define SOC_SPI_SUPPORT_DDRCLK 1 300 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 301 #define SOC_SPI_SUPPORT_CD_SIG 1 302 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 303 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 304 #define SOC_SPI_SUPPORT_CLK_APB 1 305 #define SOC_SPI_SUPPORT_CLK_XTAL 1 306 307 // Peripheral supports DIO, DOUT, QIO, or QOUT 308 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) 309 310 // Peripheral supports output given level during its "dummy phase" 311 #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 312 #define SOC_MEMSPI_IS_INDEPENDENT 1 313 #define SOC_SPI_MAX_PRE_DIVIDER 16 314 #define SOC_SPI_SUPPORT_OCT 1 315 316 #define SOC_MEMSPI_SRC_FREQ_120M 1 317 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 318 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 319 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 320 321 /*-------------------------- SPIRAM CAPS ----------------------------------------*/ 322 #define SOC_SPIRAM_SUPPORTED 1 323 #define SOC_SPIRAM_XIP_SUPPORTED 1 324 325 /*-------------------------- SYS TIMER CAPS ----------------------------------*/ 326 #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units 327 #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units 328 #define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part 329 #define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part 330 #define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 331 #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level 332 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) 333 334 /*-------------------------- TIMER GROUP CAPS --------------------------------*/ 335 #define SOC_TIMER_GROUPS (2) 336 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2) 337 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) 338 #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) 339 #define SOC_TIMER_GROUP_SUPPORT_APB (1) 340 #define SOC_TIMER_GROUP_TOTAL_TIMERS (4) 341 342 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ 343 #define SOC_TOUCH_VERSION_2 (1) // Hardware version of touch sensor 344 #define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */ 345 #define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /* Sopport touch proximity channel number. */ 346 #define SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED (1) /*Sopport touch proximity channel measure done interrupt type. */ 347 348 #define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*!<If set touch threshold max value, The touch sensor can't be in touched status */ 349 #define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */ 350 351 /*-------------------------- TWAI CAPS ---------------------------------------*/ 352 #define SOC_TWAI_CONTROLLER_NUM 1UL 353 #define SOC_TWAI_CLK_SUPPORT_APB 1 354 #define SOC_TWAI_BRP_MIN 2 355 #define SOC_TWAI_BRP_MAX 16384 356 #define SOC_TWAI_SUPPORTS_RX_STATUS 1 357 358 /*-------------------------- UART CAPS ---------------------------------------*/ 359 // ESP32-S3 has 3 UARTs 360 #define SOC_UART_NUM (3) 361 #define SOC_UART_HP_NUM (3) 362 #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ 363 #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ 364 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled 365 #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) 366 #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ 367 #define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */ 368 #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ 369 #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ 370 #define SOC_UART_REQUIRE_CORE_RESET (1) 371 372 /*-------------------------- USB CAPS ----------------------------------------*/ 373 #define SOC_USB_OTG_PERIPH_NUM (1U) 374 375 376 /*--------------------------- SHA CAPS ---------------------------------------*/ 377 /* Max amount of bytes in a single DMA operation is 4095, 378 for SHA this means that the biggest safe amount of bytes is 379 31 blocks of 128 bytes = 3968 380 */ 381 #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) 382 #define SOC_SHA_SUPPORT_DMA (1) 383 384 /* The SHA engine is able to resume hashing from a user supplied context */ 385 #define SOC_SHA_SUPPORT_RESUME (1) 386 387 /* Has a centralized DMA, which is shared with all peripherals */ 388 #define SOC_SHA_GDMA (1) 389 390 /* Supported HW algorithms */ 391 #define SOC_SHA_SUPPORT_SHA1 (1) 392 #define SOC_SHA_SUPPORT_SHA224 (1) 393 #define SOC_SHA_SUPPORT_SHA256 (1) 394 #define SOC_SHA_SUPPORT_SHA384 (1) 395 #define SOC_SHA_SUPPORT_SHA512 (1) 396 #define SOC_SHA_SUPPORT_SHA512_224 (1) 397 #define SOC_SHA_SUPPORT_SHA512_256 (1) 398 #define SOC_SHA_SUPPORT_SHA512_T (1) 399 400 401 /*--------------------------- RSA CAPS ---------------------------------------*/ 402 #define SOC_RSA_MAX_BIT_LEN (4096) 403 404 405 /*-------------------------- AES CAPS -----------------------------------------*/ 406 #define SOC_AES_SUPPORT_DMA (1) 407 408 /* Has a centralized DMA, which is shared with all peripherals */ 409 #define SOC_AES_GDMA (1) 410 411 #define SOC_AES_SUPPORT_AES_128 (1) 412 #define SOC_AES_SUPPORT_AES_256 (1) 413 414 415 /*-------------------------- Power Management CAPS ---------------------------*/ 416 #define SOC_PM_SUPPORT_EXT0_WAKEUP (1) 417 #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) 418 #define SOC_PM_SUPPORT_EXT_WAKEUP (1) /*!<Compatible to the old version of IDF */ 419 #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) 420 #define SOC_PM_SUPPORT_BT_WAKEUP (1) 421 #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */ 422 423 #define SOC_PM_SUPPORT_CPU_PD (1) 424 #define SOC_PM_SUPPORT_TAGMEM_PD (1) 425 #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) 426 #define SOC_PM_SUPPORT_RC_FAST_PD (1) 427 #define SOC_PM_SUPPORT_VDDSDIO_PD (1) 428 #define SOC_PM_SUPPORT_MAC_BB_PD (1) 429 #define SOC_PM_SUPPORT_MODEM_PD (1) /*!<Modem here includes wifi and ble */ 430 431 #define SOC_CONFIGURABLE_VDDSDIO_SUPPORTED (1) 432 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */ 433 434 #define SOC_PM_CPU_RETENTION_BY_RTCCNTL (1) 435 #define SOC_PM_MODEM_RETENTION_BY_BACKUPDMA (1) 436 437 /*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */ 438 #define SOC_CLK_RC_FAST_D256_SUPPORTED (1) 439 #define SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 (1) 440 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) 441 442 #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ 443 444 /*-------------------------- eFuse CAPS----------------------------*/ 445 #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 446 #define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1 447 #define SOC_EFUSE_HARD_DIS_JTAG 1 448 #define SOC_EFUSE_DIS_USB_JTAG 1 449 #define SOC_EFUSE_SOFT_DIS_JTAG 1 450 #define SOC_EFUSE_DIS_DIRECT_BOOT 1 451 #define SOC_EFUSE_DIS_ICACHE 1 452 #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // AES-XTS key purpose not supported for this block 453 454 /*-------------------------- Secure Boot CAPS----------------------------*/ 455 #define SOC_SECURE_BOOT_V2_RSA 1 456 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 457 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 458 #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 459 460 /*-------------------------- Flash Encryption CAPS----------------------------*/ 461 #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) 462 #define SOC_FLASH_ENCRYPTION_XTS_AES 1 463 #define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1 464 #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 465 #define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 466 467 /*-------------------------- MEMPROT CAPS ------------------------------------*/ 468 #define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 469 #define SOC_MEMPROT_MEM_ALIGN_SIZE 256 470 471 /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ 472 #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) 473 #define SOC_MAC_BB_PD_MEM_SIZE (192*4) 474 475 /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ 476 #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) 477 478 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ 479 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) 480 #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) 481 #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) 482 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) 483 #define SOC_SPI_MEM_SUPPORT_OPI_MODE (1) 484 #define SOC_SPI_MEM_SUPPORT_TIME_TUNING (1) 485 #define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1) 486 #define SOC_SPI_MEM_SUPPORT_WRAP (1) 487 488 /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ 489 #define SOC_COEX_HW_PTI (1) 490 491 /*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ 492 #define SOC_EXTERNAL_COEX_ADVANCE (0) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ 493 #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (1) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ 494 495 /*-------------------------- SDMMC CAPS -----------------------------------------*/ 496 497 /* Card detect, write protect, interrupt use GPIO Matrix on all chips. 498 * On ESP32-S3, clock/cmd/data pins use GPIO Matrix as well. 499 */ 500 #define SOC_SDMMC_USE_GPIO_MATRIX 1 501 #define SOC_SDMMC_NUM_SLOTS 2 502 /* Indicates that there is an option to use XTAL clock instead of PLL for SDMMC */ 503 #define SOC_SDMMC_SUPPORT_XTAL_CLOCK 1 504 505 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ 506 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) 507 508 /*------------------------------------ WI-FI CAPS ------------------------------------*/ 509 #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ 510 #define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */ 511 #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ 512 #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ 513 #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ 514 #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ 515 #define SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW (1) /*!< Support delta early time for rf phy on/off */ 516 #define SOC_WIFI_PHY_NEEDS_USB_WORKAROUND (1) /*!< SoC has WiFi and USB PHYs interference, needs a workaround */ 517 518 /*---------------------------------- Bluetooth CAPS ----------------------------------*/ 519 #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ 520 #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ 521 #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */ 522 #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */ 523 #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */ 524 525 /*-------------------------- ULP CAPS ----------------------------------------*/ 526 #define SOC_ULP_HAS_ADC (1) /* ADC can be accessed from ULP */ 527 528 /*------------------------------------- PHY CAPS -------------------------------------*/ 529 #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi and BLE*/ 530
