1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** PCNT_U0_CONF0_REG register 16 * Configuration register 0 for unit 0 17 */ 18 #define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) 19 /** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16; 20 * This sets the maximum threshold, in APB_CLK cycles, for the filter. 21 * 22 * Any pulses with width less than this will be ignored when the filter is enabled. 23 */ 24 #define PCNT_FILTER_THRES_U0 0x000003FFU 25 #define PCNT_FILTER_THRES_U0_M (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S) 26 #define PCNT_FILTER_THRES_U0_V 0x000003FFU 27 #define PCNT_FILTER_THRES_U0_S 0 28 /** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1; 29 * This is the enable bit for unit 0's input filter. 30 */ 31 #define PCNT_FILTER_EN_U0 (BIT(10)) 32 #define PCNT_FILTER_EN_U0_M (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S) 33 #define PCNT_FILTER_EN_U0_V 0x00000001U 34 #define PCNT_FILTER_EN_U0_S 10 35 /** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1; 36 * This is the enable bit for unit 0's zero comparator. 37 */ 38 #define PCNT_THR_ZERO_EN_U0 (BIT(11)) 39 #define PCNT_THR_ZERO_EN_U0_M (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S) 40 #define PCNT_THR_ZERO_EN_U0_V 0x00000001U 41 #define PCNT_THR_ZERO_EN_U0_S 11 42 /** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1; 43 * This is the enable bit for unit 0's thr_h_lim comparator. 44 */ 45 #define PCNT_THR_H_LIM_EN_U0 (BIT(12)) 46 #define PCNT_THR_H_LIM_EN_U0_M (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S) 47 #define PCNT_THR_H_LIM_EN_U0_V 0x00000001U 48 #define PCNT_THR_H_LIM_EN_U0_S 12 49 /** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1; 50 * This is the enable bit for unit 0's thr_l_lim comparator. 51 */ 52 #define PCNT_THR_L_LIM_EN_U0 (BIT(13)) 53 #define PCNT_THR_L_LIM_EN_U0_M (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S) 54 #define PCNT_THR_L_LIM_EN_U0_V 0x00000001U 55 #define PCNT_THR_L_LIM_EN_U0_S 13 56 /** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0; 57 * This is the enable bit for unit 0's thres0 comparator. 58 */ 59 #define PCNT_THR_THRES0_EN_U0 (BIT(14)) 60 #define PCNT_THR_THRES0_EN_U0_M (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S) 61 #define PCNT_THR_THRES0_EN_U0_V 0x00000001U 62 #define PCNT_THR_THRES0_EN_U0_S 14 63 /** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0; 64 * This is the enable bit for unit 0's thres1 comparator. 65 */ 66 #define PCNT_THR_THRES1_EN_U0 (BIT(15)) 67 #define PCNT_THR_THRES1_EN_U0_M (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S) 68 #define PCNT_THR_THRES1_EN_U0_V 0x00000001U 69 #define PCNT_THR_THRES1_EN_U0_S 15 70 /** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0; 71 * This register sets the behavior when the signal input of channel 0 detects a 72 * negative edge. 73 * 74 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 75 */ 76 #define PCNT_CH0_NEG_MODE_U0 0x00000003U 77 #define PCNT_CH0_NEG_MODE_U0_M (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S) 78 #define PCNT_CH0_NEG_MODE_U0_V 0x00000003U 79 #define PCNT_CH0_NEG_MODE_U0_S 16 80 /** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0; 81 * This register sets the behavior when the signal input of channel 0 detects a 82 * positive edge. 83 * 84 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 85 */ 86 #define PCNT_CH0_POS_MODE_U0 0x00000003U 87 #define PCNT_CH0_POS_MODE_U0_M (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S) 88 #define PCNT_CH0_POS_MODE_U0_V 0x00000003U 89 #define PCNT_CH0_POS_MODE_U0_S 18 90 /** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0; 91 * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be 92 * modified when the control signal is high. 93 * 94 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 95 * increase);2, 3: Inhibit counter modification 96 */ 97 #define PCNT_CH0_HCTRL_MODE_U0 0x00000003U 98 #define PCNT_CH0_HCTRL_MODE_U0_M (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S) 99 #define PCNT_CH0_HCTRL_MODE_U0_V 0x00000003U 100 #define PCNT_CH0_HCTRL_MODE_U0_S 20 101 /** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0; 102 * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be 103 * modified when the control signal is low. 104 * 105 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 106 * increase);2, 3: Inhibit counter modification 107 */ 108 #define PCNT_CH0_LCTRL_MODE_U0 0x00000003U 109 #define PCNT_CH0_LCTRL_MODE_U0_M (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S) 110 #define PCNT_CH0_LCTRL_MODE_U0_V 0x00000003U 111 #define PCNT_CH0_LCTRL_MODE_U0_S 22 112 /** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0; 113 * This register sets the behavior when the signal input of channel 1 detects a 114 * negative edge. 115 * 116 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 117 */ 118 #define PCNT_CH1_NEG_MODE_U0 0x00000003U 119 #define PCNT_CH1_NEG_MODE_U0_M (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S) 120 #define PCNT_CH1_NEG_MODE_U0_V 0x00000003U 121 #define PCNT_CH1_NEG_MODE_U0_S 24 122 /** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0; 123 * This register sets the behavior when the signal input of channel 1 detects a 124 * positive edge. 125 * 126 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 127 */ 128 #define PCNT_CH1_POS_MODE_U0 0x00000003U 129 #define PCNT_CH1_POS_MODE_U0_M (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S) 130 #define PCNT_CH1_POS_MODE_U0_V 0x00000003U 131 #define PCNT_CH1_POS_MODE_U0_S 26 132 /** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0; 133 * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be 134 * modified when the control signal is high. 135 * 136 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 137 * increase);2, 3: Inhibit counter modification 138 */ 139 #define PCNT_CH1_HCTRL_MODE_U0 0x00000003U 140 #define PCNT_CH1_HCTRL_MODE_U0_M (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S) 141 #define PCNT_CH1_HCTRL_MODE_U0_V 0x00000003U 142 #define PCNT_CH1_HCTRL_MODE_U0_S 28 143 /** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0; 144 * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be 145 * modified when the control signal is low. 146 * 147 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 148 * increase);2, 3: Inhibit counter modification 149 */ 150 #define PCNT_CH1_LCTRL_MODE_U0 0x00000003U 151 #define PCNT_CH1_LCTRL_MODE_U0_M (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S) 152 #define PCNT_CH1_LCTRL_MODE_U0_V 0x00000003U 153 #define PCNT_CH1_LCTRL_MODE_U0_S 30 154 155 /** PCNT_U0_CONF1_REG register 156 * Configuration register 1 for unit 0 157 */ 158 #define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) 159 /** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0; 160 * This register is used to configure the thres0 value for unit 0. 161 */ 162 #define PCNT_CNT_THRES0_U0 0x0000FFFFU 163 #define PCNT_CNT_THRES0_U0_M (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S) 164 #define PCNT_CNT_THRES0_U0_V 0x0000FFFFU 165 #define PCNT_CNT_THRES0_U0_S 0 166 /** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0; 167 * This register is used to configure the thres1 value for unit 0. 168 */ 169 #define PCNT_CNT_THRES1_U0 0x0000FFFFU 170 #define PCNT_CNT_THRES1_U0_M (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S) 171 #define PCNT_CNT_THRES1_U0_V 0x0000FFFFU 172 #define PCNT_CNT_THRES1_U0_S 16 173 174 /** PCNT_U0_CONF2_REG register 175 * Configuration register 2 for unit 0 176 */ 177 #define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) 178 /** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0; 179 * This register is used to configure the thr_h_lim value for unit 0. 180 */ 181 #define PCNT_CNT_H_LIM_U0 0x0000FFFFU 182 #define PCNT_CNT_H_LIM_U0_M (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S) 183 #define PCNT_CNT_H_LIM_U0_V 0x0000FFFFU 184 #define PCNT_CNT_H_LIM_U0_S 0 185 /** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0; 186 * This register is used to configure the thr_l_lim value for unit 0. 187 */ 188 #define PCNT_CNT_L_LIM_U0 0x0000FFFFU 189 #define PCNT_CNT_L_LIM_U0_M (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S) 190 #define PCNT_CNT_L_LIM_U0_V 0x0000FFFFU 191 #define PCNT_CNT_L_LIM_U0_S 16 192 193 /** PCNT_U1_CONF0_REG register 194 * Configuration register 0 for unit 1 195 */ 196 #define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc) 197 /** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16; 198 * This sets the maximum threshold, in APB_CLK cycles, for the filter. 199 * 200 * Any pulses with width less than this will be ignored when the filter is enabled. 201 */ 202 #define PCNT_FILTER_THRES_U1 0x000003FFU 203 #define PCNT_FILTER_THRES_U1_M (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S) 204 #define PCNT_FILTER_THRES_U1_V 0x000003FFU 205 #define PCNT_FILTER_THRES_U1_S 0 206 /** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1; 207 * This is the enable bit for unit 1's input filter. 208 */ 209 #define PCNT_FILTER_EN_U1 (BIT(10)) 210 #define PCNT_FILTER_EN_U1_M (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S) 211 #define PCNT_FILTER_EN_U1_V 0x00000001U 212 #define PCNT_FILTER_EN_U1_S 10 213 /** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1; 214 * This is the enable bit for unit 1's zero comparator. 215 */ 216 #define PCNT_THR_ZERO_EN_U1 (BIT(11)) 217 #define PCNT_THR_ZERO_EN_U1_M (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S) 218 #define PCNT_THR_ZERO_EN_U1_V 0x00000001U 219 #define PCNT_THR_ZERO_EN_U1_S 11 220 /** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1; 221 * This is the enable bit for unit 1's thr_h_lim comparator. 222 */ 223 #define PCNT_THR_H_LIM_EN_U1 (BIT(12)) 224 #define PCNT_THR_H_LIM_EN_U1_M (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S) 225 #define PCNT_THR_H_LIM_EN_U1_V 0x00000001U 226 #define PCNT_THR_H_LIM_EN_U1_S 12 227 /** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1; 228 * This is the enable bit for unit 1's thr_l_lim comparator. 229 */ 230 #define PCNT_THR_L_LIM_EN_U1 (BIT(13)) 231 #define PCNT_THR_L_LIM_EN_U1_M (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S) 232 #define PCNT_THR_L_LIM_EN_U1_V 0x00000001U 233 #define PCNT_THR_L_LIM_EN_U1_S 13 234 /** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0; 235 * This is the enable bit for unit 1's thres0 comparator. 236 */ 237 #define PCNT_THR_THRES0_EN_U1 (BIT(14)) 238 #define PCNT_THR_THRES0_EN_U1_M (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S) 239 #define PCNT_THR_THRES0_EN_U1_V 0x00000001U 240 #define PCNT_THR_THRES0_EN_U1_S 14 241 /** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0; 242 * This is the enable bit for unit 1's thres1 comparator. 243 */ 244 #define PCNT_THR_THRES1_EN_U1 (BIT(15)) 245 #define PCNT_THR_THRES1_EN_U1_M (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S) 246 #define PCNT_THR_THRES1_EN_U1_V 0x00000001U 247 #define PCNT_THR_THRES1_EN_U1_S 15 248 /** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0; 249 * This register sets the behavior when the signal input of channel 0 detects a 250 * negative edge. 251 * 252 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 253 */ 254 #define PCNT_CH0_NEG_MODE_U1 0x00000003U 255 #define PCNT_CH0_NEG_MODE_U1_M (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S) 256 #define PCNT_CH0_NEG_MODE_U1_V 0x00000003U 257 #define PCNT_CH0_NEG_MODE_U1_S 16 258 /** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0; 259 * This register sets the behavior when the signal input of channel 0 detects a 260 * positive edge. 261 * 262 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 263 */ 264 #define PCNT_CH0_POS_MODE_U1 0x00000003U 265 #define PCNT_CH0_POS_MODE_U1_M (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S) 266 #define PCNT_CH0_POS_MODE_U1_V 0x00000003U 267 #define PCNT_CH0_POS_MODE_U1_S 18 268 /** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0; 269 * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be 270 * modified when the control signal is high. 271 * 272 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 273 * increase);2, 3: Inhibit counter modification 274 */ 275 #define PCNT_CH0_HCTRL_MODE_U1 0x00000003U 276 #define PCNT_CH0_HCTRL_MODE_U1_M (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S) 277 #define PCNT_CH0_HCTRL_MODE_U1_V 0x00000003U 278 #define PCNT_CH0_HCTRL_MODE_U1_S 20 279 /** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0; 280 * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be 281 * modified when the control signal is low. 282 * 283 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 284 * increase);2, 3: Inhibit counter modification 285 */ 286 #define PCNT_CH0_LCTRL_MODE_U1 0x00000003U 287 #define PCNT_CH0_LCTRL_MODE_U1_M (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S) 288 #define PCNT_CH0_LCTRL_MODE_U1_V 0x00000003U 289 #define PCNT_CH0_LCTRL_MODE_U1_S 22 290 /** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0; 291 * This register sets the behavior when the signal input of channel 1 detects a 292 * negative edge. 293 * 294 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 295 */ 296 #define PCNT_CH1_NEG_MODE_U1 0x00000003U 297 #define PCNT_CH1_NEG_MODE_U1_M (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S) 298 #define PCNT_CH1_NEG_MODE_U1_V 0x00000003U 299 #define PCNT_CH1_NEG_MODE_U1_S 24 300 /** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0; 301 * This register sets the behavior when the signal input of channel 1 detects a 302 * positive edge. 303 * 304 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 305 */ 306 #define PCNT_CH1_POS_MODE_U1 0x00000003U 307 #define PCNT_CH1_POS_MODE_U1_M (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S) 308 #define PCNT_CH1_POS_MODE_U1_V 0x00000003U 309 #define PCNT_CH1_POS_MODE_U1_S 26 310 /** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0; 311 * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be 312 * modified when the control signal is high. 313 * 314 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 315 * increase);2, 3: Inhibit counter modification 316 */ 317 #define PCNT_CH1_HCTRL_MODE_U1 0x00000003U 318 #define PCNT_CH1_HCTRL_MODE_U1_M (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S) 319 #define PCNT_CH1_HCTRL_MODE_U1_V 0x00000003U 320 #define PCNT_CH1_HCTRL_MODE_U1_S 28 321 /** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0; 322 * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be 323 * modified when the control signal is low. 324 * 325 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 326 * increase);2, 3: Inhibit counter modification 327 */ 328 #define PCNT_CH1_LCTRL_MODE_U1 0x00000003U 329 #define PCNT_CH1_LCTRL_MODE_U1_M (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S) 330 #define PCNT_CH1_LCTRL_MODE_U1_V 0x00000003U 331 #define PCNT_CH1_LCTRL_MODE_U1_S 30 332 333 /** PCNT_U1_CONF1_REG register 334 * Configuration register 1 for unit 1 335 */ 336 #define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10) 337 /** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0; 338 * This register is used to configure the thres0 value for unit 1. 339 */ 340 #define PCNT_CNT_THRES0_U1 0x0000FFFFU 341 #define PCNT_CNT_THRES0_U1_M (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S) 342 #define PCNT_CNT_THRES0_U1_V 0x0000FFFFU 343 #define PCNT_CNT_THRES0_U1_S 0 344 /** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0; 345 * This register is used to configure the thres1 value for unit 1. 346 */ 347 #define PCNT_CNT_THRES1_U1 0x0000FFFFU 348 #define PCNT_CNT_THRES1_U1_M (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S) 349 #define PCNT_CNT_THRES1_U1_V 0x0000FFFFU 350 #define PCNT_CNT_THRES1_U1_S 16 351 352 /** PCNT_U1_CONF2_REG register 353 * Configuration register 2 for unit 1 354 */ 355 #define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14) 356 /** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0; 357 * This register is used to configure the thr_h_lim value for unit 1. 358 */ 359 #define PCNT_CNT_H_LIM_U1 0x0000FFFFU 360 #define PCNT_CNT_H_LIM_U1_M (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S) 361 #define PCNT_CNT_H_LIM_U1_V 0x0000FFFFU 362 #define PCNT_CNT_H_LIM_U1_S 0 363 /** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0; 364 * This register is used to configure the thr_l_lim value for unit 1. 365 */ 366 #define PCNT_CNT_L_LIM_U1 0x0000FFFFU 367 #define PCNT_CNT_L_LIM_U1_M (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S) 368 #define PCNT_CNT_L_LIM_U1_V 0x0000FFFFU 369 #define PCNT_CNT_L_LIM_U1_S 16 370 371 /** PCNT_U2_CONF0_REG register 372 * Configuration register 0 for unit 2 373 */ 374 #define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18) 375 /** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16; 376 * This sets the maximum threshold, in APB_CLK cycles, for the filter. 377 * 378 * Any pulses with width less than this will be ignored when the filter is enabled. 379 */ 380 #define PCNT_FILTER_THRES_U2 0x000003FFU 381 #define PCNT_FILTER_THRES_U2_M (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S) 382 #define PCNT_FILTER_THRES_U2_V 0x000003FFU 383 #define PCNT_FILTER_THRES_U2_S 0 384 /** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1; 385 * This is the enable bit for unit 2's input filter. 386 */ 387 #define PCNT_FILTER_EN_U2 (BIT(10)) 388 #define PCNT_FILTER_EN_U2_M (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S) 389 #define PCNT_FILTER_EN_U2_V 0x00000001U 390 #define PCNT_FILTER_EN_U2_S 10 391 /** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1; 392 * This is the enable bit for unit 2's zero comparator. 393 */ 394 #define PCNT_THR_ZERO_EN_U2 (BIT(11)) 395 #define PCNT_THR_ZERO_EN_U2_M (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S) 396 #define PCNT_THR_ZERO_EN_U2_V 0x00000001U 397 #define PCNT_THR_ZERO_EN_U2_S 11 398 /** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1; 399 * This is the enable bit for unit 2's thr_h_lim comparator. 400 */ 401 #define PCNT_THR_H_LIM_EN_U2 (BIT(12)) 402 #define PCNT_THR_H_LIM_EN_U2_M (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S) 403 #define PCNT_THR_H_LIM_EN_U2_V 0x00000001U 404 #define PCNT_THR_H_LIM_EN_U2_S 12 405 /** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1; 406 * This is the enable bit for unit 2's thr_l_lim comparator. 407 */ 408 #define PCNT_THR_L_LIM_EN_U2 (BIT(13)) 409 #define PCNT_THR_L_LIM_EN_U2_M (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S) 410 #define PCNT_THR_L_LIM_EN_U2_V 0x00000001U 411 #define PCNT_THR_L_LIM_EN_U2_S 13 412 /** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0; 413 * This is the enable bit for unit 2's thres0 comparator. 414 */ 415 #define PCNT_THR_THRES0_EN_U2 (BIT(14)) 416 #define PCNT_THR_THRES0_EN_U2_M (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S) 417 #define PCNT_THR_THRES0_EN_U2_V 0x00000001U 418 #define PCNT_THR_THRES0_EN_U2_S 14 419 /** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0; 420 * This is the enable bit for unit 2's thres1 comparator. 421 */ 422 #define PCNT_THR_THRES1_EN_U2 (BIT(15)) 423 #define PCNT_THR_THRES1_EN_U2_M (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S) 424 #define PCNT_THR_THRES1_EN_U2_V 0x00000001U 425 #define PCNT_THR_THRES1_EN_U2_S 15 426 /** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0; 427 * This register sets the behavior when the signal input of channel 0 detects a 428 * negative edge. 429 * 430 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 431 */ 432 #define PCNT_CH0_NEG_MODE_U2 0x00000003U 433 #define PCNT_CH0_NEG_MODE_U2_M (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S) 434 #define PCNT_CH0_NEG_MODE_U2_V 0x00000003U 435 #define PCNT_CH0_NEG_MODE_U2_S 16 436 /** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0; 437 * This register sets the behavior when the signal input of channel 0 detects a 438 * positive edge. 439 * 440 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 441 */ 442 #define PCNT_CH0_POS_MODE_U2 0x00000003U 443 #define PCNT_CH0_POS_MODE_U2_M (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S) 444 #define PCNT_CH0_POS_MODE_U2_V 0x00000003U 445 #define PCNT_CH0_POS_MODE_U2_S 18 446 /** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0; 447 * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be 448 * modified when the control signal is high. 449 * 450 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 451 * increase);2, 3: Inhibit counter modification 452 */ 453 #define PCNT_CH0_HCTRL_MODE_U2 0x00000003U 454 #define PCNT_CH0_HCTRL_MODE_U2_M (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S) 455 #define PCNT_CH0_HCTRL_MODE_U2_V 0x00000003U 456 #define PCNT_CH0_HCTRL_MODE_U2_S 20 457 /** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0; 458 * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be 459 * modified when the control signal is low. 460 * 461 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 462 * increase);2, 3: Inhibit counter modification 463 */ 464 #define PCNT_CH0_LCTRL_MODE_U2 0x00000003U 465 #define PCNT_CH0_LCTRL_MODE_U2_M (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S) 466 #define PCNT_CH0_LCTRL_MODE_U2_V 0x00000003U 467 #define PCNT_CH0_LCTRL_MODE_U2_S 22 468 /** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0; 469 * This register sets the behavior when the signal input of channel 1 detects a 470 * negative edge. 471 * 472 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 473 */ 474 #define PCNT_CH1_NEG_MODE_U2 0x00000003U 475 #define PCNT_CH1_NEG_MODE_U2_M (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S) 476 #define PCNT_CH1_NEG_MODE_U2_V 0x00000003U 477 #define PCNT_CH1_NEG_MODE_U2_S 24 478 /** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0; 479 * This register sets the behavior when the signal input of channel 1 detects a 480 * positive edge. 481 * 482 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 483 */ 484 #define PCNT_CH1_POS_MODE_U2 0x00000003U 485 #define PCNT_CH1_POS_MODE_U2_M (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S) 486 #define PCNT_CH1_POS_MODE_U2_V 0x00000003U 487 #define PCNT_CH1_POS_MODE_U2_S 26 488 /** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0; 489 * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be 490 * modified when the control signal is high. 491 * 492 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 493 * increase);2, 3: Inhibit counter modification 494 */ 495 #define PCNT_CH1_HCTRL_MODE_U2 0x00000003U 496 #define PCNT_CH1_HCTRL_MODE_U2_M (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S) 497 #define PCNT_CH1_HCTRL_MODE_U2_V 0x00000003U 498 #define PCNT_CH1_HCTRL_MODE_U2_S 28 499 /** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0; 500 * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be 501 * modified when the control signal is low. 502 * 503 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 504 * increase);2, 3: Inhibit counter modification 505 */ 506 #define PCNT_CH1_LCTRL_MODE_U2 0x00000003U 507 #define PCNT_CH1_LCTRL_MODE_U2_M (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S) 508 #define PCNT_CH1_LCTRL_MODE_U2_V 0x00000003U 509 #define PCNT_CH1_LCTRL_MODE_U2_S 30 510 511 /** PCNT_U2_CONF1_REG register 512 * Configuration register 1 for unit 2 513 */ 514 #define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c) 515 /** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0; 516 * This register is used to configure the thres0 value for unit 2. 517 */ 518 #define PCNT_CNT_THRES0_U2 0x0000FFFFU 519 #define PCNT_CNT_THRES0_U2_M (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S) 520 #define PCNT_CNT_THRES0_U2_V 0x0000FFFFU 521 #define PCNT_CNT_THRES0_U2_S 0 522 /** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0; 523 * This register is used to configure the thres1 value for unit 2. 524 */ 525 #define PCNT_CNT_THRES1_U2 0x0000FFFFU 526 #define PCNT_CNT_THRES1_U2_M (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S) 527 #define PCNT_CNT_THRES1_U2_V 0x0000FFFFU 528 #define PCNT_CNT_THRES1_U2_S 16 529 530 /** PCNT_U2_CONF2_REG register 531 * Configuration register 2 for unit 2 532 */ 533 #define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20) 534 /** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0; 535 * This register is used to configure the thr_h_lim value for unit 2. 536 */ 537 #define PCNT_CNT_H_LIM_U2 0x0000FFFFU 538 #define PCNT_CNT_H_LIM_U2_M (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S) 539 #define PCNT_CNT_H_LIM_U2_V 0x0000FFFFU 540 #define PCNT_CNT_H_LIM_U2_S 0 541 /** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0; 542 * This register is used to configure the thr_l_lim value for unit 2. 543 */ 544 #define PCNT_CNT_L_LIM_U2 0x0000FFFFU 545 #define PCNT_CNT_L_LIM_U2_M (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S) 546 #define PCNT_CNT_L_LIM_U2_V 0x0000FFFFU 547 #define PCNT_CNT_L_LIM_U2_S 16 548 549 /** PCNT_U3_CONF0_REG register 550 * Configuration register 0 for unit 3 551 */ 552 #define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24) 553 /** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16; 554 * This sets the maximum threshold, in APB_CLK cycles, for the filter. 555 * 556 * Any pulses with width less than this will be ignored when the filter is enabled. 557 */ 558 #define PCNT_FILTER_THRES_U3 0x000003FFU 559 #define PCNT_FILTER_THRES_U3_M (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S) 560 #define PCNT_FILTER_THRES_U3_V 0x000003FFU 561 #define PCNT_FILTER_THRES_U3_S 0 562 /** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1; 563 * This is the enable bit for unit 3's input filter. 564 */ 565 #define PCNT_FILTER_EN_U3 (BIT(10)) 566 #define PCNT_FILTER_EN_U3_M (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S) 567 #define PCNT_FILTER_EN_U3_V 0x00000001U 568 #define PCNT_FILTER_EN_U3_S 10 569 /** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1; 570 * This is the enable bit for unit 3's zero comparator. 571 */ 572 #define PCNT_THR_ZERO_EN_U3 (BIT(11)) 573 #define PCNT_THR_ZERO_EN_U3_M (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S) 574 #define PCNT_THR_ZERO_EN_U3_V 0x00000001U 575 #define PCNT_THR_ZERO_EN_U3_S 11 576 /** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1; 577 * This is the enable bit for unit 3's thr_h_lim comparator. 578 */ 579 #define PCNT_THR_H_LIM_EN_U3 (BIT(12)) 580 #define PCNT_THR_H_LIM_EN_U3_M (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S) 581 #define PCNT_THR_H_LIM_EN_U3_V 0x00000001U 582 #define PCNT_THR_H_LIM_EN_U3_S 12 583 /** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1; 584 * This is the enable bit for unit 3's thr_l_lim comparator. 585 */ 586 #define PCNT_THR_L_LIM_EN_U3 (BIT(13)) 587 #define PCNT_THR_L_LIM_EN_U3_M (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S) 588 #define PCNT_THR_L_LIM_EN_U3_V 0x00000001U 589 #define PCNT_THR_L_LIM_EN_U3_S 13 590 /** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0; 591 * This is the enable bit for unit 3's thres0 comparator. 592 */ 593 #define PCNT_THR_THRES0_EN_U3 (BIT(14)) 594 #define PCNT_THR_THRES0_EN_U3_M (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S) 595 #define PCNT_THR_THRES0_EN_U3_V 0x00000001U 596 #define PCNT_THR_THRES0_EN_U3_S 14 597 /** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0; 598 * This is the enable bit for unit 3's thres1 comparator. 599 */ 600 #define PCNT_THR_THRES1_EN_U3 (BIT(15)) 601 #define PCNT_THR_THRES1_EN_U3_M (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S) 602 #define PCNT_THR_THRES1_EN_U3_V 0x00000001U 603 #define PCNT_THR_THRES1_EN_U3_S 15 604 /** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0; 605 * This register sets the behavior when the signal input of channel 0 detects a 606 * negative edge. 607 * 608 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 609 */ 610 #define PCNT_CH0_NEG_MODE_U3 0x00000003U 611 #define PCNT_CH0_NEG_MODE_U3_M (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S) 612 #define PCNT_CH0_NEG_MODE_U3_V 0x00000003U 613 #define PCNT_CH0_NEG_MODE_U3_S 16 614 /** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0; 615 * This register sets the behavior when the signal input of channel 0 detects a 616 * positive edge. 617 * 618 * 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter 619 */ 620 #define PCNT_CH0_POS_MODE_U3 0x00000003U 621 #define PCNT_CH0_POS_MODE_U3_M (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S) 622 #define PCNT_CH0_POS_MODE_U3_V 0x00000003U 623 #define PCNT_CH0_POS_MODE_U3_S 18 624 /** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0; 625 * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be 626 * modified when the control signal is high. 627 * 628 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 629 * increase);2, 3: Inhibit counter modification 630 */ 631 #define PCNT_CH0_HCTRL_MODE_U3 0x00000003U 632 #define PCNT_CH0_HCTRL_MODE_U3_M (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S) 633 #define PCNT_CH0_HCTRL_MODE_U3_V 0x00000003U 634 #define PCNT_CH0_HCTRL_MODE_U3_S 20 635 /** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0; 636 * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be 637 * modified when the control signal is low. 638 * 639 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 640 * increase);2, 3: Inhibit counter modification 641 */ 642 #define PCNT_CH0_LCTRL_MODE_U3 0x00000003U 643 #define PCNT_CH0_LCTRL_MODE_U3_M (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S) 644 #define PCNT_CH0_LCTRL_MODE_U3_V 0x00000003U 645 #define PCNT_CH0_LCTRL_MODE_U3_S 22 646 /** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0; 647 * This register sets the behavior when the signal input of channel 1 detects a 648 * negative edge. 649 * 650 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 651 */ 652 #define PCNT_CH1_NEG_MODE_U3 0x00000003U 653 #define PCNT_CH1_NEG_MODE_U3_M (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S) 654 #define PCNT_CH1_NEG_MODE_U3_V 0x00000003U 655 #define PCNT_CH1_NEG_MODE_U3_S 24 656 /** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0; 657 * This register sets the behavior when the signal input of channel 1 detects a 658 * positive edge. 659 * 660 * 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter 661 */ 662 #define PCNT_CH1_POS_MODE_U3 0x00000003U 663 #define PCNT_CH1_POS_MODE_U3_M (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S) 664 #define PCNT_CH1_POS_MODE_U3_V 0x00000003U 665 #define PCNT_CH1_POS_MODE_U3_S 26 666 /** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0; 667 * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be 668 * modified when the control signal is high. 669 * 670 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 671 * increase);2, 3: Inhibit counter modification 672 */ 673 #define PCNT_CH1_HCTRL_MODE_U3 0x00000003U 674 #define PCNT_CH1_HCTRL_MODE_U3_M (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S) 675 #define PCNT_CH1_HCTRL_MODE_U3_V 0x00000003U 676 #define PCNT_CH1_HCTRL_MODE_U3_S 28 677 /** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0; 678 * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be 679 * modified when the control signal is low. 680 * 681 * 0: No modification;1: Invert behavior (increase -> decrease, decrease -> 682 * increase);2, 3: Inhibit counter modification 683 */ 684 #define PCNT_CH1_LCTRL_MODE_U3 0x00000003U 685 #define PCNT_CH1_LCTRL_MODE_U3_M (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S) 686 #define PCNT_CH1_LCTRL_MODE_U3_V 0x00000003U 687 #define PCNT_CH1_LCTRL_MODE_U3_S 30 688 689 /** PCNT_U3_CONF1_REG register 690 * Configuration register 1 for unit 3 691 */ 692 #define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28) 693 /** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0; 694 * This register is used to configure the thres0 value for unit 3. 695 */ 696 #define PCNT_CNT_THRES0_U3 0x0000FFFFU 697 #define PCNT_CNT_THRES0_U3_M (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S) 698 #define PCNT_CNT_THRES0_U3_V 0x0000FFFFU 699 #define PCNT_CNT_THRES0_U3_S 0 700 /** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0; 701 * This register is used to configure the thres1 value for unit 3. 702 */ 703 #define PCNT_CNT_THRES1_U3 0x0000FFFFU 704 #define PCNT_CNT_THRES1_U3_M (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S) 705 #define PCNT_CNT_THRES1_U3_V 0x0000FFFFU 706 #define PCNT_CNT_THRES1_U3_S 16 707 708 /** PCNT_U3_CONF2_REG register 709 * Configuration register 2 for unit 3 710 */ 711 #define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c) 712 /** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0; 713 * This register is used to configure the thr_h_lim value for unit 3. 714 */ 715 #define PCNT_CNT_H_LIM_U3 0x0000FFFFU 716 #define PCNT_CNT_H_LIM_U3_M (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S) 717 #define PCNT_CNT_H_LIM_U3_V 0x0000FFFFU 718 #define PCNT_CNT_H_LIM_U3_S 0 719 /** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0; 720 * This register is used to configure the thr_l_lim value for unit 3. 721 */ 722 #define PCNT_CNT_L_LIM_U3 0x0000FFFFU 723 #define PCNT_CNT_L_LIM_U3_M (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S) 724 #define PCNT_CNT_L_LIM_U3_V 0x0000FFFFU 725 #define PCNT_CNT_L_LIM_U3_S 16 726 727 /** PCNT_U0_CNT_REG register 728 * Counter value for unit 0 729 */ 730 #define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30) 731 /** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0; 732 * This register stores the current pulse count value for unit 0. 733 */ 734 #define PCNT_PULSE_CNT_U0 0x0000FFFFU 735 #define PCNT_PULSE_CNT_U0_M (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S) 736 #define PCNT_PULSE_CNT_U0_V 0x0000FFFFU 737 #define PCNT_PULSE_CNT_U0_S 0 738 739 /** PCNT_U1_CNT_REG register 740 * Counter value for unit 1 741 */ 742 #define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34) 743 /** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0; 744 * This register stores the current pulse count value for unit 1. 745 */ 746 #define PCNT_PULSE_CNT_U1 0x0000FFFFU 747 #define PCNT_PULSE_CNT_U1_M (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S) 748 #define PCNT_PULSE_CNT_U1_V 0x0000FFFFU 749 #define PCNT_PULSE_CNT_U1_S 0 750 751 /** PCNT_U2_CNT_REG register 752 * Counter value for unit 2 753 */ 754 #define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38) 755 /** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0; 756 * This register stores the current pulse count value for unit 2. 757 */ 758 #define PCNT_PULSE_CNT_U2 0x0000FFFFU 759 #define PCNT_PULSE_CNT_U2_M (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S) 760 #define PCNT_PULSE_CNT_U2_V 0x0000FFFFU 761 #define PCNT_PULSE_CNT_U2_S 0 762 763 /** PCNT_U3_CNT_REG register 764 * Counter value for unit 3 765 */ 766 #define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c) 767 /** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0; 768 * This register stores the current pulse count value for unit 3. 769 */ 770 #define PCNT_PULSE_CNT_U3 0x0000FFFFU 771 #define PCNT_PULSE_CNT_U3_M (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S) 772 #define PCNT_PULSE_CNT_U3_V 0x0000FFFFU 773 #define PCNT_PULSE_CNT_U3_S 0 774 775 /** PCNT_INT_RAW_REG register 776 * Interrupt raw status register 777 */ 778 #define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40) 779 /** PCNT_CNT_THR_EVENT_U0_INT_RAW : RO; bitpos: [0]; default: 0; 780 * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 781 */ 782 #define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) 783 #define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S) 784 #define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x00000001U 785 #define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 786 /** PCNT_CNT_THR_EVENT_U1_INT_RAW : RO; bitpos: [1]; default: 0; 787 * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 788 */ 789 #define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) 790 #define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S) 791 #define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x00000001U 792 #define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 793 /** PCNT_CNT_THR_EVENT_U2_INT_RAW : RO; bitpos: [2]; default: 0; 794 * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 795 */ 796 #define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) 797 #define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S) 798 #define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x00000001U 799 #define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 800 /** PCNT_CNT_THR_EVENT_U3_INT_RAW : RO; bitpos: [3]; default: 0; 801 * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 802 */ 803 #define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) 804 #define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S) 805 #define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x00000001U 806 #define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 807 808 /** PCNT_INT_ST_REG register 809 * Interrupt status register 810 */ 811 #define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44) 812 /** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0; 813 * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 814 */ 815 #define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) 816 #define PCNT_CNT_THR_EVENT_U0_INT_ST_M (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S) 817 #define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x00000001U 818 #define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 819 /** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0; 820 * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 821 */ 822 #define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) 823 #define PCNT_CNT_THR_EVENT_U1_INT_ST_M (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S) 824 #define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x00000001U 825 #define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 826 /** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0; 827 * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 828 */ 829 #define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) 830 #define PCNT_CNT_THR_EVENT_U2_INT_ST_M (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S) 831 #define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x00000001U 832 #define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 833 /** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0; 834 * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 835 */ 836 #define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) 837 #define PCNT_CNT_THR_EVENT_U3_INT_ST_M (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S) 838 #define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x00000001U 839 #define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 840 841 /** PCNT_INT_ENA_REG register 842 * Interrupt enable register 843 */ 844 #define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48) 845 /** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0; 846 * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 847 */ 848 #define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) 849 #define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S) 850 #define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x00000001U 851 #define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 852 /** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0; 853 * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 854 */ 855 #define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) 856 #define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S) 857 #define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x00000001U 858 #define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 859 /** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0; 860 * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 861 */ 862 #define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) 863 #define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S) 864 #define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x00000001U 865 #define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 866 /** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0; 867 * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 868 */ 869 #define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) 870 #define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S) 871 #define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x00000001U 872 #define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 873 874 /** PCNT_INT_CLR_REG register 875 * Interrupt clear register 876 */ 877 #define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c) 878 /** PCNT_CNT_THR_EVENT_U0_INT_CLR : WO; bitpos: [0]; default: 0; 879 * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 880 */ 881 #define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) 882 #define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S) 883 #define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x00000001U 884 #define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 885 /** PCNT_CNT_THR_EVENT_U1_INT_CLR : WO; bitpos: [1]; default: 0; 886 * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 887 */ 888 #define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) 889 #define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S) 890 #define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x00000001U 891 #define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 892 /** PCNT_CNT_THR_EVENT_U2_INT_CLR : WO; bitpos: [2]; default: 0; 893 * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 894 */ 895 #define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) 896 #define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S) 897 #define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x00000001U 898 #define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 899 /** PCNT_CNT_THR_EVENT_U3_INT_CLR : WO; bitpos: [3]; default: 0; 900 * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 901 */ 902 #define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) 903 #define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S) 904 #define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x00000001U 905 #define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 906 907 /** PCNT_U0_STATUS_REG register 908 * PNCT UNIT0 status register 909 */ 910 #define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50) 911 /** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0; 912 * The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases 913 * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter 914 * is negative. 3: pulse counter is positive. 915 */ 916 #define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003U 917 #define PCNT_CNT_THR_ZERO_MODE_U0_M (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S) 918 #define PCNT_CNT_THR_ZERO_MODE_U0_V 0x00000003U 919 #define PCNT_CNT_THR_ZERO_MODE_U0_S 0 920 /** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0; 921 * The latched value of thres1 event of PCNT_U0 when threshold event interrupt is 922 * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: 923 * others 924 */ 925 #define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) 926 #define PCNT_CNT_THR_THRES1_LAT_U0_M (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S) 927 #define PCNT_CNT_THR_THRES1_LAT_U0_V 0x00000001U 928 #define PCNT_CNT_THR_THRES1_LAT_U0_S 2 929 /** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0; 930 * The latched value of thres0 event of PCNT_U0 when threshold event interrupt is 931 * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: 932 * others 933 */ 934 #define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) 935 #define PCNT_CNT_THR_THRES0_LAT_U0_M (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S) 936 #define PCNT_CNT_THR_THRES0_LAT_U0_V 0x00000001U 937 #define PCNT_CNT_THR_THRES0_LAT_U0_S 3 938 /** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0; 939 * The latched value of low limit event of PCNT_U0 when threshold event interrupt is 940 * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is 941 * valid. 0: others 942 */ 943 #define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) 944 #define PCNT_CNT_THR_L_LIM_LAT_U0_M (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S) 945 #define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x00000001U 946 #define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 947 /** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0; 948 * The latched value of high limit event of PCNT_U0 when threshold event interrupt is 949 * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is 950 * valid. 0: others 951 */ 952 #define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) 953 #define PCNT_CNT_THR_H_LIM_LAT_U0_M (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S) 954 #define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x00000001U 955 #define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 956 /** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0; 957 * The latched value of zero threshold event of PCNT_U0 when threshold event interrupt 958 * is valid. 1: the current pulse counter equals to 0 and zero threshold event is 959 * valid. 0: others 960 */ 961 #define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) 962 #define PCNT_CNT_THR_ZERO_LAT_U0_M (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S) 963 #define PCNT_CNT_THR_ZERO_LAT_U0_V 0x00000001U 964 #define PCNT_CNT_THR_ZERO_LAT_U0_S 6 965 966 /** PCNT_U1_STATUS_REG register 967 * PNCT UNIT1 status register 968 */ 969 #define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54) 970 /** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0; 971 * The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases 972 * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter 973 * is negative. 3: pulse counter is positive. 974 */ 975 #define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003U 976 #define PCNT_CNT_THR_ZERO_MODE_U1_M (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S) 977 #define PCNT_CNT_THR_ZERO_MODE_U1_V 0x00000003U 978 #define PCNT_CNT_THR_ZERO_MODE_U1_S 0 979 /** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0; 980 * The latched value of thres1 event of PCNT_U1 when threshold event interrupt is 981 * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: 982 * others 983 */ 984 #define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) 985 #define PCNT_CNT_THR_THRES1_LAT_U1_M (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S) 986 #define PCNT_CNT_THR_THRES1_LAT_U1_V 0x00000001U 987 #define PCNT_CNT_THR_THRES1_LAT_U1_S 2 988 /** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0; 989 * The latched value of thres0 event of PCNT_U1 when threshold event interrupt is 990 * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: 991 * others 992 */ 993 #define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) 994 #define PCNT_CNT_THR_THRES0_LAT_U1_M (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S) 995 #define PCNT_CNT_THR_THRES0_LAT_U1_V 0x00000001U 996 #define PCNT_CNT_THR_THRES0_LAT_U1_S 3 997 /** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0; 998 * The latched value of low limit event of PCNT_U1 when threshold event interrupt is 999 * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is 1000 * valid. 0: others 1001 */ 1002 #define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) 1003 #define PCNT_CNT_THR_L_LIM_LAT_U1_M (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S) 1004 #define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x00000001U 1005 #define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 1006 /** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0; 1007 * The latched value of high limit event of PCNT_U1 when threshold event interrupt is 1008 * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is 1009 * valid. 0: others 1010 */ 1011 #define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) 1012 #define PCNT_CNT_THR_H_LIM_LAT_U1_M (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S) 1013 #define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x00000001U 1014 #define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 1015 /** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0; 1016 * The latched value of zero threshold event of PCNT_U1 when threshold event interrupt 1017 * is valid. 1: the current pulse counter equals to 0 and zero threshold event is 1018 * valid. 0: others 1019 */ 1020 #define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) 1021 #define PCNT_CNT_THR_ZERO_LAT_U1_M (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S) 1022 #define PCNT_CNT_THR_ZERO_LAT_U1_V 0x00000001U 1023 #define PCNT_CNT_THR_ZERO_LAT_U1_S 6 1024 1025 /** PCNT_U2_STATUS_REG register 1026 * PNCT UNIT2 status register 1027 */ 1028 #define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58) 1029 /** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0; 1030 * The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases 1031 * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter 1032 * is negative. 3: pulse counter is positive. 1033 */ 1034 #define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003U 1035 #define PCNT_CNT_THR_ZERO_MODE_U2_M (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S) 1036 #define PCNT_CNT_THR_ZERO_MODE_U2_V 0x00000003U 1037 #define PCNT_CNT_THR_ZERO_MODE_U2_S 0 1038 /** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0; 1039 * The latched value of thres1 event of PCNT_U2 when threshold event interrupt is 1040 * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: 1041 * others 1042 */ 1043 #define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) 1044 #define PCNT_CNT_THR_THRES1_LAT_U2_M (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S) 1045 #define PCNT_CNT_THR_THRES1_LAT_U2_V 0x00000001U 1046 #define PCNT_CNT_THR_THRES1_LAT_U2_S 2 1047 /** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0; 1048 * The latched value of thres0 event of PCNT_U2 when threshold event interrupt is 1049 * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: 1050 * others 1051 */ 1052 #define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) 1053 #define PCNT_CNT_THR_THRES0_LAT_U2_M (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S) 1054 #define PCNT_CNT_THR_THRES0_LAT_U2_V 0x00000001U 1055 #define PCNT_CNT_THR_THRES0_LAT_U2_S 3 1056 /** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0; 1057 * The latched value of low limit event of PCNT_U2 when threshold event interrupt is 1058 * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is 1059 * valid. 0: others 1060 */ 1061 #define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) 1062 #define PCNT_CNT_THR_L_LIM_LAT_U2_M (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S) 1063 #define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x00000001U 1064 #define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 1065 /** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0; 1066 * The latched value of high limit event of PCNT_U2 when threshold event interrupt is 1067 * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is 1068 * valid. 0: others 1069 */ 1070 #define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) 1071 #define PCNT_CNT_THR_H_LIM_LAT_U2_M (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S) 1072 #define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x00000001U 1073 #define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 1074 /** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0; 1075 * The latched value of zero threshold event of PCNT_U2 when threshold event interrupt 1076 * is valid. 1: the current pulse counter equals to 0 and zero threshold event is 1077 * valid. 0: others 1078 */ 1079 #define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) 1080 #define PCNT_CNT_THR_ZERO_LAT_U2_M (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S) 1081 #define PCNT_CNT_THR_ZERO_LAT_U2_V 0x00000001U 1082 #define PCNT_CNT_THR_ZERO_LAT_U2_S 6 1083 1084 /** PCNT_U3_STATUS_REG register 1085 * PNCT UNIT3 status register 1086 */ 1087 #define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c) 1088 /** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0; 1089 * The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases 1090 * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter 1091 * is negative. 3: pulse counter is positive. 1092 */ 1093 #define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003U 1094 #define PCNT_CNT_THR_ZERO_MODE_U3_M (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S) 1095 #define PCNT_CNT_THR_ZERO_MODE_U3_V 0x00000003U 1096 #define PCNT_CNT_THR_ZERO_MODE_U3_S 0 1097 /** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0; 1098 * The latched value of thres1 event of PCNT_U3 when threshold event interrupt is 1099 * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: 1100 * others 1101 */ 1102 #define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) 1103 #define PCNT_CNT_THR_THRES1_LAT_U3_M (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S) 1104 #define PCNT_CNT_THR_THRES1_LAT_U3_V 0x00000001U 1105 #define PCNT_CNT_THR_THRES1_LAT_U3_S 2 1106 /** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0; 1107 * The latched value of thres0 event of PCNT_U3 when threshold event interrupt is 1108 * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: 1109 * others 1110 */ 1111 #define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) 1112 #define PCNT_CNT_THR_THRES0_LAT_U3_M (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S) 1113 #define PCNT_CNT_THR_THRES0_LAT_U3_V 0x00000001U 1114 #define PCNT_CNT_THR_THRES0_LAT_U3_S 3 1115 /** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0; 1116 * The latched value of low limit event of PCNT_U3 when threshold event interrupt is 1117 * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is 1118 * valid. 0: others 1119 */ 1120 #define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) 1121 #define PCNT_CNT_THR_L_LIM_LAT_U3_M (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S) 1122 #define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x00000001U 1123 #define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 1124 /** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0; 1125 * The latched value of high limit event of PCNT_U3 when threshold event interrupt is 1126 * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is 1127 * valid. 0: others 1128 */ 1129 #define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) 1130 #define PCNT_CNT_THR_H_LIM_LAT_U3_M (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S) 1131 #define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x00000001U 1132 #define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 1133 /** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0; 1134 * The latched value of zero threshold event of PCNT_U3 when threshold event interrupt 1135 * is valid. 1: the current pulse counter equals to 0 and zero threshold event is 1136 * valid. 0: others 1137 */ 1138 #define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) 1139 #define PCNT_CNT_THR_ZERO_LAT_U3_M (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S) 1140 #define PCNT_CNT_THR_ZERO_LAT_U3_V 0x00000001U 1141 #define PCNT_CNT_THR_ZERO_LAT_U3_S 6 1142 1143 /** PCNT_CTRL_REG register 1144 * Control register for all counters 1145 */ 1146 #define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60) 1147 /** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1; 1148 * Set this bit to clear unit 0's counter. 1149 */ 1150 #define PCNT_PULSE_CNT_RST_U0 (BIT(0)) 1151 #define PCNT_PULSE_CNT_RST_U0_M (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S) 1152 #define PCNT_PULSE_CNT_RST_U0_V 0x00000001U 1153 #define PCNT_PULSE_CNT_RST_U0_S 0 1154 /** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0; 1155 * Set this bit to freeze unit 0's counter. 1156 */ 1157 #define PCNT_CNT_PAUSE_U0 (BIT(1)) 1158 #define PCNT_CNT_PAUSE_U0_M (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S) 1159 #define PCNT_CNT_PAUSE_U0_V 0x00000001U 1160 #define PCNT_CNT_PAUSE_U0_S 1 1161 /** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1; 1162 * Set this bit to clear unit 1's counter. 1163 */ 1164 #define PCNT_PULSE_CNT_RST_U1 (BIT(2)) 1165 #define PCNT_PULSE_CNT_RST_U1_M (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S) 1166 #define PCNT_PULSE_CNT_RST_U1_V 0x00000001U 1167 #define PCNT_PULSE_CNT_RST_U1_S 2 1168 /** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0; 1169 * Set this bit to freeze unit 1's counter. 1170 */ 1171 #define PCNT_CNT_PAUSE_U1 (BIT(3)) 1172 #define PCNT_CNT_PAUSE_U1_M (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S) 1173 #define PCNT_CNT_PAUSE_U1_V 0x00000001U 1174 #define PCNT_CNT_PAUSE_U1_S 3 1175 /** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1; 1176 * Set this bit to clear unit 2's counter. 1177 */ 1178 #define PCNT_PULSE_CNT_RST_U2 (BIT(4)) 1179 #define PCNT_PULSE_CNT_RST_U2_M (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S) 1180 #define PCNT_PULSE_CNT_RST_U2_V 0x00000001U 1181 #define PCNT_PULSE_CNT_RST_U2_S 4 1182 /** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0; 1183 * Set this bit to freeze unit 2's counter. 1184 */ 1185 #define PCNT_CNT_PAUSE_U2 (BIT(5)) 1186 #define PCNT_CNT_PAUSE_U2_M (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S) 1187 #define PCNT_CNT_PAUSE_U2_V 0x00000001U 1188 #define PCNT_CNT_PAUSE_U2_S 5 1189 /** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1; 1190 * Set this bit to clear unit 3's counter. 1191 */ 1192 #define PCNT_PULSE_CNT_RST_U3 (BIT(6)) 1193 #define PCNT_PULSE_CNT_RST_U3_M (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S) 1194 #define PCNT_PULSE_CNT_RST_U3_V 0x00000001U 1195 #define PCNT_PULSE_CNT_RST_U3_S 6 1196 /** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0; 1197 * Set this bit to freeze unit 3's counter. 1198 */ 1199 #define PCNT_CNT_PAUSE_U3 (BIT(7)) 1200 #define PCNT_CNT_PAUSE_U3_M (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S) 1201 #define PCNT_CNT_PAUSE_U3_V 0x00000001U 1202 #define PCNT_CNT_PAUSE_U3_S 7 1203 /** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0; 1204 * The registers clock gate enable signal of PCNT module. 1: the registers can be read 1205 * and written by application. 0: the registers can not be read or written by 1206 * application 1207 */ 1208 #define PCNT_CLK_EN (BIT(16)) 1209 #define PCNT_CLK_EN_M (PCNT_CLK_EN_V << PCNT_CLK_EN_S) 1210 #define PCNT_CLK_EN_V 0x00000001U 1211 #define PCNT_CLK_EN_S 16 1212 1213 /** PCNT_DATE_REG register 1214 * PCNT version control register 1215 */ 1216 #define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc) 1217 /** PCNT_DATE : R/W; bitpos: [31:0]; default: 419898881; 1218 * This is the PCNT version control register. 1219 */ 1220 #define PCNT_DATE 0xFFFFFFFFU 1221 #define PCNT_DATE_M (PCNT_DATE_V << PCNT_DATE_S) 1222 #define PCNT_DATE_V 0xFFFFFFFFU 1223 #define PCNT_DATE_S 0 1224 1225 #ifdef __cplusplus 1226 } 1227 #endif 1228
