1 /**
2  * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #ifdef __cplusplus
9 extern "C" {
10 #endif
11 
12 #define EFUSE_WRITE_OP_CODE 0x5a5a
13 #define EFUSE_READ_OP_CODE 0x5aa5
14 
15 #define EFUSE_PKG_VERSION_ESP32S3       0 // QFN56
16 #define EFUSE_PKG_VERSION_ESP32S3PICO   1 // LGA56
17 
18 /** EFUSE_RD_MAC_SPI_SYS_2_REG register
19  *  BLOCK1 data register 2.
20  */
21 // #define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
22 /* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
23 /*description: Stores the first part of SPI_PAD_CONF..*/
24 #define EFUSE_SPI_PAD_CONF_1    0xFFFFFFFF
25 #define EFUSE_SPI_PAD_CONF_1_M  ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S))
26 #define EFUSE_SPI_PAD_CONF_1_V  0xFFFFFFFF
27 #define EFUSE_SPI_PAD_CONF_1_S  0
28 
29 /** EFUSE_RD_MAC_SPI_SYS_3_REG register
30  *  BLOCK1 data register 3.
31  */
32 //#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
33 /* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
34 /*description: Stores the second part of SPI_PAD_CONF..*/
35 #define EFUSE_SPI_PAD_CONF_2    0x0003FFFF
36 #define EFUSE_SPI_PAD_CONF_2_M  ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S))
37 #define EFUSE_SPI_PAD_CONF_2_V  0x3FFFF
38 #define EFUSE_SPI_PAD_CONF_2_S  0
39 
40 #ifdef __cplusplus
41 }
42 #endif
43