1 /**
2  * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdint.h>
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 /** Group: Tee mode control register */
14 /** Type of m0_mode_ctrl register
15  *  Tee mode control register
16  */
17 typedef union {
18     struct {
19         /** m0_mode : R/W; bitpos: [1:0]; default: 0;
20          *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
21          *  tee_mode
22          */
23         uint32_t m0_mode:2;
24         uint32_t reserved_2:30;
25     };
26     uint32_t val;
27 } tee_m0_mode_ctrl_reg_t;
28 
29 /** Type of m1_mode_ctrl register
30  *  Tee mode control register
31  */
32 typedef union {
33     struct {
34         /** m1_mode : R/W; bitpos: [1:0]; default: 3;
35          *  M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
36          *  tee_mode
37          */
38         uint32_t m1_mode:2;
39         uint32_t reserved_2:30;
40     };
41     uint32_t val;
42 } tee_m1_mode_ctrl_reg_t;
43 
44 /** Type of m2_mode_ctrl register
45  *  Tee mode control register
46  */
47 typedef union {
48     struct {
49         /** m2_mode : R/W; bitpos: [1:0]; default: 0;
50          *  M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
51          *  tee_mode
52          */
53         uint32_t m2_mode:2;
54         uint32_t reserved_2:30;
55     };
56     uint32_t val;
57 } tee_m2_mode_ctrl_reg_t;
58 
59 /** Type of m3_mode_ctrl register
60  *  Tee mode control register
61  */
62 typedef union {
63     struct {
64         /** m3_mode : R/W; bitpos: [1:0]; default: 3;
65          *  M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
66          *  tee_mode
67          */
68         uint32_t m3_mode:2;
69         uint32_t reserved_2:30;
70     };
71     uint32_t val;
72 } tee_m3_mode_ctrl_reg_t;
73 
74 /** Type of m4_mode_ctrl register
75  *  Tee mode control register
76  */
77 typedef union {
78     struct {
79         /** m4_mode : R/W; bitpos: [1:0]; default: 3;
80          *  M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
81          *  tee_mode
82          */
83         uint32_t m4_mode:2;
84         uint32_t reserved_2:30;
85     };
86     uint32_t val;
87 } tee_m4_mode_ctrl_reg_t;
88 
89 /** Type of m5_mode_ctrl register
90  *  Tee mode control register
91  */
92 typedef union {
93     struct {
94         /** m5_mode : R/W; bitpos: [1:0]; default: 3;
95          *  M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
96          *  tee_mode
97          */
98         uint32_t m5_mode:2;
99         uint32_t reserved_2:30;
100     };
101     uint32_t val;
102 } tee_m5_mode_ctrl_reg_t;
103 
104 /** Type of m6_mode_ctrl register
105  *  Tee mode control register
106  */
107 typedef union {
108     struct {
109         /** m6_mode : R/W; bitpos: [1:0]; default: 3;
110          *  M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
111          *  tee_mode
112          */
113         uint32_t m6_mode:2;
114         uint32_t reserved_2:30;
115     };
116     uint32_t val;
117 } tee_m6_mode_ctrl_reg_t;
118 
119 /** Type of m7_mode_ctrl register
120  *  Tee mode control register
121  */
122 typedef union {
123     struct {
124         /** m7_mode : R/W; bitpos: [1:0]; default: 3;
125          *  M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
126          *  tee_mode
127          */
128         uint32_t m7_mode:2;
129         uint32_t reserved_2:30;
130     };
131     uint32_t val;
132 } tee_m7_mode_ctrl_reg_t;
133 
134 /** Type of m8_mode_ctrl register
135  *  Tee mode control register
136  */
137 typedef union {
138     struct {
139         /** m8_mode : R/W; bitpos: [1:0]; default: 3;
140          *  M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
141          *  tee_mode
142          */
143         uint32_t m8_mode:2;
144         uint32_t reserved_2:30;
145     };
146     uint32_t val;
147 } tee_m8_mode_ctrl_reg_t;
148 
149 /** Type of m9_mode_ctrl register
150  *  Tee mode control register
151  */
152 typedef union {
153     struct {
154         /** m9_mode : R/W; bitpos: [1:0]; default: 3;
155          *  M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
156          *  tee_mode
157          */
158         uint32_t m9_mode:2;
159         uint32_t reserved_2:30;
160     };
161     uint32_t val;
162 } tee_m9_mode_ctrl_reg_t;
163 
164 /** Type of m10_mode_ctrl register
165  *  Tee mode control register
166  */
167 typedef union {
168     struct {
169         /** m10_mode : R/W; bitpos: [1:0]; default: 3;
170          *  M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
171          *  tee_mode
172          */
173         uint32_t m10_mode:2;
174         uint32_t reserved_2:30;
175     };
176     uint32_t val;
177 } tee_m10_mode_ctrl_reg_t;
178 
179 /** Type of m11_mode_ctrl register
180  *  Tee mode control register
181  */
182 typedef union {
183     struct {
184         /** m11_mode : R/W; bitpos: [1:0]; default: 3;
185          *  M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
186          *  tee_mode
187          */
188         uint32_t m11_mode:2;
189         uint32_t reserved_2:30;
190     };
191     uint32_t val;
192 } tee_m11_mode_ctrl_reg_t;
193 
194 /** Type of m12_mode_ctrl register
195  *  Tee mode control register
196  */
197 typedef union {
198     struct {
199         /** m12_mode : R/W; bitpos: [1:0]; default: 3;
200          *  M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
201          *  tee_mode
202          */
203         uint32_t m12_mode:2;
204         uint32_t reserved_2:30;
205     };
206     uint32_t val;
207 } tee_m12_mode_ctrl_reg_t;
208 
209 /** Type of m13_mode_ctrl register
210  *  Tee mode control register
211  */
212 typedef union {
213     struct {
214         /** m13_mode : R/W; bitpos: [1:0]; default: 3;
215          *  M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
216          *  tee_mode
217          */
218         uint32_t m13_mode:2;
219         uint32_t reserved_2:30;
220     };
221     uint32_t val;
222 } tee_m13_mode_ctrl_reg_t;
223 
224 /** Type of m14_mode_ctrl register
225  *  Tee mode control register
226  */
227 typedef union {
228     struct {
229         /** m14_mode : R/W; bitpos: [1:0]; default: 3;
230          *  M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
231          *  tee_mode
232          */
233         uint32_t m14_mode:2;
234         uint32_t reserved_2:30;
235     };
236     uint32_t val;
237 } tee_m14_mode_ctrl_reg_t;
238 
239 /** Type of m15_mode_ctrl register
240  *  Tee mode control register
241  */
242 typedef union {
243     struct {
244         /** m15_mode : R/W; bitpos: [1:0]; default: 3;
245          *  M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
246          *  tee_mode
247          */
248         uint32_t m15_mode:2;
249         uint32_t reserved_2:30;
250     };
251     uint32_t val;
252 } tee_m15_mode_ctrl_reg_t;
253 
254 /** Type of m16_mode_ctrl register
255  *  Tee mode control register
256  */
257 typedef union {
258     struct {
259         /** m16_mode : R/W; bitpos: [1:0]; default: 3;
260          *  M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
261          *  tee_mode
262          */
263         uint32_t m16_mode:2;
264         uint32_t reserved_2:30;
265     };
266     uint32_t val;
267 } tee_m16_mode_ctrl_reg_t;
268 
269 /** Type of m17_mode_ctrl register
270  *  Tee mode control register
271  */
272 typedef union {
273     struct {
274         /** m17_mode : R/W; bitpos: [1:0]; default: 3;
275          *  M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
276          *  tee_mode
277          */
278         uint32_t m17_mode:2;
279         uint32_t reserved_2:30;
280     };
281     uint32_t val;
282 } tee_m17_mode_ctrl_reg_t;
283 
284 /** Type of m18_mode_ctrl register
285  *  Tee mode control register
286  */
287 typedef union {
288     struct {
289         /** m18_mode : R/W; bitpos: [1:0]; default: 3;
290          *  M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
291          *  tee_mode
292          */
293         uint32_t m18_mode:2;
294         uint32_t reserved_2:30;
295     };
296     uint32_t val;
297 } tee_m18_mode_ctrl_reg_t;
298 
299 /** Type of m19_mode_ctrl register
300  *  Tee mode control register
301  */
302 typedef union {
303     struct {
304         /** m19_mode : R/W; bitpos: [1:0]; default: 3;
305          *  M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
306          *  tee_mode
307          */
308         uint32_t m19_mode:2;
309         uint32_t reserved_2:30;
310     };
311     uint32_t val;
312 } tee_m19_mode_ctrl_reg_t;
313 
314 /** Type of m20_mode_ctrl register
315  *  Tee mode control register
316  */
317 typedef union {
318     struct {
319         /** m20_mode : R/W; bitpos: [1:0]; default: 3;
320          *  M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
321          *  tee_mode
322          */
323         uint32_t m20_mode:2;
324         uint32_t reserved_2:30;
325     };
326     uint32_t val;
327 } tee_m20_mode_ctrl_reg_t;
328 
329 /** Type of m21_mode_ctrl register
330  *  Tee mode control register
331  */
332 typedef union {
333     struct {
334         /** m21_mode : R/W; bitpos: [1:0]; default: 3;
335          *  M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
336          *  tee_mode
337          */
338         uint32_t m21_mode:2;
339         uint32_t reserved_2:30;
340     };
341     uint32_t val;
342 } tee_m21_mode_ctrl_reg_t;
343 
344 /** Type of m22_mode_ctrl register
345  *  Tee mode control register
346  */
347 typedef union {
348     struct {
349         /** m22_mode : R/W; bitpos: [1:0]; default: 3;
350          *  M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
351          *  tee_mode
352          */
353         uint32_t m22_mode:2;
354         uint32_t reserved_2:30;
355     };
356     uint32_t val;
357 } tee_m22_mode_ctrl_reg_t;
358 
359 /** Type of m23_mode_ctrl register
360  *  Tee mode control register
361  */
362 typedef union {
363     struct {
364         /** m23_mode : R/W; bitpos: [1:0]; default: 3;
365          *  M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
366          *  tee_mode
367          */
368         uint32_t m23_mode:2;
369         uint32_t reserved_2:30;
370     };
371     uint32_t val;
372 } tee_m23_mode_ctrl_reg_t;
373 
374 /** Type of m24_mode_ctrl register
375  *  Tee mode control register
376  */
377 typedef union {
378     struct {
379         /** m24_mode : R/W; bitpos: [1:0]; default: 3;
380          *  M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
381          *  tee_mode
382          */
383         uint32_t m24_mode:2;
384         uint32_t reserved_2:30;
385     };
386     uint32_t val;
387 } tee_m24_mode_ctrl_reg_t;
388 
389 /** Type of m25_mode_ctrl register
390  *  Tee mode control register
391  */
392 typedef union {
393     struct {
394         /** m25_mode : R/W; bitpos: [1:0]; default: 3;
395          *  M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
396          *  tee_mode
397          */
398         uint32_t m25_mode:2;
399         uint32_t reserved_2:30;
400     };
401     uint32_t val;
402 } tee_m25_mode_ctrl_reg_t;
403 
404 /** Type of m26_mode_ctrl register
405  *  Tee mode control register
406  */
407 typedef union {
408     struct {
409         /** m26_mode : R/W; bitpos: [1:0]; default: 3;
410          *  M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
411          *  tee_mode
412          */
413         uint32_t m26_mode:2;
414         uint32_t reserved_2:30;
415     };
416     uint32_t val;
417 } tee_m26_mode_ctrl_reg_t;
418 
419 /** Type of m27_mode_ctrl register
420  *  Tee mode control register
421  */
422 typedef union {
423     struct {
424         /** m27_mode : R/W; bitpos: [1:0]; default: 3;
425          *  M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
426          *  tee_mode
427          */
428         uint32_t m27_mode:2;
429         uint32_t reserved_2:30;
430     };
431     uint32_t val;
432 } tee_m27_mode_ctrl_reg_t;
433 
434 /** Type of m28_mode_ctrl register
435  *  Tee mode control register
436  */
437 typedef union {
438     struct {
439         /** m28_mode : R/W; bitpos: [1:0]; default: 3;
440          *  M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
441          *  tee_mode
442          */
443         uint32_t m28_mode:2;
444         uint32_t reserved_2:30;
445     };
446     uint32_t val;
447 } tee_m28_mode_ctrl_reg_t;
448 
449 /** Type of m29_mode_ctrl register
450  *  Tee mode control register
451  */
452 typedef union {
453     struct {
454         /** m29_mode : R/W; bitpos: [1:0]; default: 3;
455          *  M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
456          *  tee_mode
457          */
458         uint32_t m29_mode:2;
459         uint32_t reserved_2:30;
460     };
461     uint32_t val;
462 } tee_m29_mode_ctrl_reg_t;
463 
464 /** Type of m30_mode_ctrl register
465  *  Tee mode control register
466  */
467 typedef union {
468     struct {
469         /** m30_mode : R/W; bitpos: [1:0]; default: 3;
470          *  M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
471          *  tee_mode
472          */
473         uint32_t m30_mode:2;
474         uint32_t reserved_2:30;
475     };
476     uint32_t val;
477 } tee_m30_mode_ctrl_reg_t;
478 
479 /** Type of m31_mode_ctrl register
480  *  Tee mode control register
481  */
482 typedef union {
483     struct {
484         /** m31_mode : R/W; bitpos: [1:0]; default: 3;
485          *  M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
486          *  tee_mode
487          */
488         uint32_t m31_mode:2;
489         uint32_t reserved_2:30;
490     };
491     uint32_t val;
492 } tee_m31_mode_ctrl_reg_t;
493 
494 
495 /** Group: clock gating register */
496 /** Type of clock_gate register
497  *  Clock gating register
498  */
499 typedef union {
500     struct {
501         /** clk_en : R/W; bitpos: [0]; default: 1;
502          *  reg_clk_en
503          */
504         uint32_t clk_en:1;
505         uint32_t reserved_1:31;
506     };
507     uint32_t val;
508 } tee_clock_gate_reg_t;
509 
510 
511 /** Group: Version register */
512 /** Type of date register
513  *  Version register
514  */
515 typedef union {
516     struct {
517         /** date_reg : R/W; bitpos: [27:0]; default: 35672706;
518          *  reg_tee_date
519          */
520         uint32_t date_reg:28;
521         uint32_t reserved_28:4;
522     };
523     uint32_t val;
524 } tee_date_reg_t;
525 
526 
527 typedef struct {
528     volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
529     volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
530     volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;
531     volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl;
532     volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl;
533     volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl;
534     volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl;
535     volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl;
536     volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl;
537     volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl;
538     volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl;
539     volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl;
540     volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl;
541     volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl;
542     volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl;
543     volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl;
544     volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl;
545     volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl;
546     volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl;
547     volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl;
548     volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl;
549     volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl;
550     volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl;
551     volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl;
552     volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl;
553     volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl;
554     volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl;
555     volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl;
556     volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl;
557     volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl;
558     volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl;
559     volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl;
560     volatile tee_clock_gate_reg_t clock_gate;
561     uint32_t reserved_084[990];
562     volatile tee_date_reg_t date;
563 } tee_dev_t;
564 
565 extern tee_dev_t TEE;
566 
567 #ifndef __cplusplus
568 _Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure");
569 #endif
570 
571 #ifdef __cplusplus
572 }
573 #endif
574