1 /*
2  * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #pragma once
8 
9 #include "soc/soc.h"
10 #include "esp32h2/rom/cache.h"
11 
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15 
16 typedef union {
17     struct {
18         uint32_t cat0       : 2;
19         uint32_t cat1       : 2;
20         uint32_t cat2       : 2;
21         uint32_t res0       : 8;
22         uint32_t splitaddr  : 8;
23         uint32_t res1       : 10;
24     };
25     uint32_t val;
26 } constrain_reg_fields_t;
27 
28 #ifndef I_D_SRAM_SEGMENT_SIZE
29 #define I_D_SRAM_SEGMENT_SIZE       0x20000
30 #endif
31 
32 #define I_D_SPLIT_LINE_SHIFT        0x9
33 #define I_D_FAULT_ADDR_SHIFT        0x2
34 
35 #define DRAM_SRAM_START             0x3FC7C000
36 
37 //IRAM0
38 
39 //16kB (ICACHE)
40 #define IRAM0_SRAM_LEVEL_0_LOW      SOC_IRAM_LOW //0x40370000
41 #define IRAM0_SRAM_LEVEL_0_HIGH     (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
42 
43 //128kB (LEVEL 1)
44 #define IRAM0_SRAM_LEVEL_1_LOW      (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
45 #define IRAM0_SRAM_LEVEL_1_HIGH     (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
46 
47 //128kB (LEVEL 2)
48 #define IRAM0_SRAM_LEVEL_2_LOW      (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
49 #define IRAM0_SRAM_LEVEL_2_HIGH     (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
50 
51 //128kB (LEVEL 3)
52 #define IRAM0_SRAM_LEVEL_3_LOW      (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
53 #define IRAM0_SRAM_LEVEL_3_HIGH     (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
54 
55 //permission bits
56 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R  0x1
57 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W  0x2
58 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F  0x4
59 
60 //DRAM0
61 
62 //16kB ICACHE not available from DRAM0
63 
64 //128kB (LEVEL 1)
65 #define DRAM0_SRAM_LEVEL_1_LOW      SOC_DRAM_LOW //0x3FC80000
66 #define DRAM0_SRAM_LEVEL_1_HIGH     (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
67 
68 //128kB (LEVEL 2)
69 #define DRAM0_SRAM_LEVEL_2_LOW      (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
70 #define DRAM0_SRAM_LEVEL_2_HIGH     (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
71 
72 //128kB (LEVEL 3)
73 #define DRAM0_SRAM_LEVEL_3_LOW      (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
74 #define DRAM0_SRAM_LEVEL_3_HIGH     (DRAM0_SRAM_LEVEL_3_LOW  + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
75 
76 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R  0x1
77 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W  0x2
78 
79 //RTC FAST
80 
81 //permission bits
82 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W  0x1
83 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R  0x2
84 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F  0x4
85 
86 #define AREA_LOW                                                0
87 #define AREA_HIGH                                               1
88 
89 #ifdef __cplusplus
90 }
91 #endif
92