1 /**
2  * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdint.h>
9 #include "soc/soc.h"
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13 
14 /** MEM_MONITOR_LOG_SETTING_REG register
15  *  log config regsiter
16  */
17 #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
18 /** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
19  *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu
20  */
21 #define MEM_MONITOR_LOG_ENA    0x00000007U
22 #define MEM_MONITOR_LOG_ENA_M  (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
23 #define MEM_MONITOR_LOG_ENA_V  0x00000007U
24 #define MEM_MONITOR_LOG_ENA_S  0
25 /** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
26  *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
27  *  HALFWORD monitor, 4'b1000: BYTE monitor.
28  */
29 #define MEM_MONITOR_LOG_MODE    0x0000000FU
30 #define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
31 #define MEM_MONITOR_LOG_MODE_V  0x0000000FU
32 #define MEM_MONITOR_LOG_MODE_S  3
33 /** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
34  *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
35  */
36 #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(7))
37 #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
38 #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
39 #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
40 
41 /** MEM_MONITOR_LOG_CHECK_DATA_REG register
42  *  check data regsiter
43  */
44 #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
45 /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
46  *  The special check data, when write this special data, it will trigger logging.
47  */
48 #define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
49 #define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
50 #define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
51 #define MEM_MONITOR_LOG_CHECK_DATA_S  0
52 
53 /** MEM_MONITOR_LOG_DATA_MASK_REG register
54  *  check data mask register
55  */
56 #define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
57 /** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
58  *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
59  *  mask second byte, and so on.
60  */
61 #define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
62 #define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
63 #define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
64 #define MEM_MONITOR_LOG_DATA_MASK_S  0
65 
66 /** MEM_MONITOR_LOG_MIN_REG register
67  *  log boundary regsiter
68  */
69 #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
70 /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
71  *  the min address of log range
72  */
73 #define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
74 #define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
75 #define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
76 #define MEM_MONITOR_LOG_MIN_S  0
77 
78 /** MEM_MONITOR_LOG_MAX_REG register
79  *  log boundary regsiter
80  */
81 #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
82 /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
83  *  the max address of log range
84  */
85 #define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
86 #define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
87 #define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
88 #define MEM_MONITOR_LOG_MAX_S  0
89 
90 /** MEM_MONITOR_LOG_MEM_START_REG register
91  *  log message store range register
92  */
93 #define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
94 /** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
95  *  the start address of writing logging message
96  */
97 #define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
98 #define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
99 #define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
100 #define MEM_MONITOR_LOG_MEM_START_S  0
101 
102 /** MEM_MONITOR_LOG_MEM_END_REG register
103  *  log message store range register
104  */
105 #define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
106 /** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
107  *  the end address of writing logging message
108  */
109 #define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
110 #define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
111 #define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
112 #define MEM_MONITOR_LOG_MEM_END_S  0
113 
114 /** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
115  *  current writing address.
116  */
117 #define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
118 /** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
119  *  means next writing address
120  */
121 #define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
122 #define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
123 #define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
124 #define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
125 
126 /** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
127  *  writing address update
128  */
129 #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
130 /** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
131  *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
132  *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
133  */
134 #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
135 #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
136 #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
137 #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
138 
139 /** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
140  *  full flag status register
141  */
142 #define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
143 /** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
144  *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
145  */
146 #define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
147 #define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
148 #define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
149 #define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
150 /** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
151  *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
152  */
153 #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
154 #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
155 #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
156 #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
157 
158 /** MEM_MONITOR_CLOCK_GATE_REG register
159  *  clock gate force on register
160  */
161 #define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
162 /** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
163  *  Set 1 to force on the clk of mem_monitor register
164  */
165 #define MEM_MONITOR_CLK_EN    (BIT(0))
166 #define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
167 #define MEM_MONITOR_CLK_EN_V  0x00000001U
168 #define MEM_MONITOR_CLK_EN_S  0
169 
170 /** MEM_MONITOR_DATE_REG register
171  *  version register
172  */
173 #define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
174 /** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
175  *  version register
176  */
177 #define MEM_MONITOR_DATE    0x0FFFFFFFU
178 #define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
179 #define MEM_MONITOR_DATE_V  0x0FFFFFFFU
180 #define MEM_MONITOR_DATE_S  0
181 
182 #ifdef __cplusplus
183 }
184 #endif
185