1 /**
2  * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 /**
9  * @file lpperi_rev1_2_struct.h
10  * @brief Applicable to the ESP32-H2 that chip revision >= 1.2.
11  */
12 
13 #include <stdint.h>
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17 
18 /** Group: configure_register */
19 /** Type of clk_en register
20  *  need_des
21  */
22 typedef union {
23     struct {
24         uint32_t reserved_0:24;
25         /** rng_ck_en : R/W; bitpos: [24]; default: 1;
26          *  need_des
27          */
28         uint32_t rng_ck_en:1;
29         /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
30          *  need_des
31          */
32         uint32_t otp_dbg_ck_en:1;
33         /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1;
34          *  need_des
35          */
36         uint32_t lp_uart_ck_en:1;
37         /** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
38          *  need_des
39          */
40         uint32_t lp_io_ck_en:1;
41         /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1;
42          *  need_des
43          */
44         uint32_t lp_ext_i2c_ck_en:1;
45         /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1;
46          *  need_des
47          */
48         uint32_t lp_ana_i2c_ck_en:1;
49         /** efuse_ck_en : R/W; bitpos: [30]; default: 1;
50          *  need_des
51          */
52         uint32_t efuse_ck_en:1;
53         /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0;
54          *  need_des
55          */
56         uint32_t lp_cpu_ck_en:1;
57     };
58     uint32_t val;
59 } lpperi_clk_en_reg_t;
60 
61 /** Type of reset_en register
62  *  need_des
63  */
64 typedef union {
65     struct {
66         uint32_t reserved_0:23;
67         /** bus_reset_en : WT; bitpos: [23]; default: 0;
68          *  need_des
69          */
70         uint32_t bus_reset_en:1;
71         /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0;
72          *  need_des
73          */
74         uint32_t lp_ble_timer_reset_en:1;
75         /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
76          *  need_des
77          */
78         uint32_t otp_dbg_reset_en:1;
79         /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0;
80          *  need_des
81          */
82         uint32_t lp_uart_reset_en:1;
83         /** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
84          *  need_des
85          */
86         uint32_t lp_io_reset_en:1;
87         /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0;
88          *  need_des
89          */
90         uint32_t lp_ext_i2c_reset_en:1;
91         /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0;
92          *  need_des
93          */
94         uint32_t lp_ana_i2c_reset_en:1;
95         /** efuse_reset_en : R/W; bitpos: [30]; default: 0;
96          *  need_des
97          */
98         uint32_t efuse_reset_en:1;
99         /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0;
100          *  need_des
101          */
102         uint32_t lp_cpu_reset_en:1;
103     };
104     uint32_t val;
105 } lpperi_reset_en_reg_t;
106 
107 /** Type of rng_cfg register
108  *  need_des
109  */
110 typedef union {
111     struct {
112         /** rng_cfg_enable : R/W; bitpos: [1:0]; default: 0;
113          *  need_des
114          */
115         uint32_t rng_cfg_enable:2;
116         uint32_t reserved_2:30;
117     };
118     uint32_t val;
119 } lpperi_rng_cfg_reg_t;
120 
121 /** Type of rng_data register
122  *  need_des
123  */
124 typedef union {
125     struct {
126         /** rnd_data : RO; bitpos: [31:0]; default: 0;
127          *  need_des
128          */
129         uint32_t rnd_data:32;
130     };
131     uint32_t val;
132 } lpperi_rng_data_reg_t;
133 
134 /** Type of cpu register
135  *  need_des
136  */
137 typedef union {
138     struct {
139         uint32_t reserved_0:31;
140         /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1;
141          *  need_des
142          */
143         uint32_t lpcore_dbgm_unavaliable:1;
144     };
145     uint32_t val;
146 } lpperi_cpu_reg_t;
147 
148 /** Type of bus_timeout register
149  *  need_des
150  */
151 typedef union {
152     struct {
153         uint32_t reserved_0:14;
154         /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535;
155          *  need_des
156          */
157         uint32_t lp_peri_timeout_thres:16;
158         /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0;
159          *  need_des
160          */
161         uint32_t lp_peri_timeout_int_clear:1;
162         /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1;
163          *  need_des
164          */
165         uint32_t lp_peri_timeout_protect_en:1;
166     };
167     uint32_t val;
168 } lpperi_bus_timeout_reg_t;
169 
170 /** Type of bus_timeout_addr register
171  *  need_des
172  */
173 typedef union {
174     struct {
175         /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
176          *  need_des
177          */
178         uint32_t lp_peri_timeout_addr:32;
179     };
180     uint32_t val;
181 } lpperi_bus_timeout_addr_reg_t;
182 
183 /** Type of bus_timeout_uid register
184  *  need_des
185  */
186 typedef union {
187     struct {
188         /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
189          *  need_des
190          */
191         uint32_t lp_peri_timeout_uid:7;
192         uint32_t reserved_7:25;
193     };
194     uint32_t val;
195 } lpperi_bus_timeout_uid_reg_t;
196 
197 /** Type of mem_ctrl register
198  *  need_des
199  */
200 typedef union {
201     struct {
202         /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
203          *  need_des
204          */
205         uint32_t uart_wakeup_flag_clr:1;
206         /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
207          *  need_des
208          */
209         uint32_t uart_wakeup_flag:1;
210         uint32_t reserved_2:27;
211         /** uart_wakeup_en : R/W; bitpos: [29]; default: 0;
212          *  need_des
213          */
214         uint32_t uart_wakeup_en:1;
215         /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
216          *  need_des
217          */
218         uint32_t uart_mem_force_pd:1;
219         /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
220          *  need_des
221          */
222         uint32_t uart_mem_force_pu:1;
223     };
224     uint32_t val;
225 } lpperi_mem_ctrl_reg_t;
226 
227 /** Type of interrupt_source register
228  *  need_des
229  */
230 typedef union {
231     struct {
232         /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0;
233          *  BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
234          *  lp_io_int
235          */
236         uint32_t lp_interrupt_source:6;
237         uint32_t reserved_6:26;
238     };
239     uint32_t val;
240 } lpperi_interrupt_source_reg_t;
241 
242 /** Type of debug_sel0 register
243  *  need des
244  */
245 typedef union {
246     struct {
247         /** debug_sel0 : R/W; bitpos: [6:0]; default: 0;
248          *  need des
249          */
250         uint32_t debug_sel0:7;
251         /** debug_sel1 : R/W; bitpos: [13:7]; default: 0;
252          *  need des
253          */
254         uint32_t debug_sel1:7;
255         /** debug_sel2 : R/W; bitpos: [20:14]; default: 0;
256          *  need des
257          */
258         uint32_t debug_sel2:7;
259         /** debug_sel3 : R/W; bitpos: [27:21]; default: 0;
260          *  need des
261          */
262         uint32_t debug_sel3:7;
263         uint32_t reserved_28:4;
264     };
265     uint32_t val;
266 } lpperi_debug_sel0_reg_t;
267 
268 /** Type of debug_sel1 register
269  *  need des
270  */
271 typedef union {
272     struct {
273         /** debug_sel4 : R/W; bitpos: [6:0]; default: 0;
274          *  need des
275          */
276         uint32_t debug_sel4:7;
277         uint32_t reserved_7:25;
278     };
279     uint32_t val;
280 } lpperi_debug_sel1_reg_t;
281 
282 
283 /** Group: Version register */
284 /** Type of date register
285  *  need_des
286  */
287 typedef union {
288     struct {
289         /** lpperi_date : R/W; bitpos: [30:0]; default: 36732976 (0x2308030);
290          *  need_des
291          */
292         uint32_t lpperi_date:31;
293         /** clk_en : R/W; bitpos: [31]; default: 0;
294          *  need_des
295          */
296         uint32_t clk_en:1;
297     };
298     uint32_t val;
299 } lpperi_date_reg_t;
300 
301 
302 typedef struct {
303     volatile lpperi_clk_en_reg_t clk_en;
304     volatile lpperi_reset_en_reg_t reset_en;
305     volatile lpperi_rng_cfg_reg_t rng_cfg;
306     volatile lpperi_rng_data_reg_t rng_data;
307     volatile lpperi_cpu_reg_t cpu;
308     volatile lpperi_bus_timeout_reg_t bus_timeout;
309     volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr;
310     volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid;
311     volatile lpperi_mem_ctrl_reg_t mem_ctrl;
312     volatile lpperi_interrupt_source_reg_t interrupt_source;
313     volatile lpperi_debug_sel0_reg_t debug_sel0;
314     volatile lpperi_debug_sel1_reg_t debug_sel1;
315     uint32_t reserved_030[243];
316     volatile lpperi_date_reg_t date;
317 } lpperi_rev1_2_dev_t;
318 
319 #ifndef __cplusplus
320 _Static_assert(sizeof(lpperi_rev1_2_dev_t) == 0x400, "Invalid size of lpperi_rev1_2_dev_t structure");
321 #endif
322 
323 #ifdef __cplusplus
324 }
325 #endif
326