1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** LP_AON_STORE0_REG register 15 * need_des 16 */ 17 #define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) 18 /** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; 19 * need_des 20 */ 21 #define LP_AON_LP_AON_STORE0 0xFFFFFFFFU 22 #define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) 23 #define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU 24 #define LP_AON_LP_AON_STORE0_S 0 25 26 /** LP_AON_STORE1_REG register 27 * need_des 28 */ 29 #define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) 30 /** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; 31 * need_des 32 */ 33 #define LP_AON_LP_AON_STORE1 0xFFFFFFFFU 34 #define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) 35 #define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU 36 #define LP_AON_LP_AON_STORE1_S 0 37 38 /** LP_AON_STORE2_REG register 39 * need_des 40 */ 41 #define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) 42 /** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; 43 * need_des 44 */ 45 #define LP_AON_LP_AON_STORE2 0xFFFFFFFFU 46 #define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) 47 #define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU 48 #define LP_AON_LP_AON_STORE2_S 0 49 50 /** LP_AON_STORE3_REG register 51 * need_des 52 */ 53 #define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) 54 /** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; 55 * need_des 56 */ 57 #define LP_AON_LP_AON_STORE3 0xFFFFFFFFU 58 #define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) 59 #define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU 60 #define LP_AON_LP_AON_STORE3_S 0 61 62 /** LP_AON_STORE4_REG register 63 * need_des 64 */ 65 #define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) 66 /** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; 67 * need_des 68 */ 69 #define LP_AON_LP_AON_STORE4 0xFFFFFFFFU 70 #define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) 71 #define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU 72 #define LP_AON_LP_AON_STORE4_S 0 73 74 /** LP_AON_STORE5_REG register 75 * need_des 76 */ 77 #define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) 78 /** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; 79 * need_des 80 */ 81 #define LP_AON_LP_AON_STORE5 0xFFFFFFFFU 82 #define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) 83 #define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU 84 #define LP_AON_LP_AON_STORE5_S 0 85 86 /** LP_AON_STORE6_REG register 87 * need_des 88 */ 89 #define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) 90 /** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; 91 * need_des 92 */ 93 #define LP_AON_LP_AON_STORE6 0xFFFFFFFFU 94 #define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) 95 #define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU 96 #define LP_AON_LP_AON_STORE6_S 0 97 98 /** LP_AON_STORE7_REG register 99 * need_des 100 */ 101 #define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) 102 /** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; 103 * need_des 104 */ 105 #define LP_AON_LP_AON_STORE7 0xFFFFFFFFU 106 #define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) 107 #define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU 108 #define LP_AON_LP_AON_STORE7_S 0 109 110 /** LP_AON_STORE8_REG register 111 * need_des 112 */ 113 #define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) 114 /** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; 115 * need_des 116 */ 117 #define LP_AON_LP_AON_STORE8 0xFFFFFFFFU 118 #define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) 119 #define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU 120 #define LP_AON_LP_AON_STORE8_S 0 121 122 /** LP_AON_STORE9_REG register 123 * need_des 124 */ 125 #define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) 126 /** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; 127 * need_des 128 */ 129 #define LP_AON_LP_AON_STORE9 0xFFFFFFFFU 130 #define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) 131 #define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU 132 #define LP_AON_LP_AON_STORE9_S 0 133 134 /** LP_AON_GPIO_MUX_REG register 135 * need_des 136 */ 137 #define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) 138 /** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; 139 * need_des 140 */ 141 #define LP_AON_GPIO_MUX_SEL 0x000000FFU 142 #define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) 143 #define LP_AON_GPIO_MUX_SEL_V 0x000000FFU 144 #define LP_AON_GPIO_MUX_SEL_S 0 145 146 /** LP_AON_GPIO_HOLD0_REG register 147 * need_des 148 */ 149 #define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) 150 /** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; 151 * need_des 152 */ 153 #define LP_AON_GPIO_HOLD0 0xFFFFFFFFU 154 #define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) 155 #define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU 156 #define LP_AON_GPIO_HOLD0_S 0 157 158 /** LP_AON_GPIO_HOLD1_REG register 159 * need_des 160 */ 161 #define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) 162 /** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; 163 * need_des 164 */ 165 #define LP_AON_GPIO_HOLD1 0xFFFFFFFFU 166 #define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) 167 #define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU 168 #define LP_AON_GPIO_HOLD1_S 0 169 170 /** LP_AON_SYS_CFG_REG register 171 * need_des 172 */ 173 #define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) 174 /** LP_AON_ANA_FIB_SWD_ENABLE : RO; bitpos: [0]; default: 1; 175 * need_des 176 */ 177 #define LP_AON_ANA_FIB_SWD_ENABLE (BIT(0)) 178 #define LP_AON_ANA_FIB_SWD_ENABLE_M (LP_AON_ANA_FIB_SWD_ENABLE_V << LP_AON_ANA_FIB_SWD_ENABLE_S) 179 #define LP_AON_ANA_FIB_SWD_ENABLE_V 0x00000001U 180 #define LP_AON_ANA_FIB_SWD_ENABLE_S 0 181 /** LP_AON_ANA_FIB_CK_GLITCH_ENABLE : RO; bitpos: [1]; default: 1; 182 * need_des 183 */ 184 #define LP_AON_ANA_FIB_CK_GLITCH_ENABLE (BIT(1)) 185 #define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_M (LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V << LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S) 186 #define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V 0x00000001U 187 #define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S 1 188 /** LP_AON_ANA_FIB_BOD_ENABLE : RO; bitpos: [2]; default: 1; 189 * need_des 190 */ 191 #define LP_AON_ANA_FIB_BOD_ENABLE (BIT(2)) 192 #define LP_AON_ANA_FIB_BOD_ENABLE_M (LP_AON_ANA_FIB_BOD_ENABLE_V << LP_AON_ANA_FIB_BOD_ENABLE_S) 193 #define LP_AON_ANA_FIB_BOD_ENABLE_V 0x00000001U 194 #define LP_AON_ANA_FIB_BOD_ENABLE_S 2 195 /** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; 196 * need_des 197 */ 198 #define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) 199 #define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) 200 #define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U 201 #define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 202 /** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; 203 * need_des 204 */ 205 #define LP_AON_HPSYS_SW_RESET (BIT(31)) 206 #define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) 207 #define LP_AON_HPSYS_SW_RESET_V 0x00000001U 208 #define LP_AON_HPSYS_SW_RESET_S 31 209 210 /** LP_AON_CPUCORE0_CFG_REG register 211 * need_des 212 */ 213 #define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) 214 /** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; 215 * need_des 216 */ 217 #define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU 218 #define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) 219 #define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU 220 #define LP_AON_CPU_CORE0_SW_STALL_S 0 221 /** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; 222 * need_des 223 */ 224 #define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) 225 #define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) 226 #define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U 227 #define LP_AON_CPU_CORE0_SW_RESET_S 28 228 /** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; 229 * need_des 230 */ 231 #define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) 232 #define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) 233 #define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U 234 #define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 235 /** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; 236 * need_des 237 */ 238 #define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) 239 #define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) 240 #define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U 241 #define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 242 /** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; 243 * need_des 244 */ 245 #define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) 246 #define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) 247 #define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U 248 #define LP_AON_CPU_CORE0_DRESET_MASK_S 31 249 250 /** LP_AON_IO_MUX_REG register 251 * need_des 252 */ 253 #define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) 254 /** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0; 255 * need_des 256 */ 257 #define LP_AON_IO_MUX_PULL_LDO 0x00000007U 258 #define LP_AON_IO_MUX_PULL_LDO_M (LP_AON_IO_MUX_PULL_LDO_V << LP_AON_IO_MUX_PULL_LDO_S) 259 #define LP_AON_IO_MUX_PULL_LDO_V 0x00000007U 260 #define LP_AON_IO_MUX_PULL_LDO_S 28 261 /** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; 262 * need_des 263 */ 264 #define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) 265 #define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) 266 #define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U 267 #define LP_AON_IO_MUX_RESET_DISABLE_S 31 268 269 /** LP_AON_EXT_WAKEUP_CNTL_REG register 270 * need_des 271 */ 272 #define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) 273 /** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; 274 * need_des 275 */ 276 #define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU 277 #define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) 278 #define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU 279 #define LP_AON_EXT_WAKEUP_STATUS_S 0 280 /** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; 281 * need_des 282 */ 283 #define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) 284 #define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) 285 #define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U 286 #define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 287 /** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; 288 * need_des 289 */ 290 #define LP_AON_EXT_WAKEUP_SEL 0x000000FFU 291 #define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) 292 #define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU 293 #define LP_AON_EXT_WAKEUP_SEL_S 15 294 /** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; 295 * need_des 296 */ 297 #define LP_AON_EXT_WAKEUP_LV 0x000000FFU 298 #define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) 299 #define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU 300 #define LP_AON_EXT_WAKEUP_LV_S 23 301 /** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; 302 * need_des 303 */ 304 #define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) 305 #define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) 306 #define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U 307 #define LP_AON_EXT_WAKEUP_FILTER_S 31 308 309 /** LP_AON_USB_REG register 310 * need_des 311 */ 312 #define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) 313 /** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; 314 * need_des 315 */ 316 #define LP_AON_USB_RESET_DISABLE (BIT(31)) 317 #define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) 318 #define LP_AON_USB_RESET_DISABLE_V 0x00000001U 319 #define LP_AON_USB_RESET_DISABLE_S 31 320 321 /** LP_AON_LPBUS_REG register 322 * need_des 323 */ 324 #define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) 325 /** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; 326 * This field controls fast memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V 327 * operating Voltage. 328 */ 329 #define LP_AON_FAST_MEM_WPULSE 0x00000007U 330 #define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) 331 #define LP_AON_FAST_MEM_WPULSE_V 0x00000007U 332 #define LP_AON_FAST_MEM_WPULSE_S 16 333 /** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 5; 334 * This field controls fast memory WA parameter. 0b100 for 1.1V operating Voltage, 335 * 0b101 for 1.0V, 0b110 for 0.9V. 336 */ 337 #define LP_AON_FAST_MEM_WA 0x00000007U 338 #define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) 339 #define LP_AON_FAST_MEM_WA_V 0x00000007U 340 #define LP_AON_FAST_MEM_WA_S 19 341 /** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; 342 * This field controls fast memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, 343 * 0b01 for 0.9V. 344 */ 345 #define LP_AON_FAST_MEM_RA 0x00000003U 346 #define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) 347 #define LP_AON_FAST_MEM_RA_V 0x00000003U 348 #define LP_AON_FAST_MEM_RA_S 22 349 /** LP_AON_FAST_MEM_RM : R/W; bitpos: [27:24]; default: 2; 350 * This field controls fast memory RM parameter. 0b0011 for 1.1V operating Voltage, 351 * 0b0010 for 1.0V, 0b0000 for 0.9V. 352 */ 353 #define LP_AON_FAST_MEM_RM 0x0000000FU 354 #define LP_AON_FAST_MEM_RM_M (LP_AON_FAST_MEM_RM_V << LP_AON_FAST_MEM_RM_S) 355 #define LP_AON_FAST_MEM_RM_V 0x0000000FU 356 #define LP_AON_FAST_MEM_RM_S 24 357 /** LP_AON_FAST_MEM_MUX_FSM_IDLE : HRO; bitpos: [28]; default: 0; 358 * reserved 359 */ 360 #define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) 361 #define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) 362 #define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U 363 #define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 364 /** LP_AON_FAST_MEM_MUX_SEL_STATUS : HRO; bitpos: [29]; default: 0; 365 * reserved 366 */ 367 #define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) 368 #define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) 369 #define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U 370 #define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 371 /** LP_AON_FAST_MEM_MUX_SEL_UPDATE : HRO; bitpos: [30]; default: 0; 372 * reserved 373 */ 374 #define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) 375 #define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) 376 #define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U 377 #define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 378 /** LP_AON_FAST_MEM_MUX_SEL : HRO; bitpos: [31]; default: 0; 379 * reserved 380 */ 381 #define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) 382 #define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) 383 #define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U 384 #define LP_AON_FAST_MEM_MUX_SEL_S 31 385 386 /** LP_AON_SDIO_ACTIVE_REG register 387 * need_des 388 */ 389 #define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) 390 /** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; 391 * need_des 392 */ 393 #define LP_AON_SDIO_ACT_DNUM 0x000003FFU 394 #define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) 395 #define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU 396 #define LP_AON_SDIO_ACT_DNUM_S 22 397 398 /** LP_AON_LPCORE_REG register 399 * need_des 400 */ 401 #define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) 402 /** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; 403 * need_des 404 */ 405 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) 406 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) 407 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U 408 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 409 /** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; 410 * need_des 411 */ 412 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) 413 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) 414 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U 415 #define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 416 /** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; 417 * need_des 418 */ 419 #define LP_AON_LPCORE_DISABLE (BIT(31)) 420 #define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) 421 #define LP_AON_LPCORE_DISABLE_V 0x00000001U 422 #define LP_AON_LPCORE_DISABLE_S 31 423 424 /** LP_AON_SAR_CCT_REG register 425 * need_des 426 */ 427 #define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) 428 /** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; 429 * need_des 430 */ 431 #define LP_AON_SAR2_PWDET_CCT 0x00000007U 432 #define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) 433 #define LP_AON_SAR2_PWDET_CCT_V 0x00000007U 434 #define LP_AON_SAR2_PWDET_CCT_S 29 435 436 /** LP_AON_JTAG_SEL_REG register 437 * need_des 438 */ 439 #define LP_AON_JTAG_SEL_REG (DR_REG_LP_AON_BASE + 0x58) 440 /** LP_AON_JTAG_SEL_SOFT : R/W; bitpos: [31]; default: 1; 441 * If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or 442 * usb_jtag is disabled by efuse, this field determines which one jtag between 443 * usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. 444 */ 445 #define LP_AON_JTAG_SEL_SOFT (BIT(31)) 446 #define LP_AON_JTAG_SEL_SOFT_M (LP_AON_JTAG_SEL_SOFT_V << LP_AON_JTAG_SEL_SOFT_S) 447 #define LP_AON_JTAG_SEL_SOFT_V 0x00000001U 448 #define LP_AON_JTAG_SEL_SOFT_S 31 449 450 /** LP_AON_DATE_REG register 451 * need_des 452 */ 453 #define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) 454 /** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35717264; 455 * need_des 456 */ 457 #define LP_AON_DATE 0x7FFFFFFFU 458 #define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) 459 #define LP_AON_DATE_V 0x7FFFFFFFU 460 #define LP_AON_DATE_S 0 461 /** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; 462 * need_des 463 */ 464 #define LP_AON_CLK_EN (BIT(31)) 465 #define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) 466 #define LP_AON_CLK_EN_V 0x00000001U 467 #define LP_AON_CLK_EN_S 31 468 469 #ifdef __cplusplus 470 } 471 #endif 472
