1 /**
2  * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdint.h>
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 /** Group: monitor configuration registers */
14 /** Type of core_0_intr_ena register
15  *  core0 monitor enable configuration register
16  */
17 typedef union {
18     struct {
19         /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
20          *  Core0 dram0 area0 read monitor enable
21          */
22         uint32_t core_0_area_dram0_0_rd_ena:1;
23         /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
24          *  Core0 dram0 area0 write monitor enable
25          */
26         uint32_t core_0_area_dram0_0_wr_ena:1;
27         /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
28          *  Core0 dram0 area1 read monitor enable
29          */
30         uint32_t core_0_area_dram0_1_rd_ena:1;
31         /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
32          *  Core0 dram0 area1 write monitor enable
33          */
34         uint32_t core_0_area_dram0_1_wr_ena:1;
35         /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
36          *  Core0 PIF area0 read monitor enable
37          */
38         uint32_t core_0_area_pif_0_rd_ena:1;
39         /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
40          *  Core0 PIF area0 write monitor enable
41          */
42         uint32_t core_0_area_pif_0_wr_ena:1;
43         /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
44          *  Core0 PIF area1 read monitor enable
45          */
46         uint32_t core_0_area_pif_1_rd_ena:1;
47         /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
48          *  Core0 PIF area1 write monitor enable
49          */
50         uint32_t core_0_area_pif_1_wr_ena:1;
51         /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
52          *  Core0 stackpoint underflow monitor enable
53          */
54         uint32_t core_0_sp_spill_min_ena:1;
55         /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
56          *  Core0 stackpoint overflow monitor enable
57          */
58         uint32_t core_0_sp_spill_max_ena:1;
59         /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
60          *  IBUS busy monitor enable
61          */
62         uint32_t core_0_iram0_exception_monitor_ena:1;
63         /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
64          *  DBUS busy monitor enbale
65          */
66         uint32_t core_0_dram0_exception_monitor_ena:1;
67         uint32_t reserved_12:20;
68     };
69     uint32_t val;
70 } assist_debug_core_0_intr_ena_reg_t;
71 
72 /** Type of core_0_area_dram0_0_min register
73  *  core0 dram0 region0 addr configuration register
74  */
75 typedef union {
76     struct {
77         /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
78          *  Core0 dram0 region0 start addr
79          */
80         uint32_t core_0_area_dram0_0_min:32;
81     };
82     uint32_t val;
83 } assist_debug_core_0_area_dram0_0_min_reg_t;
84 
85 /** Type of core_0_area_dram0_0_max register
86  *  core0 dram0 region0 addr configuration register
87  */
88 typedef union {
89     struct {
90         /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
91          *  Core0 dram0 region0 end addr
92          */
93         uint32_t core_0_area_dram0_0_max:32;
94     };
95     uint32_t val;
96 } assist_debug_core_0_area_dram0_0_max_reg_t;
97 
98 /** Type of core_0_area_dram0_1_min register
99  *  core0 dram0 region1 addr configuration register
100  */
101 typedef union {
102     struct {
103         /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
104          *  Core0 dram0 region1 start addr
105          */
106         uint32_t core_0_area_dram0_1_min:32;
107     };
108     uint32_t val;
109 } assist_debug_core_0_area_dram0_1_min_reg_t;
110 
111 /** Type of core_0_area_dram0_1_max register
112  *  core0 dram0 region1 addr configuration register
113  */
114 typedef union {
115     struct {
116         /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
117          *  Core0 dram0 region1 end addr
118          */
119         uint32_t core_0_area_dram0_1_max:32;
120     };
121     uint32_t val;
122 } assist_debug_core_0_area_dram0_1_max_reg_t;
123 
124 /** Type of core_0_area_pif_0_min register
125  *  core0 PIF region0 addr configuration register
126  */
127 typedef union {
128     struct {
129         /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
130          *  Core0 PIF region0 start addr
131          */
132         uint32_t core_0_area_pif_0_min:32;
133     };
134     uint32_t val;
135 } assist_debug_core_0_area_pif_0_min_reg_t;
136 
137 /** Type of core_0_area_pif_0_max register
138  *  core0 PIF region0 addr configuration register
139  */
140 typedef union {
141     struct {
142         /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
143          *  Core0 PIF region0 end addr
144          */
145         uint32_t core_0_area_pif_0_max:32;
146     };
147     uint32_t val;
148 } assist_debug_core_0_area_pif_0_max_reg_t;
149 
150 /** Type of core_0_area_pif_1_min register
151  *  core0 PIF region1 addr configuration register
152  */
153 typedef union {
154     struct {
155         /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
156          *  Core0 PIF region1 start addr
157          */
158         uint32_t core_0_area_pif_1_min:32;
159     };
160     uint32_t val;
161 } assist_debug_core_0_area_pif_1_min_reg_t;
162 
163 /** Type of core_0_area_pif_1_max register
164  *  core0 PIF region1 addr configuration register
165  */
166 typedef union {
167     struct {
168         /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
169          *  Core0 PIF region1 end addr
170          */
171         uint32_t core_0_area_pif_1_max:32;
172     };
173     uint32_t val;
174 } assist_debug_core_0_area_pif_1_max_reg_t;
175 
176 /** Type of core_0_area_pc register
177  *  core0 area pc status register
178  */
179 typedef union {
180     struct {
181         /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
182          *  the stackpointer when first touch region monitor interrupt
183          */
184         uint32_t core_0_area_pc:32;
185     };
186     uint32_t val;
187 } assist_debug_core_0_area_pc_reg_t;
188 
189 /** Type of core_0_area_sp register
190  *  core0 area sp status register
191  */
192 typedef union {
193     struct {
194         /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
195          *  the PC when first touch region monitor interrupt
196          */
197         uint32_t core_0_area_sp:32;
198     };
199     uint32_t val;
200 } assist_debug_core_0_area_sp_reg_t;
201 
202 /** Type of core_0_sp_min register
203  *  stack min value
204  */
205 typedef union {
206     struct {
207         /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
208          *  core0 sp region configuration regsiter
209          */
210         uint32_t core_0_sp_min:32;
211     };
212     uint32_t val;
213 } assist_debug_core_0_sp_min_reg_t;
214 
215 /** Type of core_0_sp_max register
216  *  stack max value
217  */
218 typedef union {
219     struct {
220         /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
221          *  core0 sp pc status register
222          */
223         uint32_t core_0_sp_max:32;
224     };
225     uint32_t val;
226 } assist_debug_core_0_sp_max_reg_t;
227 
228 /** Type of core_0_sp_pc register
229  *  stack monitor pc status register
230  */
231 typedef union {
232     struct {
233         /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
234          *  This regsiter stores the PC when trigger stack monitor.
235          */
236         uint32_t core_0_sp_pc:32;
237     };
238     uint32_t val;
239 } assist_debug_core_0_sp_pc_reg_t;
240 
241 
242 /** Group: interrupt configuration register */
243 /** Type of core_0_intr_raw register
244  *  core0 monitor interrupt status register
245  */
246 typedef union {
247     struct {
248         /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
249          *  Core0 dram0 area0 read monitor interrupt status
250          */
251         uint32_t core_0_area_dram0_0_rd_raw:1;
252         /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
253          *  Core0 dram0 area0 write monitor interrupt status
254          */
255         uint32_t core_0_area_dram0_0_wr_raw:1;
256         /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
257          *  Core0 dram0 area1 read monitor interrupt status
258          */
259         uint32_t core_0_area_dram0_1_rd_raw:1;
260         /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
261          *  Core0 dram0 area1 write monitor interrupt status
262          */
263         uint32_t core_0_area_dram0_1_wr_raw:1;
264         /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
265          *  Core0 PIF area0 read monitor interrupt status
266          */
267         uint32_t core_0_area_pif_0_rd_raw:1;
268         /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
269          *  Core0 PIF area0 write monitor interrupt status
270          */
271         uint32_t core_0_area_pif_0_wr_raw:1;
272         /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
273          *  Core0 PIF area1 read monitor interrupt status
274          */
275         uint32_t core_0_area_pif_1_rd_raw:1;
276         /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
277          *  Core0 PIF area1 write monitor interrupt status
278          */
279         uint32_t core_0_area_pif_1_wr_raw:1;
280         /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
281          *  Core0 stackpoint underflow monitor interrupt status
282          */
283         uint32_t core_0_sp_spill_min_raw:1;
284         /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
285          *  Core0 stackpoint overflow monitor interrupt status
286          */
287         uint32_t core_0_sp_spill_max_raw:1;
288         /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
289          *  IBUS busy monitor interrupt status
290          */
291         uint32_t core_0_iram0_exception_monitor_raw:1;
292         /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
293          *  DBUS busy monitor initerrupt status
294          */
295         uint32_t core_0_dram0_exception_monitor_raw:1;
296         uint32_t reserved_12:20;
297     };
298     uint32_t val;
299 } assist_debug_core_0_intr_raw_reg_t;
300 
301 /** Type of core_0_intr_rls register
302  *  core0 monitor interrupt enable register
303  */
304 typedef union {
305     struct {
306         /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
307          *  Core0 dram0 area0 read monitor interrupt enable
308          */
309         uint32_t core_0_area_dram0_0_rd_rls:1;
310         /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
311          *  Core0 dram0 area0 write monitor interrupt enable
312          */
313         uint32_t core_0_area_dram0_0_wr_rls:1;
314         /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
315          *  Core0 dram0 area1 read monitor interrupt enable
316          */
317         uint32_t core_0_area_dram0_1_rd_rls:1;
318         /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
319          *  Core0 dram0 area1 write monitor interrupt enable
320          */
321         uint32_t core_0_area_dram0_1_wr_rls:1;
322         /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
323          *  Core0 PIF area0 read monitor interrupt enable
324          */
325         uint32_t core_0_area_pif_0_rd_rls:1;
326         /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
327          *  Core0 PIF area0 write monitor interrupt enable
328          */
329         uint32_t core_0_area_pif_0_wr_rls:1;
330         /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
331          *  Core0 PIF area1 read monitor interrupt enable
332          */
333         uint32_t core_0_area_pif_1_rd_rls:1;
334         /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
335          *  Core0 PIF area1 write monitor interrupt enable
336          */
337         uint32_t core_0_area_pif_1_wr_rls:1;
338         /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
339          *  Core0 stackpoint underflow monitor interrupt enable
340          */
341         uint32_t core_0_sp_spill_min_rls:1;
342         /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
343          *  Core0 stackpoint overflow monitor interrupt enable
344          */
345         uint32_t core_0_sp_spill_max_rls:1;
346         /** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0;
347          *  IBUS busy monitor interrupt enable
348          */
349         uint32_t core_0_iram0_exception_monitor_rls:1;
350         /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
351          *  DBUS busy monitor interrupt enbale
352          */
353         uint32_t core_0_dram0_exception_monitor_rls:1;
354         uint32_t reserved_12:20;
355     };
356     uint32_t val;
357 } assist_debug_core_0_intr_rls_reg_t;
358 
359 /** Type of core_0_intr_clr register
360  *  core0 monitor interrupt clr register
361  */
362 typedef union {
363     struct {
364         /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
365          *  Core0 dram0 area0 read monitor interrupt clr
366          */
367         uint32_t core_0_area_dram0_0_rd_clr:1;
368         /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
369          *  Core0 dram0 area0 write monitor interrupt clr
370          */
371         uint32_t core_0_area_dram0_0_wr_clr:1;
372         /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
373          *  Core0 dram0 area1 read monitor interrupt clr
374          */
375         uint32_t core_0_area_dram0_1_rd_clr:1;
376         /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
377          *  Core0 dram0 area1 write monitor interrupt clr
378          */
379         uint32_t core_0_area_dram0_1_wr_clr:1;
380         /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
381          *  Core0 PIF area0 read monitor interrupt clr
382          */
383         uint32_t core_0_area_pif_0_rd_clr:1;
384         /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
385          *  Core0 PIF area0 write monitor interrupt clr
386          */
387         uint32_t core_0_area_pif_0_wr_clr:1;
388         /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
389          *  Core0 PIF area1 read monitor interrupt clr
390          */
391         uint32_t core_0_area_pif_1_rd_clr:1;
392         /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
393          *  Core0 PIF area1 write monitor interrupt clr
394          */
395         uint32_t core_0_area_pif_1_wr_clr:1;
396         /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
397          *  Core0 stackpoint underflow monitor interrupt clr
398          */
399         uint32_t core_0_sp_spill_min_clr:1;
400         /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
401          *  Core0 stackpoint overflow monitor interrupt clr
402          */
403         uint32_t core_0_sp_spill_max_clr:1;
404         /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
405          *  IBUS busy monitor interrupt clr
406          */
407         uint32_t core_0_iram0_exception_monitor_clr:1;
408         /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
409          *  DBUS busy monitor interrupt clr
410          */
411         uint32_t core_0_dram0_exception_monitor_clr:1;
412         uint32_t reserved_12:20;
413     };
414     uint32_t val;
415 } assist_debug_core_0_intr_clr_reg_t;
416 
417 
418 /** Group: pc reording configuration register */
419 /** Type of core_0_rcd_en register
420  *  record enable configuration register
421  */
422 typedef union {
423     struct {
424         /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
425          *  Set 1 to enable record PC
426          */
427         uint32_t core_0_rcd_recorden:1;
428         /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
429          *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
430          */
431         uint32_t core_0_rcd_pdebugen:1;
432         uint32_t reserved_2:30;
433     };
434     uint32_t val;
435 } assist_debug_core_0_rcd_en_reg_t;
436 
437 
438 /** Group: pc reording status register */
439 /** Type of core_0_rcd_pdebugpc register
440  *  record status regsiter
441  */
442 typedef union {
443     struct {
444         /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
445          *  recorded PC
446          */
447         uint32_t core_0_rcd_pdebugpc:32;
448     };
449     uint32_t val;
450 } assist_debug_core_0_rcd_pdebugpc_reg_t;
451 
452 /** Type of core_0_rcd_pdebugsp register
453  *  record status regsiter
454  */
455 typedef union {
456     struct {
457         /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
458          *  recorded sp
459          */
460         uint32_t core_0_rcd_pdebugsp:32;
461     };
462     uint32_t val;
463 } assist_debug_core_0_rcd_pdebugsp_reg_t;
464 
465 
466 /** Group: exception monitor regsiter */
467 /** Type of core_0_iram0_exception_monitor_0 register
468  *  exception monitor status register0
469  */
470 typedef union {
471     struct {
472         /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
473          *  reg_core_0_iram0_recording_addr_0
474          */
475         uint32_t core_0_iram0_recording_addr_0:24;
476         /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
477          *  reg_core_0_iram0_recording_wr_0
478          */
479         uint32_t core_0_iram0_recording_wr_0:1;
480         /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
481          *  reg_core_0_iram0_recording_loadstore_0
482          */
483         uint32_t core_0_iram0_recording_loadstore_0:1;
484         uint32_t reserved_26:6;
485     };
486     uint32_t val;
487 } assist_debug_core_0_iram0_exception_monitor_0_reg_t;
488 
489 /** Type of core_0_iram0_exception_monitor_1 register
490  *  exception monitor status register1
491  */
492 typedef union {
493     struct {
494         /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
495          *  reg_core_0_iram0_recording_addr_1
496          */
497         uint32_t core_0_iram0_recording_addr_1:24;
498         /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
499          *  reg_core_0_iram0_recording_wr_1
500          */
501         uint32_t core_0_iram0_recording_wr_1:1;
502         /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
503          *  reg_core_0_iram0_recording_loadstore_1
504          */
505         uint32_t core_0_iram0_recording_loadstore_1:1;
506         uint32_t reserved_26:6;
507     };
508     uint32_t val;
509 } assist_debug_core_0_iram0_exception_monitor_1_reg_t;
510 
511 /** Type of core_0_dram0_exception_monitor_0 register
512  *  exception monitor status register2
513  */
514 typedef union {
515     struct {
516         /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
517          *  reg_core_0_dram0_recording_addr_0
518          */
519         uint32_t core_0_dram0_recording_addr_0:24;
520         /** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
521          *  reg_core_0_dram0_recording_wr_0
522          */
523         uint32_t core_0_dram0_recording_wr_0:1;
524         /** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0;
525          *  reg_core_0_dram0_recording_byteen_0
526          */
527         uint32_t core_0_dram0_recording_byteen_0:4;
528         uint32_t reserved_29:3;
529     };
530     uint32_t val;
531 } assist_debug_core_0_dram0_exception_monitor_0_reg_t;
532 
533 /** Type of core_0_dram0_exception_monitor_1 register
534  *  exception monitor status register3
535  */
536 typedef union {
537     struct {
538         /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
539          *  reg_core_0_dram0_recording_pc_0
540          */
541         uint32_t core_0_dram0_recording_pc_0:32;
542     };
543     uint32_t val;
544 } assist_debug_core_0_dram0_exception_monitor_1_reg_t;
545 
546 /** Type of core_0_dram0_exception_monitor_2 register
547  *  exception monitor status register4
548  */
549 typedef union {
550     struct {
551         /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
552          *  reg_core_0_dram0_recording_addr_1
553          */
554         uint32_t core_0_dram0_recording_addr_1:24;
555         /** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
556          *  reg_core_0_dram0_recording_wr_1
557          */
558         uint32_t core_0_dram0_recording_wr_1:1;
559         /** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0;
560          *  reg_core_0_dram0_recording_byteen_1
561          */
562         uint32_t core_0_dram0_recording_byteen_1:4;
563         uint32_t reserved_29:3;
564     };
565     uint32_t val;
566 } assist_debug_core_0_dram0_exception_monitor_2_reg_t;
567 
568 /** Type of core_0_dram0_exception_monitor_3 register
569  *  exception monitor status register5
570  */
571 typedef union {
572     struct {
573         /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
574          *  reg_core_0_dram0_recording_pc_1
575          */
576         uint32_t core_0_dram0_recording_pc_1:32;
577     };
578     uint32_t val;
579 } assist_debug_core_0_dram0_exception_monitor_3_reg_t;
580 
581 /** Type of core_x_iram0_dram0_exception_monitor_0 register
582  *  exception monitor status register6
583  */
584 typedef union {
585     struct {
586         /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
587          *  reg_core_x_iram0_dram0_limit_cycle_0
588          */
589         uint32_t core_x_iram0_dram0_limit_cycle_0:20;
590         uint32_t reserved_20:12;
591     };
592     uint32_t val;
593 } assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
594 
595 /** Type of core_x_iram0_dram0_exception_monitor_1 register
596  *  exception monitor status register7
597  */
598 typedef union {
599     struct {
600         /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
601          *  reg_core_x_iram0_dram0_limit_cycle_1
602          */
603         uint32_t core_x_iram0_dram0_limit_cycle_1:20;
604         uint32_t reserved_20:12;
605     };
606     uint32_t val;
607 } assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
608 
609 
610 /** Group: cpu status registers */
611 /** Type of core_0_lastpc_before_exception register
612  *  cpu status register
613  */
614 typedef union {
615     struct {
616         /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
617          *  cpu's lastpc before exception
618          */
619         uint32_t core_0_lastpc_before_exc:32;
620     };
621     uint32_t val;
622 } assist_debug_core_0_lastpc_before_exception_reg_t;
623 
624 /** Type of core_0_debug_mode register
625  *  cpu status register
626  */
627 typedef union {
628     struct {
629         /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
630          *  cpu debug mode status, 1 means cpu enter debug mode.
631          */
632         uint32_t core_0_debug_mode:1;
633         /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
634          *  cpu debug_module active status
635          */
636         uint32_t core_0_debug_module_active:1;
637         uint32_t reserved_2:30;
638     };
639     uint32_t val;
640 } assist_debug_core_0_debug_mode_reg_t;
641 
642 
643 /** Group: Configuration Registers */
644 /** Type of clock_gate register
645  *  clock register
646  */
647 typedef union {
648     struct {
649         /** clk_en : R/W; bitpos: [0]; default: 1;
650          *  Set 1 force on the clock gate
651          */
652         uint32_t clk_en:1;
653         uint32_t reserved_1:31;
654     };
655     uint32_t val;
656 } assist_debug_clock_gate_reg_t;
657 
658 /** Type of date register
659  *  version register
660  */
661 typedef union {
662     struct {
663         /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
664          *  version register
665          */
666         uint32_t assist_debug_date:28;
667         uint32_t reserved_28:4;
668     };
669     uint32_t val;
670 } assist_debug_date_reg_t;
671 
672 
673 typedef struct {
674     volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
675     volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
676     volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
677     volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
678     volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
679     volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
680     volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
681     volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
682     volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
683     volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
684     volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
685     volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
686     volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
687     volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
688     volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
689     volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
690     volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
691     volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
692     volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
693     volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
694     volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
695     volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
696     volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
697     volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
698     volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
699     volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
700     volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
701     volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
702     volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
703     volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
704     volatile assist_debug_clock_gate_reg_t clock_gate;
705     uint32_t reserved_07c[224];
706     volatile assist_debug_date_reg_t date;
707 } assist_debug_dev_t;
708 
709 extern assist_debug_dev_t ASSIST_DEBUG;
710 
711 #ifndef __cplusplus
712 _Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
713 #endif
714 
715 #ifdef __cplusplus
716 }
717 #endif
718