1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "modem/reg_base.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) 15 /* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */ 16 /* description: .*/ 17 #define MODEM_SYSCON_CLK_EN (BIT(0)) 18 #define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S) 19 #define MODEM_SYSCON_CLK_EN_V 0x00000001U 20 #define MODEM_SYSCON_CLK_EN_S 0 21 22 #define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) 23 /* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [21]; default: 0; */ 24 /* description: .*/ 25 #define MODEM_SYSCON_CLK_ETM_EN (BIT(21)) 26 #define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S) 27 #define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U 28 #define MODEM_SYSCON_CLK_ETM_EN_S 21 29 /* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [22]; default: 0; */ 30 /* description: .*/ 31 #define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(22)) 32 #define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S) 33 #define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U 34 #define MODEM_SYSCON_CLK_ZB_APB_EN_S 22 35 /* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [23]; default: 0; */ 36 /* description: .*/ 37 #define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(23)) 38 #define MODEM_SYSCON_CLK_ZB_MAC_EN_M (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S) 39 #define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x00000001U 40 #define MODEM_SYSCON_CLK_ZB_MAC_EN_S 23 41 /* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [24]; default: 0; */ 42 /* description: .*/ 43 #define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(24)) 44 #define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S) 45 #define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U 46 #define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 24 47 /* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [25]; default: 0; */ 48 /* description: .*/ 49 #define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(25)) 50 #define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S) 51 #define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U 52 #define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 25 53 /* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [26]; default: 0; */ 54 /* description: .*/ 55 #define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(26)) 56 #define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S) 57 #define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U 58 #define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 26 59 /* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [27]; default: 0; */ 60 /* description: .*/ 61 #define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(27)) 62 #define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S) 63 #define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U 64 #define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 27 65 /* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [28]; default: 0; */ 66 /* description: .*/ 67 #define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(28)) 68 #define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S) 69 #define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U 70 #define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 28 71 /* MODEM_SYSCON_CLK_BLE_TIMER_APB_EN : R/W; bitpos: [29]; default: 0; */ 72 /* description: .*/ 73 #define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN (BIT(29)) 74 #define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S) 75 #define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V 0x00000001U 76 #define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S 29 77 /* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */ 78 /* description: .*/ 79 #define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) 80 #define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S) 81 #define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U 82 #define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 83 /* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */ 84 /* description: .*/ 85 #define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) 86 #define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S) 87 #define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U 88 #define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 89 90 #define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) 91 /* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0; */ 92 /* description: .*/ 93 #define MODEM_SYSCON_CLK_ETM_FO (BIT(22)) 94 #define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S) 95 #define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U 96 #define MODEM_SYSCON_CLK_ETM_FO_S 22 97 /* MODEM_SYSCON_CLK_ZB_FO : R/W; bitpos: [24]; default: 0; */ 98 /* description: .*/ 99 #define MODEM_SYSCON_CLK_ZB_FO (BIT(24)) 100 #define MODEM_SYSCON_CLK_ZB_FO_M (MODEM_SYSCON_CLK_ZB_FO_V << MODEM_SYSCON_CLK_ZB_FO_S) 101 #define MODEM_SYSCON_CLK_ZB_FO_V 0x00000001U 102 #define MODEM_SYSCON_CLK_ZB_FO_S 24 103 /* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; */ 104 /* description: .*/ 105 #define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) 106 #define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S) 107 #define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U 108 #define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 109 /* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */ 110 /* description: .*/ 111 #define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) 112 #define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S) 113 #define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U 114 #define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 115 /* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; */ 116 /* description: .*/ 117 #define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) 118 #define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S) 119 #define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U 120 #define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 121 122 #define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0xc) 123 /* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */ 124 /* description: .*/ 125 #define MODEM_SYSCON_RST_FE (BIT(14)) 126 #define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S) 127 #define MODEM_SYSCON_RST_FE_V 0x00000001U 128 #define MODEM_SYSCON_RST_FE_S 14 129 /* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */ 130 /* description: .*/ 131 #define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) 132 #define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S) 133 #define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U 134 #define MODEM_SYSCON_RST_BTMAC_APB_S 15 135 /* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */ 136 /* description: .*/ 137 #define MODEM_SYSCON_RST_BTMAC (BIT(16)) 138 #define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S) 139 #define MODEM_SYSCON_RST_BTMAC_V 0x00000001U 140 #define MODEM_SYSCON_RST_BTMAC_S 16 141 /* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */ 142 /* description: .*/ 143 #define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) 144 #define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S) 145 #define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U 146 #define MODEM_SYSCON_RST_BTBB_APB_S 17 147 /* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */ 148 /* description: .*/ 149 #define MODEM_SYSCON_RST_BTBB (BIT(18)) 150 #define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S) 151 #define MODEM_SYSCON_RST_BTBB_V 0x00000001U 152 #define MODEM_SYSCON_RST_BTBB_S 18 153 /* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */ 154 /* description: .*/ 155 #define MODEM_SYSCON_RST_ETM (BIT(22)) 156 #define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S) 157 #define MODEM_SYSCON_RST_ETM_V 0x00000001U 158 #define MODEM_SYSCON_RST_ETM_S 22 159 /* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */ 160 /* description: .*/ 161 #define MODEM_SYSCON_RST_ZBMAC (BIT(24)) 162 #define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S) 163 #define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U 164 #define MODEM_SYSCON_RST_ZBMAC_S 24 165 /* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */ 166 /* description: .*/ 167 #define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) 168 #define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S) 169 #define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U 170 #define MODEM_SYSCON_RST_MODEM_ECB_S 25 171 /* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */ 172 /* description: .*/ 173 #define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) 174 #define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S) 175 #define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U 176 #define MODEM_SYSCON_RST_MODEM_CCM_S 26 177 /* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */ 178 /* description: .*/ 179 #define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) 180 #define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S) 181 #define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U 182 #define MODEM_SYSCON_RST_MODEM_BAH_S 27 183 /* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */ 184 /* description: .*/ 185 #define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) 186 #define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S) 187 #define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U 188 #define MODEM_SYSCON_RST_MODEM_SEC_S 29 189 /* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */ 190 /* description: .*/ 191 #define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) 192 #define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S) 193 #define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U 194 #define MODEM_SYSCON_RST_BLE_TIMER_S 30 195 /* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */ 196 /* description: .*/ 197 #define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) 198 #define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S) 199 #define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U 200 #define MODEM_SYSCON_RST_DATA_DUMP_S 31 201 202 #define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) 203 /* MODEM_SYSCON_CLK_FE_16M_EN : R/W; bitpos: [12]; default: 0; */ 204 /* description: .*/ 205 #define MODEM_SYSCON_CLK_FE_16M_EN (BIT(12)) 206 #define MODEM_SYSCON_CLK_FE_16M_EN_M (MODEM_SYSCON_CLK_FE_16M_EN_V << MODEM_SYSCON_CLK_FE_16M_EN_S) 207 #define MODEM_SYSCON_CLK_FE_16M_EN_V 0x00000001U 208 #define MODEM_SYSCON_CLK_FE_16M_EN_S 12 209 /* MODEM_SYSCON_CLK_FE_32M_EN : R/W; bitpos: [13]; default: 0; */ 210 /* description: .*/ 211 #define MODEM_SYSCON_CLK_FE_32M_EN (BIT(13)) 212 #define MODEM_SYSCON_CLK_FE_32M_EN_M (MODEM_SYSCON_CLK_FE_32M_EN_V << MODEM_SYSCON_CLK_FE_32M_EN_S) 213 #define MODEM_SYSCON_CLK_FE_32M_EN_V 0x00000001U 214 #define MODEM_SYSCON_CLK_FE_32M_EN_S 13 215 /* MODEM_SYSCON_CLK_FE_SDM_EN : R/W; bitpos: [14]; default: 0; */ 216 /* description: .*/ 217 #define MODEM_SYSCON_CLK_FE_SDM_EN (BIT(14)) 218 #define MODEM_SYSCON_CLK_FE_SDM_EN_M (MODEM_SYSCON_CLK_FE_SDM_EN_V << MODEM_SYSCON_CLK_FE_SDM_EN_S) 219 #define MODEM_SYSCON_CLK_FE_SDM_EN_V 0x00000001U 220 #define MODEM_SYSCON_CLK_FE_SDM_EN_S 14 221 /* MODEM_SYSCON_CLK_FE_ADC_EN : R/W; bitpos: [15]; default: 0; */ 222 /* description: .*/ 223 #define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(15)) 224 #define MODEM_SYSCON_CLK_FE_ADC_EN_M (MODEM_SYSCON_CLK_FE_ADC_EN_V << MODEM_SYSCON_CLK_FE_ADC_EN_S) 225 #define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x00000001U 226 #define MODEM_SYSCON_CLK_FE_ADC_EN_S 15 227 /* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0; */ 228 /* description: .*/ 229 #define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16)) 230 #define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S) 231 #define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U 232 #define MODEM_SYSCON_CLK_FE_APB_EN_S 16 233 /* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */ 234 /* description: .*/ 235 #define MODEM_SYSCON_CLK_BT_APB_EN (BIT(17)) 236 #define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S) 237 #define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U 238 #define MODEM_SYSCON_CLK_BT_APB_EN_S 17 239 /* MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0; */ 240 /* description: .*/ 241 #define MODEM_SYSCON_CLK_BT_EN (BIT(18)) 242 #define MODEM_SYSCON_CLK_BT_EN_M (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S) 243 #define MODEM_SYSCON_CLK_BT_EN_V 0x00000001U 244 #define MODEM_SYSCON_CLK_BT_EN_S 18 245 246 #define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) 247 /* MODEM_SYSCON_CLK_FE_FO : R/W; bitpos: [16]; default: 0; */ 248 /* description: .*/ 249 #define MODEM_SYSCON_CLK_FE_FO (BIT(16)) 250 #define MODEM_SYSCON_CLK_FE_FO_M (MODEM_SYSCON_CLK_FE_FO_V << MODEM_SYSCON_CLK_FE_FO_S) 251 #define MODEM_SYSCON_CLK_FE_FO_V 0x00000001U 252 #define MODEM_SYSCON_CLK_FE_FO_S 16 253 /* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */ 254 /* description: .*/ 255 #define MODEM_SYSCON_CLK_BT_FO (BIT(18)) 256 #define MODEM_SYSCON_CLK_BT_FO_M (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S) 257 #define MODEM_SYSCON_CLK_BT_FO_V 0x00000001U 258 #define MODEM_SYSCON_CLK_BT_FO_S 18 259 260 #define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) 261 /* MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0; */ 262 /* description: .*/ 263 #define MODEM_SYSCON_MODEM_MEM_WP 0x00000007U 264 #define MODEM_SYSCON_MODEM_MEM_WP_M (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S) 265 #define MODEM_SYSCON_MODEM_MEM_WP_V 0x00000007U 266 #define MODEM_SYSCON_MODEM_MEM_WP_S 0 267 /* MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 4; */ 268 /* description: .*/ 269 #define MODEM_SYSCON_MODEM_MEM_WA 0x00000007U 270 #define MODEM_SYSCON_MODEM_MEM_WA_M (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S) 271 #define MODEM_SYSCON_MODEM_MEM_WA_V 0x00000007U 272 #define MODEM_SYSCON_MODEM_MEM_WA_S 3 273 /* MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0; */ 274 /* description: .*/ 275 #define MODEM_SYSCON_MODEM_MEM_RA 0x00000003U 276 #define MODEM_SYSCON_MODEM_MEM_RA_M (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S) 277 #define MODEM_SYSCON_MODEM_MEM_RA_V 0x00000003U 278 #define MODEM_SYSCON_MODEM_MEM_RA_S 6 279 280 #define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c) 281 /* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 35685120; */ 282 /* description: .*/ 283 #define MODEM_SYSCON_DATE 0x0FFFFFFFU 284 #define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S) 285 #define MODEM_SYSCON_DATE_V 0x0FFFFFFFU 286 #define MODEM_SYSCON_DATE_S 0 287 288 #ifdef __cplusplus 289 } 290 #endif 291
