1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "modem/reg_base.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) 15 /* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */ 16 /* description: .*/ 17 #define MODEM_LPCON_CLK_EN (BIT(0)) 18 #define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S) 19 #define MODEM_LPCON_CLK_EN_V 0x00000001U 20 #define MODEM_LPCON_CLK_EN_S 0 21 22 #define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) 23 /* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */ 24 /* description: .*/ 25 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) 26 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S) 27 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U 28 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 29 /* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */ 30 /* description: .*/ 31 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) 32 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S) 33 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U 34 #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 35 /* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */ 36 /* description: .*/ 37 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) 38 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S) 39 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U 40 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 41 /* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */ 42 /* description: .*/ 43 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) 44 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S) 45 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U 46 #define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 47 /* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */ 48 /* description: .*/ 49 #define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU 50 #define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S) 51 #define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU 52 #define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 53 54 #define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) 55 /* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; */ 56 /* description: .*/ 57 #define MODEM_LPCON_CLK_COEX_EN (BIT(1)) 58 #define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S) 59 #define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U 60 #define MODEM_LPCON_CLK_COEX_EN_S 1 61 /* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */ 62 /* description: .*/ 63 #define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) 64 #define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S) 65 #define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U 66 #define MODEM_LPCON_CLK_I2C_MST_EN_S 2 67 /* MODEM_LPCON_CLK_FE_MEM_EN : R/W; bitpos: [5]; default: 0; */ 68 /* description: .*/ 69 #define MODEM_LPCON_CLK_FE_MEM_EN (BIT(5)) 70 #define MODEM_LPCON_CLK_FE_MEM_EN_M (MODEM_LPCON_CLK_FE_MEM_EN_V << MODEM_LPCON_CLK_FE_MEM_EN_S) 71 #define MODEM_LPCON_CLK_FE_MEM_EN_V 0x00000001U 72 #define MODEM_LPCON_CLK_FE_MEM_EN_S 5 73 74 #define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0xc) 75 /* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; */ 76 /* description: .*/ 77 #define MODEM_LPCON_CLK_COEX_FO (BIT(1)) 78 #define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S) 79 #define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U 80 #define MODEM_LPCON_CLK_COEX_FO_S 1 81 /* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */ 82 /* description: .*/ 83 #define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) 84 #define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S) 85 #define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U 86 #define MODEM_LPCON_CLK_I2C_MST_FO_S 2 87 /* MODEM_LPCON_CLK_FE_MEM_FO : R/W; bitpos: [5]; default: 0; */ 88 /* description: .*/ 89 #define MODEM_LPCON_CLK_FE_MEM_FO (BIT(5)) 90 #define MODEM_LPCON_CLK_FE_MEM_FO_M (MODEM_LPCON_CLK_FE_MEM_FO_V << MODEM_LPCON_CLK_FE_MEM_FO_S) 91 #define MODEM_LPCON_CLK_FE_MEM_FO_V 0x00000001U 92 #define MODEM_LPCON_CLK_FE_MEM_FO_S 5 93 94 #define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) 95 /* MODEM_LPCON_PWR_TICK_TARGET : R/W; bitpos: [5:0]; default: 31; */ 96 /* description: .*/ 97 #define MODEM_LPCON_PWR_TICK_TARGET 0x0000003FU 98 #define MODEM_LPCON_PWR_TICK_TARGET_M (MODEM_LPCON_PWR_TICK_TARGET_V << MODEM_LPCON_PWR_TICK_TARGET_S) 99 #define MODEM_LPCON_PWR_TICK_TARGET_V 0x0000003FU 100 #define MODEM_LPCON_PWR_TICK_TARGET_S 0 101 102 #define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) 103 /* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; */ 104 /* description: .*/ 105 #define MODEM_LPCON_RST_COEX (BIT(1)) 106 #define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S) 107 #define MODEM_LPCON_RST_COEX_V 0x00000001U 108 #define MODEM_LPCON_RST_COEX_S 1 109 /* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; */ 110 /* description: .*/ 111 #define MODEM_LPCON_RST_I2C_MST (BIT(2)) 112 #define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S) 113 #define MODEM_LPCON_RST_I2C_MST_V 0x00000001U 114 #define MODEM_LPCON_RST_I2C_MST_S 2 115 116 #define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) 117 /* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; */ 118 /* description: .*/ 119 #define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2)) 120 #define MODEM_LPCON_AGC_MEM_FORCE_PU_M (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S) 121 #define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x00000001U 122 #define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2 123 /* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */ 124 /* description: .*/ 125 #define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3)) 126 #define MODEM_LPCON_AGC_MEM_FORCE_PD_M (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S) 127 #define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x00000001U 128 #define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3 129 /* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; */ 130 /* description: .*/ 131 #define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4)) 132 #define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S) 133 #define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x00000001U 134 #define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4 135 /* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; */ 136 /* description: .*/ 137 #define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5)) 138 #define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S) 139 #define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x00000001U 140 #define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5 141 /* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0; */ 142 /* description: .*/ 143 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8)) 144 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S) 145 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x00000001U 146 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8 147 /* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0; */ 148 /* description: .*/ 149 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9)) 150 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S) 151 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x00000001U 152 #define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9 153 /* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0; */ 154 /* description: .*/ 155 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10)) 156 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S) 157 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x00000001U 158 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10 159 /* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0; */ 160 /* description: .*/ 161 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11)) 162 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S) 163 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x00000001U 164 #define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11 165 /* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0; */ 166 /* description: .*/ 167 #define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007U 168 #define MODEM_LPCON_MODEM_PWR_MEM_WP_M (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S) 169 #define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x00000007U 170 #define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12 171 /* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 5; */ 172 /* description: .*/ 173 #define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007U 174 #define MODEM_LPCON_MODEM_PWR_MEM_WA_M (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S) 175 #define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x00000007U 176 #define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15 177 /* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0; */ 178 /* description: .*/ 179 #define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003U 180 #define MODEM_LPCON_MODEM_PWR_MEM_RA_M (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S) 181 #define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x00000003U 182 #define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18 183 /* MODEM_LPCON_MODEM_PWR_MEM_RM : R/W; bitpos: [23:20]; default: 2; */ 184 /* description: .*/ 185 #define MODEM_LPCON_MODEM_PWR_MEM_RM 0x0000000FU 186 #define MODEM_LPCON_MODEM_PWR_MEM_RM_M (MODEM_LPCON_MODEM_PWR_MEM_RM_V << MODEM_LPCON_MODEM_PWR_MEM_RM_S) 187 #define MODEM_LPCON_MODEM_PWR_MEM_RM_V 0x0000000FU 188 #define MODEM_LPCON_MODEM_PWR_MEM_RM_S 20 189 190 #define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x1c) 191 /* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35689088; */ 192 /* description: .*/ 193 #define MODEM_LPCON_DATE 0x0FFFFFFFU 194 #define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S) 195 #define MODEM_LPCON_DATE_V 0x0FFFFFFFU 196 #define MODEM_LPCON_DATE_S 0 197 198 #ifdef __cplusplus 199 } 200 #endif 201
