1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** TWAI_MODE_REG register 15 * TWAI mode register. 16 */ 17 #define TWAI_MODE_REG(i) (REG_TWAI_BASE(i) + 0x0) 18 /** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; 19 * 1: reset, detection of a set reset mode bit results in aborting the current 20 * transmission/reception of a message and entering the reset mode. 0: normal, on the 21 * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the 22 * operating mode. 23 */ 24 #define TWAI_RESET_MODE (BIT(0)) 25 #define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) 26 #define TWAI_RESET_MODE_V 0x00000001U 27 #define TWAI_RESET_MODE_S 0 28 /** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; 29 * 1: listen only, in this mode the TWAI controller would give no acknowledge to the 30 * TWAI-bus, even if a message is received successfully. The error counters are 31 * stopped at the current value. 0: normal. 32 */ 33 #define TWAI_LISTEN_ONLY_MODE (BIT(1)) 34 #define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) 35 #define TWAI_LISTEN_ONLY_MODE_V 0x00000001U 36 #define TWAI_LISTEN_ONLY_MODE_S 1 37 /** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; 38 * 1: self test, in this mode a full node test is possible without any other active 39 * node on the bus using the self reception request command. The TWAI controller will 40 * perform a successful transmission, even if there is no acknowledge received. 0: 41 * normal, an acknowledge is required for successful transmission. 42 */ 43 #define TWAI_SELF_TEST_MODE (BIT(2)) 44 #define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) 45 #define TWAI_SELF_TEST_MODE_V 0x00000001U 46 #define TWAI_SELF_TEST_MODE_S 2 47 /** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0; 48 * 1:single, the single acceptance filter option is enabled (one filter with the 49 * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled 50 * (two filters, each with the length of 16 bit are active). 51 */ 52 #define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3)) 53 #define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S) 54 #define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U 55 #define TWAI_ACCEPTANCE_FILTER_MODE_S 3 56 57 /** TWAI_CMD_REG register 58 * TWAI command register. 59 */ 60 #define TWAI_CMD_REG(i) (REG_TWAI_BASE(i) + 0x4) 61 /** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0; 62 * 1: present, a message shall be transmitted. 0: absent 63 */ 64 #define TWAI_TX_REQUEST (BIT(0)) 65 #define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S) 66 #define TWAI_TX_REQUEST_V 0x00000001U 67 #define TWAI_TX_REQUEST_S 0 68 /** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; 69 * 1: present, if not already in progress, a pending transmission request is 70 * cancelled. 0: absent 71 */ 72 #define TWAI_ABORT_TX (BIT(1)) 73 #define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) 74 #define TWAI_ABORT_TX_V 0x00000001U 75 #define TWAI_ABORT_TX_S 1 76 /** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0; 77 * 1: released, the receive buffer, representing the message memory space in the 78 * RXFIFO is released. 0: no action 79 */ 80 #define TWAI_RELEASE_BUFFER (BIT(2)) 81 #define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S) 82 #define TWAI_RELEASE_BUFFER_V 0x00000001U 83 #define TWAI_RELEASE_BUFFER_S 2 84 /** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0; 85 * 1: clear, the data overrun status bit is cleared. 0: no action. 86 */ 87 #define TWAI_CLEAR_DATA_OVERRUN (BIT(3)) 88 #define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S) 89 #define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U 90 #define TWAI_CLEAR_DATA_OVERRUN_S 3 91 /** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0; 92 * 1: present, a message shall be transmitted and received simultaneously. 0: absent. 93 */ 94 #define TWAI_SELF_RX_REQUEST (BIT(4)) 95 #define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S) 96 #define TWAI_SELF_RX_REQUEST_V 0x00000001U 97 #define TWAI_SELF_RX_REQUEST_S 4 98 99 /** TWAI_STATUS_REG register 100 * TWAI status register. 101 */ 102 #define TWAI_STATUS_REG(i) (REG_TWAI_BASE(i) + 0x8) 103 /** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0; 104 * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no 105 * message is available 106 */ 107 #define TWAI_STATUS_RECEIVE_BUFFER (BIT(0)) 108 #define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S) 109 #define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U 110 #define TWAI_STATUS_RECEIVE_BUFFER_S 0 111 /** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0; 112 * 1: overrun, a message was lost because there was not enough space for that message 113 * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data 114 * overrun command was given 115 */ 116 #define TWAI_STATUS_OVERRUN (BIT(1)) 117 #define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S) 118 #define TWAI_STATUS_OVERRUN_V 0x00000001U 119 #define TWAI_STATUS_OVERRUN_S 1 120 /** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0; 121 * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the 122 * CPU cannot access the transmit buffer, a message is either waiting for transmission 123 * or is in the process of being transmitted 124 */ 125 #define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2)) 126 #define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S) 127 #define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U 128 #define TWAI_STATUS_TRANSMIT_BUFFER_S 2 129 /** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0; 130 * 1: complete, last requested transmission has been successfully completed. 0: 131 * incomplete, previously requested transmission is not yet completed 132 */ 133 #define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3)) 134 #define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S) 135 #define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U 136 #define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3 137 /** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0; 138 * 1: receive, the TWAI controller is receiving a message. 0: idle 139 */ 140 #define TWAI_STATUS_RECEIVE (BIT(4)) 141 #define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S) 142 #define TWAI_STATUS_RECEIVE_V 0x00000001U 143 #define TWAI_STATUS_RECEIVE_S 4 144 /** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0; 145 * 1: transmit, the TWAI controller is transmitting a message. 0: idle 146 */ 147 #define TWAI_STATUS_TRANSMIT (BIT(5)) 148 #define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S) 149 #define TWAI_STATUS_TRANSMIT_V 0x00000001U 150 #define TWAI_STATUS_TRANSMIT_S 5 151 /** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0; 152 * 1: error, at least one of the error counters has reached or exceeded the CPU 153 * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error 154 * counters are below the warning limit 155 */ 156 #define TWAI_STATUS_ERR (BIT(6)) 157 #define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S) 158 #define TWAI_STATUS_ERR_V 0x00000001U 159 #define TWAI_STATUS_ERR_S 6 160 /** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0; 161 * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the 162 * TWAI controller is involved in bus activities 163 */ 164 #define TWAI_STATUS_NODE_BUS_OFF (BIT(7)) 165 #define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S) 166 #define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U 167 #define TWAI_STATUS_NODE_BUS_OFF_S 7 168 /** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0; 169 * 1: current message is destroyed because of FIFO overflow. 170 */ 171 #define TWAI_STATUS_MISS (BIT(8)) 172 #define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S) 173 #define TWAI_STATUS_MISS_V 0x00000001U 174 #define TWAI_STATUS_MISS_S 8 175 176 /** TWAI_INTERRUPT_REG register 177 * Interrupt signals' register. 178 */ 179 #define TWAI_INTERRUPT_REG(i) (REG_TWAI_BASE(i) + 0xc) 180 /** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0; 181 * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set 182 * within the interrupt enable register. 0: reset 183 */ 184 #define TWAI_RECEIVE_INT_ST (BIT(0)) 185 #define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S) 186 #define TWAI_RECEIVE_INT_ST_V 0x00000001U 187 #define TWAI_RECEIVE_INT_ST_S 0 188 /** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0; 189 * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' 190 * (released) and the TIE bit is set within the interrupt enable register. 0: reset 191 */ 192 #define TWAI_TRANSMIT_INT_ST (BIT(1)) 193 #define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S) 194 #define TWAI_TRANSMIT_INT_ST_V 0x00000001U 195 #define TWAI_TRANSMIT_INT_ST_S 1 196 /** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0; 197 * 1: this bit is set on every change (set and clear) of either the error status or 198 * bus status bits and the EIE bit is set within the interrupt enable register. 0: 199 * reset 200 */ 201 #define TWAI_ERR_WARNING_INT_ST (BIT(2)) 202 #define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S) 203 #define TWAI_ERR_WARNING_INT_ST_V 0x00000001U 204 #define TWAI_ERR_WARNING_INT_ST_S 2 205 /** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; 206 * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the 207 * DOIE bit is set within the interrupt enable register. 0: reset 208 */ 209 #define TWAI_DATA_OVERRUN_INT_ST (BIT(3)) 210 #define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S) 211 #define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U 212 #define TWAI_DATA_OVERRUN_INT_ST_S 3 213 /** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; 214 * 1: this bit is set whenever the TWAI controller has reached the error passive 215 * status (at least one error counter exceeds the protocol-defined level of 127) or if 216 * the TWAI controller is in the error passive status and enters the error active 217 * status again and the EPIE bit is set within the interrupt enable register. 0: reset 218 */ 219 #define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) 220 #define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) 221 #define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U 222 #define TWAI_ERR_PASSIVE_INT_ST_S 5 223 /** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0; 224 * 1: this bit is set when the TWAI controller lost the arbitration and becomes a 225 * receiver and the ALIE bit is set within the interrupt enable register. 0: reset 226 */ 227 #define TWAI_ARBITRATION_LOST_INT_ST (BIT(6)) 228 #define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S) 229 #define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U 230 #define TWAI_ARBITRATION_LOST_INT_ST_S 6 231 /** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; 232 * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and 233 * the BEIE bit is set within the interrupt enable register. 0: reset 234 */ 235 #define TWAI_BUS_ERR_INT_ST (BIT(7)) 236 #define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) 237 #define TWAI_BUS_ERR_INT_ST_V 0x00000001U 238 #define TWAI_BUS_ERR_INT_ST_S 7 239 /** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0; 240 * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and 241 * this interrupt enable bit is set within the interrupt enable register. 0: reset 242 */ 243 #define TWAI_IDLE_INT_ST (BIT(8)) 244 #define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S) 245 #define TWAI_IDLE_INT_ST_V 0x00000001U 246 #define TWAI_IDLE_INT_ST_S 8 247 248 /** TWAI_INTERRUPT_ENABLE_REG register 249 * Interrupt enable register. 250 */ 251 #define TWAI_INTERRUPT_ENABLE_REG(i) (REG_TWAI_BASE(i) + 0x10) 252 /** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0; 253 * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests 254 * the respective interrupt. 0: disable 255 */ 256 #define TWAI_EXT_RECEIVE_INT_ENA (BIT(0)) 257 #define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S) 258 #define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U 259 #define TWAI_EXT_RECEIVE_INT_ENA_S 0 260 /** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0; 261 * 1: enabled, when a message has been successfully transmitted or the transmit buffer 262 * is accessible again (e.g. after an abort transmission command), the TWAI controller 263 * requests the respective interrupt. 0: disable 264 */ 265 #define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1)) 266 #define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S) 267 #define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U 268 #define TWAI_EXT_TRANSMIT_INT_ENA_S 1 269 /** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0; 270 * 1: enabled, if the error or bus status change (see status register. Table 14), the 271 * TWAI controllerrequests the respective interrupt. 0: disable 272 */ 273 #define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2)) 274 #define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S) 275 #define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U 276 #define TWAI_EXT_ERR_WARNING_INT_ENA_S 2 277 /** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; 278 * 1: enabled, if the data overrun status bit is set (see status register. Table 14), 279 * the TWAI controllerrequests the respective interrupt. 0: disable 280 */ 281 #define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3)) 282 #define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S) 283 #define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U 284 #define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3 285 /** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; 286 * 1: enabled, if the error status of the TWAI controller changes from error active to 287 * error passive or vice versa, the respective interrupt is requested. 0: disable 288 */ 289 #define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) 290 #define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) 291 #define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U 292 #define TWAI_ERR_PASSIVE_INT_ENA_S 5 293 /** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; 294 * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt 295 * is requested. 0: disable 296 */ 297 #define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6)) 298 #define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S) 299 #define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U 300 #define TWAI_ARBITRATION_LOST_INT_ENA_S 6 301 /** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; 302 * 1: enabled, if an bus error has been detected, the TWAI controller requests the 303 * respective interrupt. 0: disable 304 */ 305 #define TWAI_BUS_ERR_INT_ENA (BIT(7)) 306 #define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) 307 #define TWAI_BUS_ERR_INT_ENA_V 0x00000001U 308 #define TWAI_BUS_ERR_INT_ENA_S 7 309 /** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0; 310 * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the 311 * respective interrupt. 0: disable 312 */ 313 #define TWAI_IDLE_INT_ENA (BIT(8)) 314 #define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S) 315 #define TWAI_IDLE_INT_ENA_V 0x00000001U 316 #define TWAI_IDLE_INT_ENA_S 8 317 318 /** TWAI_BUS_TIMING_0_REG register 319 * Bit timing configuration register 0. 320 */ 321 #define TWAI_BUS_TIMING_0_REG(i) (REG_TWAI_BASE(i) + 0x18) 322 /** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0; 323 * The period of the TWAI system clock is programmable and determines the individual 324 * bit timing. Software has R/W permission in reset mode and RO permission in 325 * operation mode. 326 */ 327 #define TWAI_BAUD_PRESC 0x00003FFFU 328 #define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) 329 #define TWAI_BAUD_PRESC_V 0x00003FFFU 330 #define TWAI_BAUD_PRESC_S 0 331 /** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0; 332 * The synchronization jump width defines the maximum number of clock cycles a bit 333 * period may be shortened or lengthened. Software has R/W permission in reset mode 334 * and RO in operation mode. 335 */ 336 #define TWAI_SYNC_JUMP_WIDTH 0x00000003U 337 #define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) 338 #define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U 339 #define TWAI_SYNC_JUMP_WIDTH_S 14 340 341 /** TWAI_BUS_TIMING_1_REG register 342 * Bit timing configuration register 1. 343 */ 344 #define TWAI_BUS_TIMING_1_REG(i) (REG_TWAI_BASE(i) + 0x1c) 345 /** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0; 346 * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in 347 * reset mode and RO in operation mode. 348 */ 349 #define TWAI_TIME_SEGMENT1 0x0000000FU 350 #define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S) 351 #define TWAI_TIME_SEGMENT1_V 0x0000000FU 352 #define TWAI_TIME_SEGMENT1_S 0 353 /** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0; 354 * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in 355 * reset mode and RO in operation mode. 356 */ 357 #define TWAI_TIME_SEGMENT2 0x00000007U 358 #define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S) 359 #define TWAI_TIME_SEGMENT2_V 0x00000007U 360 #define TWAI_TIME_SEGMENT2_S 4 361 /** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0; 362 * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. 363 * Software has R/W permission in reset mode and RO in operation mode. 364 */ 365 #define TWAI_TIME_SAMPLING (BIT(7)) 366 #define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S) 367 #define TWAI_TIME_SAMPLING_V 0x00000001U 368 #define TWAI_TIME_SAMPLING_S 7 369 370 /** TWAI_ARB_LOST_CAP_REG register 371 * TWAI arbiter lost capture register. 372 */ 373 #define TWAI_ARB_LOST_CAP_REG(i) (REG_TWAI_BASE(i) + 0x2c) 374 /** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0; 375 * This register contains information about the bit position of losing arbitration. 376 */ 377 #define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU 378 #define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S) 379 #define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU 380 #define TWAI_ARBITRATION_LOST_CAPTURE_S 0 381 382 /** TWAI_ERR_CODE_CAP_REG register 383 * TWAI error info capture register. 384 */ 385 #define TWAI_ERR_CODE_CAP_REG(i) (REG_TWAI_BASE(i) + 0x30) 386 /** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0; 387 * This register contains information about the location of errors on the bus. 388 */ 389 #define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU 390 #define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S) 391 #define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU 392 #define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0 393 /** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0; 394 * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. 395 */ 396 #define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5)) 397 #define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S) 398 #define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U 399 #define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5 400 /** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0; 401 * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. 402 */ 403 #define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U 404 #define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S) 405 #define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U 406 #define TWAI_ERR_CAPTURE_CODE_TYPE_S 6 407 408 /** TWAI_ERR_WARNING_LIMIT_REG register 409 * TWAI error threshold configuration register. 410 */ 411 #define TWAI_ERR_WARNING_LIMIT_REG(i) (REG_TWAI_BASE(i) + 0x34) 412 /** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96; 413 * The threshold that trigger error warning interrupt when this interrupt is enabled. 414 * Software has R/W permission in reset mode and RO in operation mode. 415 */ 416 #define TWAI_ERR_WARNING_LIMIT 0x000000FFU 417 #define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) 418 #define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU 419 #define TWAI_ERR_WARNING_LIMIT_S 0 420 421 /** TWAI_RX_ERR_CNT_REG register 422 * Rx error counter register. 423 */ 424 #define TWAI_RX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x38) 425 /** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; 426 * The RX error counter register reflects the current value of the transmit error 427 * counter. Software has R/W permission in reset mode and RO in operation mode. 428 */ 429 #define TWAI_RX_ERR_CNT 0x000000FFU 430 #define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) 431 #define TWAI_RX_ERR_CNT_V 0x000000FFU 432 #define TWAI_RX_ERR_CNT_S 0 433 434 /** TWAI_TX_ERR_CNT_REG register 435 * Tx error counter register. 436 */ 437 #define TWAI_TX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x3c) 438 /** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; 439 * The TX error counter register reflects the current value of the transmit error 440 * counter. Software has R/W permission in reset mode and RO in operation mode. 441 */ 442 #define TWAI_TX_ERR_CNT 0x000000FFU 443 #define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) 444 #define TWAI_TX_ERR_CNT_V 0x000000FFU 445 #define TWAI_TX_ERR_CNT_S 0 446 447 /** TWAI_DATA_0_REG register 448 * Data register 0. 449 */ 450 #define TWAI_DATA_0_REG(i) (REG_TWAI_BASE(i) + 0x40) 451 /** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0; 452 * In reset mode, it is acceptance code register 0 with R/W Permission. In operation 453 * mode, when software initiate write operation, it is tx data register 0 and when 454 * software initiate read operation, it is rx data register 0. 455 */ 456 #define TWAI_DATA_0 0x000000FFU 457 #define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S) 458 #define TWAI_DATA_0_V 0x000000FFU 459 #define TWAI_DATA_0_S 0 460 461 /** TWAI_DATA_1_REG register 462 * Data register 1. 463 */ 464 #define TWAI_DATA_1_REG(i) (REG_TWAI_BASE(i) + 0x44) 465 /** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0; 466 * In reset mode, it is acceptance code register 1 with R/W Permission. In operation 467 * mode, when software initiate write operation, it is tx data register 1 and when 468 * software initiate read operation, it is rx data register 1. 469 */ 470 #define TWAI_DATA_1 0x000000FFU 471 #define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S) 472 #define TWAI_DATA_1_V 0x000000FFU 473 #define TWAI_DATA_1_S 0 474 475 /** TWAI_DATA_2_REG register 476 * Data register 2. 477 */ 478 #define TWAI_DATA_2_REG(i) (REG_TWAI_BASE(i) + 0x48) 479 /** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0; 480 * In reset mode, it is acceptance code register 2 with R/W Permission. In operation 481 * mode, when software initiate write operation, it is tx data register 2 and when 482 * software initiate read operation, it is rx data register 2. 483 */ 484 #define TWAI_DATA_2 0x000000FFU 485 #define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S) 486 #define TWAI_DATA_2_V 0x000000FFU 487 #define TWAI_DATA_2_S 0 488 489 /** TWAI_DATA_3_REG register 490 * Data register 3. 491 */ 492 #define TWAI_DATA_3_REG(i) (REG_TWAI_BASE(i) + 0x4c) 493 /** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0; 494 * In reset mode, it is acceptance code register 3 with R/W Permission. In operation 495 * mode, when software initiate write operation, it is tx data register 3 and when 496 * software initiate read operation, it is rx data register 3. 497 */ 498 #define TWAI_DATA_3 0x000000FFU 499 #define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S) 500 #define TWAI_DATA_3_V 0x000000FFU 501 #define TWAI_DATA_3_S 0 502 503 /** TWAI_DATA_4_REG register 504 * Data register 4. 505 */ 506 #define TWAI_DATA_4_REG(i) (REG_TWAI_BASE(i) + 0x50) 507 /** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0; 508 * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation 509 * mode, when software initiate write operation, it is tx data register 4 and when 510 * software initiate read operation, it is rx data register 4. 511 */ 512 #define TWAI_DATA_4 0x000000FFU 513 #define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S) 514 #define TWAI_DATA_4_V 0x000000FFU 515 #define TWAI_DATA_4_S 0 516 517 /** TWAI_DATA_5_REG register 518 * Data register 5. 519 */ 520 #define TWAI_DATA_5_REG(i) (REG_TWAI_BASE(i) + 0x54) 521 /** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0; 522 * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation 523 * mode, when software initiate write operation, it is tx data register 5 and when 524 * software initiate read operation, it is rx data register 5. 525 */ 526 #define TWAI_DATA_5 0x000000FFU 527 #define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S) 528 #define TWAI_DATA_5_V 0x000000FFU 529 #define TWAI_DATA_5_S 0 530 531 /** TWAI_DATA_6_REG register 532 * Data register 6. 533 */ 534 #define TWAI_DATA_6_REG(i) (REG_TWAI_BASE(i) + 0x58) 535 /** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0; 536 * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation 537 * mode, when software initiate write operation, it is tx data register 6 and when 538 * software initiate read operation, it is rx data register 6. 539 */ 540 #define TWAI_DATA_6 0x000000FFU 541 #define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S) 542 #define TWAI_DATA_6_V 0x000000FFU 543 #define TWAI_DATA_6_S 0 544 545 /** TWAI_DATA_7_REG register 546 * Data register 7. 547 */ 548 #define TWAI_DATA_7_REG(i) (REG_TWAI_BASE(i) + 0x5c) 549 /** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0; 550 * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation 551 * mode, when software initiate write operation, it is tx data register 7 and when 552 * software initiate read operation, it is rx data register 7. 553 */ 554 #define TWAI_DATA_7 0x000000FFU 555 #define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S) 556 #define TWAI_DATA_7_V 0x000000FFU 557 #define TWAI_DATA_7_S 0 558 559 /** TWAI_DATA_8_REG register 560 * Data register 8. 561 */ 562 #define TWAI_DATA_8_REG(i) (REG_TWAI_BASE(i) + 0x60) 563 /** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0; 564 * In reset mode, reserved with RO. In operation mode, when software initiate write 565 * operation, it is tx data register 8 and when software initiate read operation, it 566 * is rx data register 8. 567 */ 568 #define TWAI_DATA_8 0x000000FFU 569 #define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S) 570 #define TWAI_DATA_8_V 0x000000FFU 571 #define TWAI_DATA_8_S 0 572 573 /** TWAI_DATA_9_REG register 574 * Data register 9. 575 */ 576 #define TWAI_DATA_9_REG(i) (REG_TWAI_BASE(i) + 0x64) 577 /** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0; 578 * In reset mode, reserved with RO. In operation mode, when software initiate write 579 * operation, it is tx data register 9 and when software initiate read operation, it 580 * is rx data register 9. 581 */ 582 #define TWAI_DATA_9 0x000000FFU 583 #define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S) 584 #define TWAI_DATA_9_V 0x000000FFU 585 #define TWAI_DATA_9_S 0 586 587 /** TWAI_DATA_10_REG register 588 * Data register 10. 589 */ 590 #define TWAI_DATA_10_REG(i) (REG_TWAI_BASE(i) + 0x68) 591 /** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0; 592 * In reset mode, reserved with RO. In operation mode, when software initiate write 593 * operation, it is tx data register 10 and when software initiate read operation, it 594 * is rx data register 10. 595 */ 596 #define TWAI_DATA_10 0x000000FFU 597 #define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S) 598 #define TWAI_DATA_10_V 0x000000FFU 599 #define TWAI_DATA_10_S 0 600 601 /** TWAI_DATA_11_REG register 602 * Data register 11. 603 */ 604 #define TWAI_DATA_11_REG(i) (REG_TWAI_BASE(i) + 0x6c) 605 /** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0; 606 * In reset mode, reserved with RO. In operation mode, when software initiate write 607 * operation, it is tx data register 11 and when software initiate read operation, it 608 * is rx data register 11. 609 */ 610 #define TWAI_DATA_11 0x000000FFU 611 #define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S) 612 #define TWAI_DATA_11_V 0x000000FFU 613 #define TWAI_DATA_11_S 0 614 615 /** TWAI_DATA_12_REG register 616 * Data register 12. 617 */ 618 #define TWAI_DATA_12_REG(i) (REG_TWAI_BASE(i) + 0x70) 619 /** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0; 620 * In reset mode, reserved with RO. In operation mode, when software initiate write 621 * operation, it is tx data register 12 and when software initiate read operation, it 622 * is rx data register 12. 623 */ 624 #define TWAI_DATA_12 0x000000FFU 625 #define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S) 626 #define TWAI_DATA_12_V 0x000000FFU 627 #define TWAI_DATA_12_S 0 628 629 /** TWAI_RX_MESSAGE_COUNTER_REG register 630 * Received message counter register. 631 */ 632 #define TWAI_RX_MESSAGE_COUNTER_REG(i) (REG_TWAI_BASE(i) + 0x74) 633 /** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; 634 * Reflects the number of messages available within the RXFIFO. The value is 635 * incremented with each receive event and decremented by the release receive buffer 636 * command. 637 */ 638 #define TWAI_RX_MESSAGE_COUNTER 0x0000007FU 639 #define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) 640 #define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU 641 #define TWAI_RX_MESSAGE_COUNTER_S 0 642 643 /** TWAI_CLOCK_DIVIDER_REG register 644 * Clock divider register. 645 */ 646 #define TWAI_CLOCK_DIVIDER_REG(i) (REG_TWAI_BASE(i) + 0x7c) 647 /** TWAI_CD : R/W; bitpos: [7:0]; default: 0; 648 * These bits are used to define the frequency at the external CLKOUT pin. 649 */ 650 #define TWAI_CD 0x000000FFU 651 #define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) 652 #define TWAI_CD_V 0x000000FFU 653 #define TWAI_CD_S 0 654 /** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0; 655 * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has 656 * R/W permission in reset mode and RO in operation mode. 657 */ 658 #define TWAI_CLOCK_OFF (BIT(8)) 659 #define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) 660 #define TWAI_CLOCK_OFF_V 0x00000001U 661 #define TWAI_CLOCK_OFF_S 8 662 663 /** TWAI_SW_STANDBY_CFG_REG register 664 * Software configure standby pin directly. 665 */ 666 #define TWAI_SW_STANDBY_CFG_REG(i) (REG_TWAI_BASE(i) + 0x80) 667 /** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0; 668 * Enable standby pin. 669 */ 670 #define TWAI_SW_STANDBY_EN (BIT(0)) 671 #define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S) 672 #define TWAI_SW_STANDBY_EN_V 0x00000001U 673 #define TWAI_SW_STANDBY_EN_S 0 674 /** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1; 675 * Clear standby pin. 676 */ 677 #define TWAI_SW_STANDBY_CLR (BIT(1)) 678 #define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S) 679 #define TWAI_SW_STANDBY_CLR_V 0x00000001U 680 #define TWAI_SW_STANDBY_CLR_S 1 681 682 /** TWAI_HW_CFG_REG register 683 * Hardware configure standby pin. 684 */ 685 #define TWAI_HW_CFG_REG(i) (REG_TWAI_BASE(i) + 0x84) 686 /** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0; 687 * Enable function that hardware control standby pin. 688 */ 689 #define TWAI_HW_STANDBY_EN (BIT(0)) 690 #define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S) 691 #define TWAI_HW_STANDBY_EN_V 0x00000001U 692 #define TWAI_HW_STANDBY_EN_S 0 693 694 /** TWAI_HW_STANDBY_CNT_REG register 695 * Configure standby counter. 696 */ 697 #define TWAI_HW_STANDBY_CNT_REG(i) (REG_TWAI_BASE(i) + 0x88) 698 /** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1; 699 * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN 700 * is enabled. 701 */ 702 #define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU 703 #define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S) 704 #define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU 705 #define TWAI_STANDBY_WAIT_CNT_S 0 706 707 /** TWAI_IDLE_INTR_CNT_REG register 708 * Configure idle interrupt counter. 709 */ 710 #define TWAI_IDLE_INTR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x8c) 711 /** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1; 712 * Configure the number of cycles before triggering idle interrupt. 713 */ 714 #define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU 715 #define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S) 716 #define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU 717 #define TWAI_IDLE_INTR_CNT_S 0 718 719 /** TWAI_ECO_CFG_REG register 720 * ECO configuration register. 721 */ 722 #define TWAI_ECO_CFG_REG(i) (REG_TWAI_BASE(i) + 0x90) 723 /** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0; 724 * Enable eco module. 725 */ 726 #define TWAI_RDN_ENA (BIT(0)) 727 #define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S) 728 #define TWAI_RDN_ENA_V 0x00000001U 729 #define TWAI_RDN_ENA_S 0 730 /** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1; 731 * Output of eco module. 732 */ 733 #define TWAI_RDN_RESULT (BIT(1)) 734 #define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S) 735 #define TWAI_RDN_RESULT_V 0x00000001U 736 #define TWAI_RDN_RESULT_S 1 737 738 #ifdef __cplusplus 739 } 740 #endif 741
