1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ 15 #define TIMG_WDT_WKEY_VALUE 0x50D83AA1 16 17 /* Possible values for TIMG_WDT_STGx */ 18 #define TIMG_WDT_STG_SEL_OFF 0 19 #define TIMG_WDT_STG_SEL_INT 1 20 #define TIMG_WDT_STG_SEL_RESET_CPU 2 21 #define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 22 23 #define TIMG_WDT_RESET_LENGTH_100_NS 0 24 #define TIMG_WDT_RESET_LENGTH_200_NS 1 25 #define TIMG_WDT_RESET_LENGTH_300_NS 2 26 #define TIMG_WDT_RESET_LENGTH_400_NS 3 27 #define TIMG_WDT_RESET_LENGTH_500_NS 4 28 #define TIMG_WDT_RESET_LENGTH_800_NS 5 29 #define TIMG_WDT_RESET_LENGTH_1600_NS 6 30 #define TIMG_WDT_RESET_LENGTH_3200_NS 7 31 /* Possible values for TIMG_WDT_STGx */ 32 #define TIMG_WDT_STG_SEL_OFF 0 33 #define TIMG_WDT_STG_SEL_INT 1 34 #define TIMG_WDT_STG_SEL_RESET_CPU 2 35 #define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 36 37 38 /** TIMG_T0CONFIG_REG register 39 * Timer 0 configuration register 40 */ 41 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) 42 /** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; 43 * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source 44 * clock of timer group. 45 */ 46 #define TIMG_T0_USE_XTAL (BIT(9)) 47 #define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) 48 #define TIMG_T0_USE_XTAL_V 0x00000001U 49 #define TIMG_T0_USE_XTAL_S 9 50 /** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; 51 * When set, the alarm is enabled. This bit is automatically cleared once an 52 * alarm occurs. 53 */ 54 #define TIMG_T0_ALARM_EN (BIT(10)) 55 #define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) 56 #define TIMG_T0_ALARM_EN_V 0x00000001U 57 #define TIMG_T0_ALARM_EN_S 10 58 /** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; 59 * When set, Timer 0 's clock divider counter will be reset. 60 */ 61 #define TIMG_T0_DIVCNT_RST (BIT(12)) 62 #define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) 63 #define TIMG_T0_DIVCNT_RST_V 0x00000001U 64 #define TIMG_T0_DIVCNT_RST_S 12 65 /** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; 66 * Timer 0 clock (T0_clk) prescaler value. 67 */ 68 #define TIMG_T0_DIVIDER 0x0000FFFFU 69 #define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) 70 #define TIMG_T0_DIVIDER_V 0x0000FFFFU 71 #define TIMG_T0_DIVIDER_S 13 72 /** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; 73 * When set, timer 0 auto-reload at alarm is enabled. 74 */ 75 #define TIMG_T0_AUTORELOAD (BIT(29)) 76 #define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) 77 #define TIMG_T0_AUTORELOAD_V 0x00000001U 78 #define TIMG_T0_AUTORELOAD_S 29 79 /** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; 80 * When set, the timer 0 time-base counter will increment every clock tick. When 81 * cleared, the timer 0 time-base counter will decrement. 82 */ 83 #define TIMG_T0_INCREASE (BIT(30)) 84 #define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) 85 #define TIMG_T0_INCREASE_V 0x00000001U 86 #define TIMG_T0_INCREASE_S 30 87 /** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; 88 * When set, the timer 0 time-base counter is enabled. 89 */ 90 #define TIMG_T0_EN (BIT(31)) 91 #define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) 92 #define TIMG_T0_EN_V 0x00000001U 93 #define TIMG_T0_EN_S 31 94 95 /** TIMG_T0LO_REG register 96 * Timer 0 current value, low 32 bits 97 */ 98 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) 99 /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; 100 * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter 101 * of timer 0 can be read here. 102 */ 103 #define TIMG_T0_LO 0xFFFFFFFFU 104 #define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) 105 #define TIMG_T0_LO_V 0xFFFFFFFFU 106 #define TIMG_T0_LO_S 0 107 108 /** TIMG_T0HI_REG register 109 * Timer 0 current value, high 22 bits 110 */ 111 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) 112 /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; 113 * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter 114 * of timer 0 can be read here. 115 */ 116 #define TIMG_T0_HI 0x003FFFFFU 117 #define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) 118 #define TIMG_T0_HI_V 0x003FFFFFU 119 #define TIMG_T0_HI_S 0 120 121 /** TIMG_T0UPDATE_REG register 122 * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG 123 */ 124 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) 125 /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; 126 * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. 127 */ 128 #define TIMG_T0_UPDATE (BIT(31)) 129 #define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) 130 #define TIMG_T0_UPDATE_V 0x00000001U 131 #define TIMG_T0_UPDATE_S 31 132 133 /** TIMG_T0ALARMLO_REG register 134 * Timer 0 alarm value, low 32 bits 135 */ 136 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) 137 /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; 138 * Timer 0 alarm trigger time-base counter value, low 32 bits. 139 */ 140 #define TIMG_T0_ALARM_LO 0xFFFFFFFFU 141 #define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) 142 #define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU 143 #define TIMG_T0_ALARM_LO_S 0 144 145 /** TIMG_T0ALARMHI_REG register 146 * Timer 0 alarm value, high bits 147 */ 148 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) 149 /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; 150 * Timer 0 alarm trigger time-base counter value, high 22 bits. 151 */ 152 #define TIMG_T0_ALARM_HI 0x003FFFFFU 153 #define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) 154 #define TIMG_T0_ALARM_HI_V 0x003FFFFFU 155 #define TIMG_T0_ALARM_HI_S 0 156 157 /** TIMG_T0LOADLO_REG register 158 * Timer 0 reload value, low 32 bits 159 */ 160 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) 161 /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; 162 * Low 32 bits of the value that a reload will load onto timer 0 time-base 163 * Counter. 164 */ 165 #define TIMG_T0_LOAD_LO 0xFFFFFFFFU 166 #define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) 167 #define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU 168 #define TIMG_T0_LOAD_LO_S 0 169 170 /** TIMG_T0LOADHI_REG register 171 * Timer 0 reload value, high 22 bits 172 */ 173 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) 174 /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; 175 * High 22 bits of the value that a reload will load onto timer 0 time-base 176 * counter. 177 */ 178 #define TIMG_T0_LOAD_HI 0x003FFFFFU 179 #define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) 180 #define TIMG_T0_LOAD_HI_V 0x003FFFFFU 181 #define TIMG_T0_LOAD_HI_S 0 182 183 /** TIMG_T0LOAD_REG register 184 * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG 185 */ 186 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) 187 /** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; 188 * 189 * Write any value to trigger a timer 0 time-base counter reload. 190 */ 191 #define TIMG_T0_LOAD 0xFFFFFFFFU 192 #define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) 193 #define TIMG_T0_LOAD_V 0xFFFFFFFFU 194 #define TIMG_T0_LOAD_S 0 195 196 /** TIMG_WDTCONFIG0_REG register 197 * Watchdog timer configuration register 198 */ 199 #define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) 200 /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; 201 * WDT reset CPU enable. 202 */ 203 #define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) 204 #define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) 205 #define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U 206 #define TIMG_WDT_APPCPU_RESET_EN_S 12 207 /** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; 208 * WDT reset CPU enable. 209 */ 210 #define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) 211 #define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) 212 #define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U 213 #define TIMG_WDT_PROCPU_RESET_EN_S 13 214 /** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; 215 * When set, Flash boot protection is enabled. 216 */ 217 #define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) 218 #define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) 219 #define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U 220 #define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 221 /** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; 222 * System reset signal length selection. 0: 100 ns, 1: 200 ns, 223 * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. 224 */ 225 #define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U 226 #define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) 227 #define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U 228 #define TIMG_WDT_SYS_RESET_LENGTH_S 15 229 /** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; 230 * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 231 * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. 232 */ 233 #define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U 234 #define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) 235 #define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U 236 #define TIMG_WDT_CPU_RESET_LENGTH_S 18 237 /** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0; 238 * choose WDT clock:0-apb_clk, 1-xtal_clk. 239 */ 240 #define TIMG_WDT_USE_XTAL (BIT(21)) 241 #define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S) 242 #define TIMG_WDT_USE_XTAL_V 0x00000001U 243 #define TIMG_WDT_USE_XTAL_S 21 244 /** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; 245 * update the WDT configuration registers 246 */ 247 #define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) 248 #define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) 249 #define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U 250 #define TIMG_WDT_CONF_UPDATE_EN_S 22 251 /** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; 252 * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 253 */ 254 #define TIMG_WDT_STG3 0x00000003U 255 #define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) 256 #define TIMG_WDT_STG3_V 0x00000003U 257 #define TIMG_WDT_STG3_S 23 258 /** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; 259 * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 260 */ 261 #define TIMG_WDT_STG2 0x00000003U 262 #define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) 263 #define TIMG_WDT_STG2_V 0x00000003U 264 #define TIMG_WDT_STG2_S 25 265 /** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; 266 * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 267 */ 268 #define TIMG_WDT_STG1 0x00000003U 269 #define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) 270 #define TIMG_WDT_STG1_V 0x00000003U 271 #define TIMG_WDT_STG1_S 27 272 /** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; 273 * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 274 */ 275 #define TIMG_WDT_STG0 0x00000003U 276 #define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) 277 #define TIMG_WDT_STG0_V 0x00000003U 278 #define TIMG_WDT_STG0_S 29 279 /** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; 280 * When set, MWDT is enabled. 281 */ 282 #define TIMG_WDT_EN (BIT(31)) 283 #define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) 284 #define TIMG_WDT_EN_V 0x00000001U 285 #define TIMG_WDT_EN_S 31 286 287 /** TIMG_WDTCONFIG1_REG register 288 * Watchdog timer prescaler register 289 */ 290 #define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) 291 /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; 292 * When set, WDT 's clock divider counter will be reset. 293 */ 294 #define TIMG_WDT_DIVCNT_RST (BIT(0)) 295 #define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) 296 #define TIMG_WDT_DIVCNT_RST_V 0x00000001U 297 #define TIMG_WDT_DIVCNT_RST_S 0 298 /** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; 299 * MWDT clock prescaler value. MWDT clock period = 12.5 ns * 300 * TIMG_WDT_CLK_PRESCALE. 301 */ 302 #define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU 303 #define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) 304 #define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU 305 #define TIMG_WDT_CLK_PRESCALE_S 16 306 307 /** TIMG_WDTCONFIG2_REG register 308 * Watchdog timer stage 0 timeout value 309 */ 310 #define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) 311 /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; 312 * Stage 0 timeout value, in MWDT clock cycles. 313 */ 314 #define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU 315 #define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) 316 #define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU 317 #define TIMG_WDT_STG0_HOLD_S 0 318 319 /** TIMG_WDTCONFIG3_REG register 320 * Watchdog timer stage 1 timeout value 321 */ 322 #define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) 323 /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; 324 * Stage 1 timeout value, in MWDT clock cycles. 325 */ 326 #define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU 327 #define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) 328 #define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU 329 #define TIMG_WDT_STG1_HOLD_S 0 330 331 /** TIMG_WDTCONFIG4_REG register 332 * Watchdog timer stage 2 timeout value 333 */ 334 #define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) 335 /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; 336 * Stage 2 timeout value, in MWDT clock cycles. 337 */ 338 #define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU 339 #define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) 340 #define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU 341 #define TIMG_WDT_STG2_HOLD_S 0 342 343 /** TIMG_WDTCONFIG5_REG register 344 * Watchdog timer stage 3 timeout value 345 */ 346 #define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) 347 /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; 348 * Stage 3 timeout value, in MWDT clock cycles. 349 */ 350 #define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU 351 #define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) 352 #define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU 353 #define TIMG_WDT_STG3_HOLD_S 0 354 355 /** TIMG_WDTFEED_REG register 356 * Write to feed the watchdog timer 357 */ 358 #define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) 359 /** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; 360 * Write any value to feed the MWDT. (WO) 361 */ 362 #define TIMG_WDT_FEED 0xFFFFFFFFU 363 #define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) 364 #define TIMG_WDT_FEED_V 0xFFFFFFFFU 365 #define TIMG_WDT_FEED_S 0 366 367 /** TIMG_WDTWPROTECT_REG register 368 * Watchdog write protect register 369 */ 370 #define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) 371 /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; 372 * If the register contains a different value than its reset value, write 373 * protection is enabled. 374 */ 375 #define TIMG_WDT_WKEY 0xFFFFFFFFU 376 #define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) 377 #define TIMG_WDT_WKEY_V 0xFFFFFFFFU 378 #define TIMG_WDT_WKEY_S 0 379 380 /** TIMG_RTCCALICFG_REG register 381 * RTC calibration configure register 382 */ 383 #define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) 384 /** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; 385 * 0: one-shot frequency calculation,1: periodic frequency calculation, 386 */ 387 #define TIMG_RTC_CALI_START_CYCLING (BIT(12)) 388 #define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) 389 #define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U 390 #define TIMG_RTC_CALI_START_CYCLING_S 12 391 /** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; 392 * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. 393 */ 394 #define TIMG_RTC_CALI_CLK_SEL 0x00000003U 395 #define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) 396 #define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U 397 #define TIMG_RTC_CALI_CLK_SEL_S 13 398 /** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; 399 * indicate one-shot frequency calculation is done. 400 */ 401 #define TIMG_RTC_CALI_RDY (BIT(15)) 402 #define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) 403 #define TIMG_RTC_CALI_RDY_V 0x00000001U 404 #define TIMG_RTC_CALI_RDY_S 15 405 /** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; 406 * Configure the time to calculate RTC slow clock's frequency. 407 */ 408 #define TIMG_RTC_CALI_MAX 0x00007FFFU 409 #define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) 410 #define TIMG_RTC_CALI_MAX_V 0x00007FFFU 411 #define TIMG_RTC_CALI_MAX_S 16 412 /** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; 413 * Set this bit to start one-shot frequency calculation. 414 */ 415 #define TIMG_RTC_CALI_START (BIT(31)) 416 #define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) 417 #define TIMG_RTC_CALI_START_V 0x00000001U 418 #define TIMG_RTC_CALI_START_S 31 419 420 /** TIMG_RTCCALICFG1_REG register 421 * RTC calibration configure1 register 422 */ 423 #define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) 424 /** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; 425 * indicate periodic frequency calculation is done. 426 */ 427 #define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) 428 #define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) 429 #define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U 430 #define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 431 /** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; 432 * When one-shot or periodic frequency calculation is done, read this value to 433 * calculate RTC slow clock's frequency. 434 */ 435 #define TIMG_RTC_CALI_VALUE 0x01FFFFFFU 436 #define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) 437 #define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU 438 #define TIMG_RTC_CALI_VALUE_S 7 439 440 /** TIMG_INT_ENA_TIMERS_REG register 441 * Interrupt enable bits 442 */ 443 #define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) 444 /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; 445 * The interrupt enable bit for the TIMG_T$x_INT interrupt. 446 */ 447 #define TIMG_T0_INT_ENA (BIT(0)) 448 #define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) 449 #define TIMG_T0_INT_ENA_V 0x00000001U 450 #define TIMG_T0_INT_ENA_S 0 451 /** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0; 452 * The interrupt enable bit for the TIMG_WDT_INT interrupt. 453 */ 454 #define TIMG_WDT_INT_ENA (BIT(1)) 455 #define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) 456 #define TIMG_WDT_INT_ENA_V 0x00000001U 457 #define TIMG_WDT_INT_ENA_S 1 458 459 /** TIMG_INT_RAW_TIMERS_REG register 460 * Raw interrupt status 461 */ 462 #define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) 463 /** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; 464 * The raw interrupt status bit for the TIMG_T$x_INT interrupt. 465 */ 466 #define TIMG_T0_INT_RAW (BIT(0)) 467 #define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) 468 #define TIMG_T0_INT_RAW_V 0x00000001U 469 #define TIMG_T0_INT_RAW_S 0 470 /** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; 471 * The raw interrupt status bit for the TIMG_WDT_INT interrupt. 472 */ 473 #define TIMG_WDT_INT_RAW (BIT(1)) 474 #define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) 475 #define TIMG_WDT_INT_RAW_V 0x00000001U 476 #define TIMG_WDT_INT_RAW_S 1 477 478 /** TIMG_INT_ST_TIMERS_REG register 479 * Masked interrupt status 480 */ 481 #define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) 482 /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; 483 * The masked interrupt status bit for the TIMG_T$x_INT interrupt. 484 */ 485 #define TIMG_T0_INT_ST (BIT(0)) 486 #define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) 487 #define TIMG_T0_INT_ST_V 0x00000001U 488 #define TIMG_T0_INT_ST_S 0 489 /** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0; 490 * The masked interrupt status bit for the TIMG_WDT_INT interrupt. 491 */ 492 #define TIMG_WDT_INT_ST (BIT(1)) 493 #define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) 494 #define TIMG_WDT_INT_ST_V 0x00000001U 495 #define TIMG_WDT_INT_ST_S 1 496 497 /** TIMG_INT_CLR_TIMERS_REG register 498 * Interrupt clear bits 499 */ 500 #define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c) 501 /** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; 502 * Set this bit to clear the TIMG_T$x_INT interrupt. 503 */ 504 #define TIMG_T0_INT_CLR (BIT(0)) 505 #define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) 506 #define TIMG_T0_INT_CLR_V 0x00000001U 507 #define TIMG_T0_INT_CLR_S 0 508 /** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0; 509 * Set this bit to clear the TIMG_WDT_INT interrupt. 510 */ 511 #define TIMG_WDT_INT_CLR (BIT(1)) 512 #define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) 513 #define TIMG_WDT_INT_CLR_V 0x00000001U 514 #define TIMG_WDT_INT_CLR_S 1 515 516 /** TIMG_RTCCALICFG2_REG register 517 * Timer group calibration register 518 */ 519 #define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) 520 /** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; 521 * RTC calibration timeout indicator 522 */ 523 #define TIMG_RTC_CALI_TIMEOUT (BIT(0)) 524 #define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) 525 #define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U 526 #define TIMG_RTC_CALI_TIMEOUT_S 0 527 /** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; 528 * Cycles that release calibration timeout reset 529 */ 530 #define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU 531 #define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) 532 #define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU 533 #define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 534 /** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; 535 * Threshold value for the RTC calibration timer. If the calibration timer's value 536 * exceeds this threshold, a timeout is triggered. 537 */ 538 #define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU 539 #define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) 540 #define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU 541 #define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 542 543 /** TIMG_NTIMERS_DATE_REG register 544 * Timer version control register 545 */ 546 #define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8) 547 /** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35676274; 548 * Timer version control register 549 */ 550 #define TIMG_NTIMGS_DATE 0x0FFFFFFFU 551 #define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) 552 #define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU 553 #define TIMG_NTIMGS_DATE_S 0 554 555 /** TIMG_REGCLK_REG register 556 * Timer group clock gate register 557 */ 558 #define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) 559 /** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; 560 * enable timer's etm task and event 561 */ 562 #define TIMG_ETM_EN (BIT(28)) 563 #define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) 564 #define TIMG_ETM_EN_V 0x00000001U 565 #define TIMG_ETM_EN_S 28 566 /** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1; 567 * enable WDT's clock 568 */ 569 #define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) 570 #define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S) 571 #define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U 572 #define TIMG_WDT_CLK_IS_ACTIVE_S 29 573 /** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1; 574 * enable Timer $x's clock 575 */ 576 #define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) 577 #define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S) 578 #define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U 579 #define TIMG_TIMER_CLK_IS_ACTIVE_S 30 580 /** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; 581 * Register clock gate signal. 1: Registers can be read and written to by software. 0: 582 * Registers can not be read or written to by software. 583 */ 584 #define TIMG_CLK_EN (BIT(31)) 585 #define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) 586 #define TIMG_CLK_EN_V 0x00000001U 587 #define TIMG_CLK_EN_S 31 588 589 #ifdef __cplusplus 590 } 591 #endif 592
