1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** LP_I2C_ANA_MST_I2C0_CTRL_REG register 15 * need_des 16 */ 17 #define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0) 18 /** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; 19 * need_des 20 */ 21 #define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU 22 #define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S) 23 #define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU 24 #define LP_I2C_ANA_MST_I2C0_CTRL_S 0 25 /** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; 26 * need_des 27 */ 28 #define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25)) 29 #define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S) 30 #define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U 31 #define LP_I2C_ANA_MST_I2C0_BUSY_S 25 32 33 /** LP_I2C_ANA_MST_I2C0_CONF_REG register 34 * need_des 35 */ 36 #define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4) 37 /** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; 38 * need_des 39 */ 40 #define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU 41 #define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S) 42 #define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU 43 #define LP_I2C_ANA_MST_I2C0_CONF_S 0 44 /** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7; 45 * reserved 46 */ 47 #define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU 48 #define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S) 49 #define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU 50 #define LP_I2C_ANA_MST_I2C0_STATUS_S 24 51 52 /** LP_I2C_ANA_MST_I2C0_DATA_REG register 53 * need_des 54 */ 55 #define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8) 56 /** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0; 57 * need_des 58 */ 59 #define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU 60 #define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S) 61 #define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU 62 #define LP_I2C_ANA_MST_I2C0_RDATA_S 0 63 /** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1; 64 * need_des 65 */ 66 #define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U 67 #define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S) 68 #define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U 69 #define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8 70 /** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1; 71 * need des 72 */ 73 #define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11)) 74 #define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S) 75 #define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U 76 #define LP_I2C_ANA_MST_I2C_MST_SEL_S 11 77 78 /** LP_I2C_ANA_MST_ANA_CONF1_REG register 79 * need_des 80 */ 81 #define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc) 82 /** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; 83 * need_des 84 */ 85 #define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU 86 #define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S) 87 #define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU 88 #define LP_I2C_ANA_MST_ANA_CONF1_S 0 89 90 /** LP_I2C_ANA_MST_NOUSE_REG register 91 * need_des 92 */ 93 #define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10) 94 /** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; 95 * need_des 96 */ 97 #define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU 98 #define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S) 99 #define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU 100 #define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0 101 102 /** LP_I2C_ANA_MST_DEVICE_EN_REG register 103 * need_des 104 */ 105 #define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14) 106 /** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0; 107 * need_des 108 */ 109 #define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU 110 #define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S) 111 #define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU 112 #define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0 113 114 /** LP_I2C_ANA_MST_DATE_REG register 115 * need_des 116 */ 117 #define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc) 118 /** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873; 119 * need_des 120 */ 121 #define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU 122 #define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S) 123 #define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU 124 #define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0 125 /** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0; 126 * need_des 127 */ 128 #define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28)) 129 #define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S) 130 #define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U 131 #define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28 132 133 #ifdef __cplusplus 134 } 135 #endif 136
