1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** LP_CLKRST_LP_CLK_CONF_REG register 15 * need_des 16 */ 17 #define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) 18 /** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; 19 * need_des 20 */ 21 #define LP_CLKRST_SLOW_CLK_SEL 0x00000003U 22 #define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) 23 #define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U 24 #define LP_CLKRST_SLOW_CLK_SEL_S 0 25 /** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1; 26 * need_des 27 */ 28 #define LP_CLKRST_FAST_CLK_SEL (BIT(2)) 29 #define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) 30 #define LP_CLKRST_FAST_CLK_SEL_V 0x00000001U 31 #define LP_CLKRST_FAST_CLK_SEL_S 2 32 /** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0; 33 * need_des 34 */ 35 #define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU 36 #define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) 37 #define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU 38 #define LP_CLKRST_LP_PERI_DIV_NUM_S 3 39 40 /** LP_CLKRST_LP_CLK_PO_EN_REG register 41 * need_des 42 */ 43 #define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) 44 /** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; 45 * need_des 46 */ 47 #define LP_CLKRST_AON_SLOW_OEN (BIT(0)) 48 #define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) 49 #define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U 50 #define LP_CLKRST_AON_SLOW_OEN_S 0 51 /** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; 52 * need_des 53 */ 54 #define LP_CLKRST_AON_FAST_OEN (BIT(1)) 55 #define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) 56 #define LP_CLKRST_AON_FAST_OEN_V 0x00000001U 57 #define LP_CLKRST_AON_FAST_OEN_S 1 58 /** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; 59 * need_des 60 */ 61 #define LP_CLKRST_SOSC_OEN (BIT(2)) 62 #define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) 63 #define LP_CLKRST_SOSC_OEN_V 0x00000001U 64 #define LP_CLKRST_SOSC_OEN_S 2 65 /** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; 66 * need_des 67 */ 68 #define LP_CLKRST_FOSC_OEN (BIT(3)) 69 #define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) 70 #define LP_CLKRST_FOSC_OEN_V 0x00000001U 71 #define LP_CLKRST_FOSC_OEN_S 3 72 /** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; 73 * need_des 74 */ 75 #define LP_CLKRST_OSC32K_OEN (BIT(4)) 76 #define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) 77 #define LP_CLKRST_OSC32K_OEN_V 0x00000001U 78 #define LP_CLKRST_OSC32K_OEN_S 4 79 /** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; 80 * need_des 81 */ 82 #define LP_CLKRST_XTAL32K_OEN (BIT(5)) 83 #define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) 84 #define LP_CLKRST_XTAL32K_OEN_V 0x00000001U 85 #define LP_CLKRST_XTAL32K_OEN_S 5 86 /** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; 87 * need_des 88 */ 89 #define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) 90 #define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) 91 #define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U 92 #define LP_CLKRST_CORE_EFUSE_OEN_S 6 93 /** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; 94 * need_des 95 */ 96 #define LP_CLKRST_SLOW_OEN (BIT(7)) 97 #define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) 98 #define LP_CLKRST_SLOW_OEN_V 0x00000001U 99 #define LP_CLKRST_SLOW_OEN_S 7 100 /** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; 101 * need_des 102 */ 103 #define LP_CLKRST_FAST_OEN (BIT(8)) 104 #define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) 105 #define LP_CLKRST_FAST_OEN_V 0x00000001U 106 #define LP_CLKRST_FAST_OEN_S 8 107 /** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; 108 * need_des 109 */ 110 #define LP_CLKRST_RNG_OEN (BIT(9)) 111 #define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) 112 #define LP_CLKRST_RNG_OEN_V 0x00000001U 113 #define LP_CLKRST_RNG_OEN_S 9 114 /** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; 115 * need_des 116 */ 117 #define LP_CLKRST_LPBUS_OEN (BIT(10)) 118 #define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) 119 #define LP_CLKRST_LPBUS_OEN_V 0x00000001U 120 #define LP_CLKRST_LPBUS_OEN_S 10 121 122 /** LP_CLKRST_LP_CLK_EN_REG register 123 * need_des 124 */ 125 #define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) 126 /** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; 127 * need_des 128 */ 129 #define LP_CLKRST_FAST_ORI_GATE (BIT(31)) 130 #define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) 131 #define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U 132 #define LP_CLKRST_FAST_ORI_GATE_S 31 133 134 /** LP_CLKRST_LP_RST_EN_REG register 135 * need_des 136 */ 137 #define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) 138 /** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; 139 * need_des 140 */ 141 #define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) 142 #define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) 143 #define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U 144 #define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 145 /** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; 146 * need_des 147 */ 148 #define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) 149 #define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) 150 #define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U 151 #define LP_CLKRST_LP_TIMER_RESET_EN_S 29 152 /** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; 153 * need_des 154 */ 155 #define LP_CLKRST_WDT_RESET_EN (BIT(30)) 156 #define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) 157 #define LP_CLKRST_WDT_RESET_EN_V 0x00000001U 158 #define LP_CLKRST_WDT_RESET_EN_S 30 159 /** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; 160 * need_des 161 */ 162 #define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) 163 #define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) 164 #define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U 165 #define LP_CLKRST_ANA_PERI_RESET_EN_S 31 166 167 /** LP_CLKRST_RESET_CAUSE_REG register 168 * need_des 169 */ 170 #define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) 171 /** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; 172 * need_des 173 */ 174 #define LP_CLKRST_RESET_CAUSE 0x0000001FU 175 #define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) 176 #define LP_CLKRST_RESET_CAUSE_V 0x0000001FU 177 #define LP_CLKRST_RESET_CAUSE_S 0 178 /** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; 179 * need_des 180 */ 181 #define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) 182 #define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) 183 #define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U 184 #define LP_CLKRST_CORE0_RESET_FLAG_S 5 185 /** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; 186 * need_des 187 */ 188 #define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) 189 #define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) 190 #define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U 191 #define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 192 /** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; 193 * need_des 194 */ 195 #define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) 196 #define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) 197 #define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U 198 #define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 199 /** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; 200 * need_des 201 */ 202 #define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) 203 #define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) 204 #define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U 205 #define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 206 207 /** LP_CLKRST_CPU_RESET_REG register 208 * need_des 209 */ 210 #define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) 211 /** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; 212 * need_des 213 */ 214 #define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U 215 #define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) 216 #define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U 217 #define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 218 /** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; 219 * need_des 220 */ 221 #define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) 222 #define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) 223 #define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U 224 #define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 225 /** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; 226 * need_des 227 */ 228 #define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU 229 #define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) 230 #define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU 231 #define LP_CLKRST_CPU_STALL_WAIT_S 26 232 /** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; 233 * need_des 234 */ 235 #define LP_CLKRST_CPU_STALL_EN (BIT(31)) 236 #define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) 237 #define LP_CLKRST_CPU_STALL_EN_V 0x00000001U 238 #define LP_CLKRST_CPU_STALL_EN_S 31 239 240 /** LP_CLKRST_FOSC_CNTL_REG register 241 * need_des 242 */ 243 #define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) 244 /** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; 245 * need_des 246 */ 247 #define LP_CLKRST_FOSC_DFREQ 0x000003FFU 248 #define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) 249 #define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU 250 #define LP_CLKRST_FOSC_DFREQ_S 22 251 252 /** LP_CLKRST_RC32K_CNTL_REG register 253 * need_des 254 */ 255 #define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) 256 /** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172; 257 * need_des 258 */ 259 #define LP_CLKRST_RC32K_DFREQ 0x000003FFU 260 #define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) 261 #define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU 262 #define LP_CLKRST_RC32K_DFREQ_S 22 263 264 /** LP_CLKRST_CLK_TO_HP_REG register 265 * need_des 266 */ 267 #define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) 268 /** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; 269 * need_des 270 */ 271 #define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) 272 #define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) 273 #define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U 274 #define LP_CLKRST_ICG_HP_XTAL32K_S 28 275 /** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; 276 * need_des 277 */ 278 #define LP_CLKRST_ICG_HP_SOSC (BIT(29)) 279 #define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) 280 #define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U 281 #define LP_CLKRST_ICG_HP_SOSC_S 29 282 /** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; 283 * need_des 284 */ 285 #define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) 286 #define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) 287 #define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U 288 #define LP_CLKRST_ICG_HP_OSC32K_S 30 289 /** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; 290 * need_des 291 */ 292 #define LP_CLKRST_ICG_HP_FOSC (BIT(31)) 293 #define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) 294 #define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U 295 #define LP_CLKRST_ICG_HP_FOSC_S 31 296 297 /** LP_CLKRST_LPMEM_FORCE_REG register 298 * need_des 299 */ 300 #define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) 301 /** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; 302 * need_des 303 */ 304 #define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) 305 #define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) 306 #define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U 307 #define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 308 309 /** LP_CLKRST_LPPERI_REG register 310 * need_des 311 */ 312 #define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) 313 /** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; 314 * need_des 315 */ 316 #define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) 317 #define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) 318 #define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U 319 #define LP_CLKRST_LP_I2C_CLK_SEL_S 30 320 /** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; 321 * need_des 322 */ 323 #define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) 324 #define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) 325 #define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U 326 #define LP_CLKRST_LP_UART_CLK_SEL_S 31 327 328 /** LP_CLKRST_XTAL32K_REG register 329 * need_des 330 */ 331 #define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) 332 /** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; 333 * need_des 334 */ 335 #define LP_CLKRST_DRES_XTAL32K 0x00000007U 336 #define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) 337 #define LP_CLKRST_DRES_XTAL32K_V 0x00000007U 338 #define LP_CLKRST_DRES_XTAL32K_S 22 339 /** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; 340 * need_des 341 */ 342 #define LP_CLKRST_DGM_XTAL32K 0x00000007U 343 #define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) 344 #define LP_CLKRST_DGM_XTAL32K_V 0x00000007U 345 #define LP_CLKRST_DGM_XTAL32K_S 25 346 /** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; 347 * need_des 348 */ 349 #define LP_CLKRST_DBUF_XTAL32K (BIT(28)) 350 #define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) 351 #define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U 352 #define LP_CLKRST_DBUF_XTAL32K_S 28 353 /** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; 354 * need_des 355 */ 356 #define LP_CLKRST_DAC_XTAL32K 0x00000007U 357 #define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) 358 #define LP_CLKRST_DAC_XTAL32K_V 0x00000007U 359 #define LP_CLKRST_DAC_XTAL32K_S 29 360 361 /** LP_CLKRST_DATE_REG register 362 * need_des 363 */ 364 #define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) 365 /** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35676304; 366 * need_des 367 */ 368 #define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU 369 #define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) 370 #define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU 371 #define LP_CLKRST_CLKRST_DATE_S 0 372 /** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; 373 * need_des 374 */ 375 #define LP_CLKRST_CLK_EN (BIT(31)) 376 #define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) 377 #define LP_CLKRST_CLK_EN_V 0x00000001U 378 #define LP_CLKRST_CLK_EN_S 31 379 380 #ifdef __cplusplus 381 } 382 #endif 383
