1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** GPIO_BT_SELECT_REG register 15 * GPIO bit select register 16 */ 17 #define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) 18 /** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; 19 * GPIO bit select register 20 */ 21 #define GPIO_BT_SEL 0xFFFFFFFFU 22 #define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) 23 #define GPIO_BT_SEL_V 0xFFFFFFFFU 24 #define GPIO_BT_SEL_S 0 25 26 /** GPIO_OUT_REG register 27 * GPIO output register for GPIO0-31 28 */ 29 #define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) 30 /** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0; 31 * GPIO output register for GPIO0-31 32 */ 33 #define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU 34 #define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) 35 #define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFFU 36 #define GPIO_OUT_DATA_ORIG_S 0 37 38 /** GPIO_OUT_W1TS_REG register 39 * GPIO output set register for GPIO0-31 40 */ 41 #define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) 42 /** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; 43 * GPIO output set register for GPIO0-31 44 */ 45 #define GPIO_OUT_W1TS 0xFFFFFFFFU 46 #define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) 47 #define GPIO_OUT_W1TS_V 0xFFFFFFFFU 48 #define GPIO_OUT_W1TS_S 0 49 50 /** GPIO_OUT_W1TC_REG register 51 * GPIO output clear register for GPIO0-31 52 */ 53 #define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) 54 /** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; 55 * GPIO output clear register for GPIO0-31 56 */ 57 #define GPIO_OUT_W1TC 0xFFFFFFFFU 58 #define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) 59 #define GPIO_OUT_W1TC_V 0xFFFFFFFFU 60 #define GPIO_OUT_W1TC_S 0 61 62 /** GPIO_OUT1_REG register 63 * GPIO output register for GPIO32-34 64 */ 65 #define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) 66 /** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [2:0]; default: 0; 67 * GPIO output register for GPIO32-34 68 */ 69 #define GPIO_OUT1_DATA_ORIG 0x00000007U 70 #define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) 71 #define GPIO_OUT1_DATA_ORIG_V 0x00000007U 72 #define GPIO_OUT1_DATA_ORIG_S 0 73 74 /** GPIO_OUT1_W1TS_REG register 75 * GPIO output set register for GPIO32-34 76 */ 77 #define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) 78 /** GPIO_OUT1_W1TS : WT; bitpos: [2:0]; default: 0; 79 * GPIO output set register for GPIO32-34 80 */ 81 #define GPIO_OUT1_W1TS 0x00000007U 82 #define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) 83 #define GPIO_OUT1_W1TS_V 0x00000007U 84 #define GPIO_OUT1_W1TS_S 0 85 86 /** GPIO_OUT1_W1TC_REG register 87 * GPIO output clear register for GPIO32-34 88 */ 89 #define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) 90 /** GPIO_OUT1_W1TC : WT; bitpos: [2:0]; default: 0; 91 * GPIO output clear register for GPIO32-34 92 */ 93 #define GPIO_OUT1_W1TC 0x00000007U 94 #define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) 95 #define GPIO_OUT1_W1TC_V 0x00000007U 96 #define GPIO_OUT1_W1TC_S 0 97 98 /** GPIO_SDIO_SELECT_REG register 99 * GPIO sdio select register 100 */ 101 #define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) 102 /** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; 103 * GPIO sdio select register 104 */ 105 #define GPIO_SDIO_SEL 0x000000FFU 106 #define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) 107 #define GPIO_SDIO_SEL_V 0x000000FFU 108 #define GPIO_SDIO_SEL_S 0 109 110 /** GPIO_ENABLE_REG register 111 * GPIO output enable register for GPIO0-31 112 */ 113 #define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) 114 /** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0; 115 * GPIO output enable register for GPIO0-31 116 */ 117 #define GPIO_ENABLE_DATA 0xFFFFFFFFU 118 #define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) 119 #define GPIO_ENABLE_DATA_V 0xFFFFFFFFU 120 #define GPIO_ENABLE_DATA_S 0 121 122 /** GPIO_ENABLE_W1TS_REG register 123 * GPIO output enable set register for GPIO0-31 124 */ 125 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) 126 /** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; 127 * GPIO output enable set register for GPIO0-31 128 */ 129 #define GPIO_ENABLE_W1TS 0xFFFFFFFFU 130 #define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) 131 #define GPIO_ENABLE_W1TS_V 0xFFFFFFFFU 132 #define GPIO_ENABLE_W1TS_S 0 133 134 /** GPIO_ENABLE_W1TC_REG register 135 * GPIO output enable clear register for GPIO0-31 136 */ 137 #define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) 138 /** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; 139 * GPIO output enable clear register for GPIO0-31 140 */ 141 #define GPIO_ENABLE_W1TC 0xFFFFFFFFU 142 #define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) 143 #define GPIO_ENABLE_W1TC_V 0xFFFFFFFFU 144 #define GPIO_ENABLE_W1TC_S 0 145 146 /** GPIO_ENABLE1_REG register 147 * GPIO output enable register for GPIO32-34 148 */ 149 #define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c) 150 /** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [2:0]; default: 0; 151 * GPIO output enable register for GPIO32-34 152 */ 153 #define GPIO_ENABLE1_DATA 0x00000007U 154 #define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) 155 #define GPIO_ENABLE1_DATA_V 0x00000007U 156 #define GPIO_ENABLE1_DATA_S 0 157 158 /** GPIO_ENABLE1_W1TS_REG register 159 * GPIO output enable set register for GPIO32-34 160 */ 161 #define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) 162 /** GPIO_ENABLE1_W1TS : WT; bitpos: [2:0]; default: 0; 163 * GPIO output enable set register for GPIO32-34 164 */ 165 #define GPIO_ENABLE1_W1TS 0x00000007U 166 #define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) 167 #define GPIO_ENABLE1_W1TS_V 0x00000007U 168 #define GPIO_ENABLE1_W1TS_S 0 169 170 /** GPIO_ENABLE1_W1TC_REG register 171 * GPIO output enable clear register for GPIO32-34 172 */ 173 #define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) 174 /** GPIO_ENABLE1_W1TC : WT; bitpos: [2:0]; default: 0; 175 * GPIO output enable clear register for GPIO32-34 176 */ 177 #define GPIO_ENABLE1_W1TC 0x00000007U 178 #define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) 179 #define GPIO_ENABLE1_W1TC_V 0x00000007U 180 #define GPIO_ENABLE1_W1TC_S 0 181 182 /** GPIO_STRAP_REG register 183 * pad strapping register 184 */ 185 #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) 186 /** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; 187 * pad strapping register 188 */ 189 #define GPIO_STRAPPING 0x0000FFFFU 190 #define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) 191 #define GPIO_STRAPPING_V 0x0000FFFFU 192 #define GPIO_STRAPPING_S 0 193 194 /** GPIO_IN_REG register 195 * GPIO input register for GPIO0-31 196 */ 197 #define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) 198 /** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; 199 * GPIO input register for GPIO0-31 200 */ 201 #define GPIO_IN_DATA_NEXT 0xFFFFFFFFU 202 #define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) 203 #define GPIO_IN_DATA_NEXT_V 0xFFFFFFFFU 204 #define GPIO_IN_DATA_NEXT_S 0 205 206 /** GPIO_IN1_REG register 207 * GPIO input register for GPIO32-34 208 */ 209 #define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) 210 /** GPIO_IN1_DATA_NEXT : RO; bitpos: [2:0]; default: 0; 211 * GPIO input register for GPIO32-34 212 */ 213 #define GPIO_IN1_DATA_NEXT 0x00000007U 214 #define GPIO_IN1_DATA_NEXT_M (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S) 215 #define GPIO_IN1_DATA_NEXT_V 0x00000007U 216 #define GPIO_IN1_DATA_NEXT_S 0 217 218 /** GPIO_STATUS_REG register 219 * GPIO interrupt status register for GPIO0-31 220 */ 221 #define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) 222 /** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0; 223 * GPIO interrupt status register for GPIO0-31 224 */ 225 #define GPIO_STATUS_INTERRUPT 0xFFFFFFFFU 226 #define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) 227 #define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFFU 228 #define GPIO_STATUS_INTERRUPT_S 0 229 230 /** GPIO_STATUS_W1TS_REG register 231 * GPIO interrupt status set register for GPIO0-31 232 */ 233 #define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) 234 /** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0; 235 * GPIO interrupt status set register for GPIO0-31 236 */ 237 #define GPIO_STATUS_W1TS 0xFFFFFFFFU 238 #define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) 239 #define GPIO_STATUS_W1TS_V 0xFFFFFFFFU 240 #define GPIO_STATUS_W1TS_S 0 241 242 /** GPIO_STATUS_W1TC_REG register 243 * GPIO interrupt status clear register for GPIO0-31 244 */ 245 #define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) 246 /** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0; 247 * GPIO interrupt status clear register for GPIO0-31 248 */ 249 #define GPIO_STATUS_W1TC 0xFFFFFFFFU 250 #define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) 251 #define GPIO_STATUS_W1TC_V 0xFFFFFFFFU 252 #define GPIO_STATUS_W1TC_S 0 253 254 /** GPIO_STATUS1_REG register 255 * GPIO interrupt status register for GPIO32-34 256 */ 257 #define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) 258 /** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [2:0]; default: 0; 259 * GPIO interrupt status register for GPIO32-34 260 */ 261 #define GPIO_STATUS1_INTERRUPT 0x00000007U 262 #define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) 263 #define GPIO_STATUS1_INTERRUPT_V 0x00000007U 264 #define GPIO_STATUS1_INTERRUPT_S 0 265 266 /** GPIO_STATUS1_W1TS_REG register 267 * GPIO interrupt status set register for GPIO32-34 268 */ 269 #define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) 270 /** GPIO_STATUS1_W1TS : WT; bitpos: [2:0]; default: 0; 271 * GPIO interrupt status set register for GPIO32-34 272 */ 273 #define GPIO_STATUS1_W1TS 0x00000007U 274 #define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) 275 #define GPIO_STATUS1_W1TS_V 0x00000007U 276 #define GPIO_STATUS1_W1TS_S 0 277 278 /** GPIO_STATUS1_W1TC_REG register 279 * GPIO interrupt status clear register for GPIO32-34 280 */ 281 #define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) 282 /** GPIO_STATUS1_W1TC : WT; bitpos: [2:0]; default: 0; 283 * GPIO interrupt status clear register for GPIO32-34 284 */ 285 #define GPIO_STATUS1_W1TC 0x00000007U 286 #define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) 287 #define GPIO_STATUS1_W1TC_V 0x00000007U 288 #define GPIO_STATUS1_W1TC_S 0 289 290 /** GPIO_PCPU_INT_REG register 291 * GPIO PRO_CPU interrupt status register for GPIO0-31 292 */ 293 #define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) 294 /** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; 295 * GPIO PRO_CPU interrupt status register for GPIO0-31 296 */ 297 #define GPIO_PROCPU_INT 0xFFFFFFFFU 298 #define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) 299 #define GPIO_PROCPU_INT_V 0xFFFFFFFFU 300 #define GPIO_PROCPU_INT_S 0 301 302 /** GPIO_PCPU_NMI_INT_REG register 303 * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 304 */ 305 #define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) 306 /** GPIO_PROCPU_NMI_INT : RO; bitpos: [31:0]; default: 0; 307 * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 308 */ 309 #define GPIO_PROCPU_NMI_INT 0xFFFFFFFFU 310 #define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) 311 #define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFFU 312 #define GPIO_PROCPU_NMI_INT_S 0 313 314 /** GPIO_CPUSDIO_INT_REG register 315 * GPIO CPUSDIO interrupt status register for GPIO0-31 316 */ 317 #define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) 318 /** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; 319 * GPIO CPUSDIO interrupt status register for GPIO0-31 320 */ 321 #define GPIO_SDIO_INT 0xFFFFFFFFU 322 #define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) 323 #define GPIO_SDIO_INT_V 0xFFFFFFFFU 324 #define GPIO_SDIO_INT_S 0 325 326 /** GPIO_PCPU_INT1_REG register 327 * GPIO PRO_CPU interrupt status register for GPIO32-34 328 */ 329 #define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) 330 /** GPIO_PROCPU_INT1 : RO; bitpos: [2:0]; default: 0; 331 * GPIO PRO_CPU interrupt status register for GPIO32-34 332 */ 333 #define GPIO_PROCPU_INT1 0x00000007U 334 #define GPIO_PROCPU_INT1_M (GPIO_PROCPU_INT1_V << GPIO_PROCPU_INT1_S) 335 #define GPIO_PROCPU_INT1_V 0x00000007U 336 #define GPIO_PROCPU_INT1_S 0 337 338 /** GPIO_PCPU_NMI_INT1_REG register 339 * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 340 */ 341 #define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6c) 342 /** GPIO_PROCPU_NMI_INT1 : RO; bitpos: [2:0]; default: 0; 343 * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 344 */ 345 #define GPIO_PROCPU_NMI_INT1 0x00000007U 346 #define GPIO_PROCPU_NMI_INT1_M (GPIO_PROCPU_NMI_INT1_V << GPIO_PROCPU_NMI_INT1_S) 347 #define GPIO_PROCPU_NMI_INT1_V 0x00000007U 348 #define GPIO_PROCPU_NMI_INT1_S 0 349 350 /** GPIO_CPUSDIO_INT1_REG register 351 * GPIO CPUSDIO interrupt status register for GPIO32-34 352 */ 353 #define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) 354 /** GPIO_SDIO_INT1 : RO; bitpos: [2:0]; default: 0; 355 * GPIO CPUSDIO interrupt status register for GPIO32-34 356 */ 357 #define GPIO_SDIO_INT1 0x00000007U 358 #define GPIO_SDIO_INT1_M (GPIO_SDIO_INT1_V << GPIO_SDIO_INT1_S) 359 #define GPIO_SDIO_INT1_V 0x00000007U 360 #define GPIO_SDIO_INT1_S 0 361 362 /** GPIO_PIN0_REG register 363 * GPIO pin configuration register 364 */ 365 #define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) 366 /** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 367 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 368 * posedge. 369 */ 370 #define GPIO_PIN0_SYNC2_BYPASS 0x00000003U 371 #define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) 372 #define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U 373 #define GPIO_PIN0_SYNC2_BYPASS_S 0 374 /** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 375 * set this bit to select pad driver. 1:open-drain. 0:normal. 376 */ 377 #define GPIO_PIN0_PAD_DRIVER (BIT(2)) 378 #define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) 379 #define GPIO_PIN0_PAD_DRIVER_V 0x00000001U 380 #define GPIO_PIN0_PAD_DRIVER_S 2 381 /** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 382 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 383 * posedge. 384 */ 385 #define GPIO_PIN0_SYNC1_BYPASS 0x00000003U 386 #define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) 387 #define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U 388 #define GPIO_PIN0_SYNC1_BYPASS_S 3 389 /** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 390 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 391 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 392 * at high level 393 */ 394 #define GPIO_PIN0_INT_TYPE 0x00000007U 395 #define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) 396 #define GPIO_PIN0_INT_TYPE_V 0x00000007U 397 #define GPIO_PIN0_INT_TYPE_S 7 398 /** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 399 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 400 */ 401 #define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) 402 #define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) 403 #define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U 404 #define GPIO_PIN0_WAKEUP_ENABLE_S 10 405 /** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; 406 * reserved 407 */ 408 #define GPIO_PIN0_CONFIG 0x00000003U 409 #define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) 410 #define GPIO_PIN0_CONFIG_V 0x00000003U 411 #define GPIO_PIN0_CONFIG_S 11 412 /** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; 413 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 414 * interrupt. 415 */ 416 #define GPIO_PIN0_INT_ENA 0x0000001FU 417 #define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) 418 #define GPIO_PIN0_INT_ENA_V 0x0000001FU 419 #define GPIO_PIN0_INT_ENA_S 13 420 421 /** GPIO_PIN1_REG register 422 * GPIO pin configuration register 423 */ 424 #define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) 425 /** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 426 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 427 * posedge. 428 */ 429 #define GPIO_PIN1_SYNC2_BYPASS 0x00000003U 430 #define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) 431 #define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U 432 #define GPIO_PIN1_SYNC2_BYPASS_S 0 433 /** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 434 * set this bit to select pad driver. 1:open-drain. 0:normal. 435 */ 436 #define GPIO_PIN1_PAD_DRIVER (BIT(2)) 437 #define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) 438 #define GPIO_PIN1_PAD_DRIVER_V 0x00000001U 439 #define GPIO_PIN1_PAD_DRIVER_S 2 440 /** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 441 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 442 * posedge. 443 */ 444 #define GPIO_PIN1_SYNC1_BYPASS 0x00000003U 445 #define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) 446 #define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U 447 #define GPIO_PIN1_SYNC1_BYPASS_S 3 448 /** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 449 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 450 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 451 * at high level 452 */ 453 #define GPIO_PIN1_INT_TYPE 0x00000007U 454 #define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) 455 #define GPIO_PIN1_INT_TYPE_V 0x00000007U 456 #define GPIO_PIN1_INT_TYPE_S 7 457 /** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 458 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 459 */ 460 #define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) 461 #define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) 462 #define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U 463 #define GPIO_PIN1_WAKEUP_ENABLE_S 10 464 /** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; 465 * reserved 466 */ 467 #define GPIO_PIN1_CONFIG 0x00000003U 468 #define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) 469 #define GPIO_PIN1_CONFIG_V 0x00000003U 470 #define GPIO_PIN1_CONFIG_S 11 471 /** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; 472 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 473 * interrupt. 474 */ 475 #define GPIO_PIN1_INT_ENA 0x0000001FU 476 #define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) 477 #define GPIO_PIN1_INT_ENA_V 0x0000001FU 478 #define GPIO_PIN1_INT_ENA_S 13 479 480 /** GPIO_PIN2_REG register 481 * GPIO pin configuration register 482 */ 483 #define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) 484 /** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 485 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 486 * posedge. 487 */ 488 #define GPIO_PIN2_SYNC2_BYPASS 0x00000003U 489 #define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) 490 #define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U 491 #define GPIO_PIN2_SYNC2_BYPASS_S 0 492 /** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 493 * set this bit to select pad driver. 1:open-drain. 0:normal. 494 */ 495 #define GPIO_PIN2_PAD_DRIVER (BIT(2)) 496 #define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) 497 #define GPIO_PIN2_PAD_DRIVER_V 0x00000001U 498 #define GPIO_PIN2_PAD_DRIVER_S 2 499 /** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 500 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 501 * posedge. 502 */ 503 #define GPIO_PIN2_SYNC1_BYPASS 0x00000003U 504 #define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) 505 #define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U 506 #define GPIO_PIN2_SYNC1_BYPASS_S 3 507 /** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 508 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 509 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 510 * at high level 511 */ 512 #define GPIO_PIN2_INT_TYPE 0x00000007U 513 #define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) 514 #define GPIO_PIN2_INT_TYPE_V 0x00000007U 515 #define GPIO_PIN2_INT_TYPE_S 7 516 /** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 517 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 518 */ 519 #define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) 520 #define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) 521 #define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U 522 #define GPIO_PIN2_WAKEUP_ENABLE_S 10 523 /** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; 524 * reserved 525 */ 526 #define GPIO_PIN2_CONFIG 0x00000003U 527 #define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) 528 #define GPIO_PIN2_CONFIG_V 0x00000003U 529 #define GPIO_PIN2_CONFIG_S 11 530 /** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; 531 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 532 * interrupt. 533 */ 534 #define GPIO_PIN2_INT_ENA 0x0000001FU 535 #define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) 536 #define GPIO_PIN2_INT_ENA_V 0x0000001FU 537 #define GPIO_PIN2_INT_ENA_S 13 538 539 /** GPIO_PIN3_REG register 540 * GPIO pin configuration register 541 */ 542 #define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) 543 /** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 544 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 545 * posedge. 546 */ 547 #define GPIO_PIN3_SYNC2_BYPASS 0x00000003U 548 #define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) 549 #define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U 550 #define GPIO_PIN3_SYNC2_BYPASS_S 0 551 /** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 552 * set this bit to select pad driver. 1:open-drain. 0:normal. 553 */ 554 #define GPIO_PIN3_PAD_DRIVER (BIT(2)) 555 #define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) 556 #define GPIO_PIN3_PAD_DRIVER_V 0x00000001U 557 #define GPIO_PIN3_PAD_DRIVER_S 2 558 /** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 559 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 560 * posedge. 561 */ 562 #define GPIO_PIN3_SYNC1_BYPASS 0x00000003U 563 #define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) 564 #define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U 565 #define GPIO_PIN3_SYNC1_BYPASS_S 3 566 /** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 567 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 568 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 569 * at high level 570 */ 571 #define GPIO_PIN3_INT_TYPE 0x00000007U 572 #define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) 573 #define GPIO_PIN3_INT_TYPE_V 0x00000007U 574 #define GPIO_PIN3_INT_TYPE_S 7 575 /** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 576 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 577 */ 578 #define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) 579 #define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) 580 #define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U 581 #define GPIO_PIN3_WAKEUP_ENABLE_S 10 582 /** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; 583 * reserved 584 */ 585 #define GPIO_PIN3_CONFIG 0x00000003U 586 #define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) 587 #define GPIO_PIN3_CONFIG_V 0x00000003U 588 #define GPIO_PIN3_CONFIG_S 11 589 /** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; 590 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 591 * interrupt. 592 */ 593 #define GPIO_PIN3_INT_ENA 0x0000001FU 594 #define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) 595 #define GPIO_PIN3_INT_ENA_V 0x0000001FU 596 #define GPIO_PIN3_INT_ENA_S 13 597 598 /** GPIO_PIN4_REG register 599 * GPIO pin configuration register 600 */ 601 #define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) 602 /** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 603 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 604 * posedge. 605 */ 606 #define GPIO_PIN4_SYNC2_BYPASS 0x00000003U 607 #define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) 608 #define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U 609 #define GPIO_PIN4_SYNC2_BYPASS_S 0 610 /** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 611 * set this bit to select pad driver. 1:open-drain. 0:normal. 612 */ 613 #define GPIO_PIN4_PAD_DRIVER (BIT(2)) 614 #define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) 615 #define GPIO_PIN4_PAD_DRIVER_V 0x00000001U 616 #define GPIO_PIN4_PAD_DRIVER_S 2 617 /** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 618 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 619 * posedge. 620 */ 621 #define GPIO_PIN4_SYNC1_BYPASS 0x00000003U 622 #define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) 623 #define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U 624 #define GPIO_PIN4_SYNC1_BYPASS_S 3 625 /** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 626 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 627 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 628 * at high level 629 */ 630 #define GPIO_PIN4_INT_TYPE 0x00000007U 631 #define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) 632 #define GPIO_PIN4_INT_TYPE_V 0x00000007U 633 #define GPIO_PIN4_INT_TYPE_S 7 634 /** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 635 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 636 */ 637 #define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) 638 #define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) 639 #define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U 640 #define GPIO_PIN4_WAKEUP_ENABLE_S 10 641 /** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; 642 * reserved 643 */ 644 #define GPIO_PIN4_CONFIG 0x00000003U 645 #define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) 646 #define GPIO_PIN4_CONFIG_V 0x00000003U 647 #define GPIO_PIN4_CONFIG_S 11 648 /** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; 649 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 650 * interrupt. 651 */ 652 #define GPIO_PIN4_INT_ENA 0x0000001FU 653 #define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) 654 #define GPIO_PIN4_INT_ENA_V 0x0000001FU 655 #define GPIO_PIN4_INT_ENA_S 13 656 657 /** GPIO_PIN5_REG register 658 * GPIO pin configuration register 659 */ 660 #define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) 661 /** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 662 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 663 * posedge. 664 */ 665 #define GPIO_PIN5_SYNC2_BYPASS 0x00000003U 666 #define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) 667 #define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U 668 #define GPIO_PIN5_SYNC2_BYPASS_S 0 669 /** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 670 * set this bit to select pad driver. 1:open-drain. 0:normal. 671 */ 672 #define GPIO_PIN5_PAD_DRIVER (BIT(2)) 673 #define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) 674 #define GPIO_PIN5_PAD_DRIVER_V 0x00000001U 675 #define GPIO_PIN5_PAD_DRIVER_S 2 676 /** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 677 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 678 * posedge. 679 */ 680 #define GPIO_PIN5_SYNC1_BYPASS 0x00000003U 681 #define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) 682 #define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U 683 #define GPIO_PIN5_SYNC1_BYPASS_S 3 684 /** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 685 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 686 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 687 * at high level 688 */ 689 #define GPIO_PIN5_INT_TYPE 0x00000007U 690 #define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) 691 #define GPIO_PIN5_INT_TYPE_V 0x00000007U 692 #define GPIO_PIN5_INT_TYPE_S 7 693 /** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 694 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 695 */ 696 #define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) 697 #define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) 698 #define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U 699 #define GPIO_PIN5_WAKEUP_ENABLE_S 10 700 /** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; 701 * reserved 702 */ 703 #define GPIO_PIN5_CONFIG 0x00000003U 704 #define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) 705 #define GPIO_PIN5_CONFIG_V 0x00000003U 706 #define GPIO_PIN5_CONFIG_S 11 707 /** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; 708 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 709 * interrupt. 710 */ 711 #define GPIO_PIN5_INT_ENA 0x0000001FU 712 #define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) 713 #define GPIO_PIN5_INT_ENA_V 0x0000001FU 714 #define GPIO_PIN5_INT_ENA_S 13 715 716 /** GPIO_PIN6_REG register 717 * GPIO pin configuration register 718 */ 719 #define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) 720 /** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 721 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 722 * posedge. 723 */ 724 #define GPIO_PIN6_SYNC2_BYPASS 0x00000003U 725 #define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) 726 #define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U 727 #define GPIO_PIN6_SYNC2_BYPASS_S 0 728 /** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 729 * set this bit to select pad driver. 1:open-drain. 0:normal. 730 */ 731 #define GPIO_PIN6_PAD_DRIVER (BIT(2)) 732 #define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) 733 #define GPIO_PIN6_PAD_DRIVER_V 0x00000001U 734 #define GPIO_PIN6_PAD_DRIVER_S 2 735 /** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 736 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 737 * posedge. 738 */ 739 #define GPIO_PIN6_SYNC1_BYPASS 0x00000003U 740 #define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) 741 #define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U 742 #define GPIO_PIN6_SYNC1_BYPASS_S 3 743 /** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 744 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 745 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 746 * at high level 747 */ 748 #define GPIO_PIN6_INT_TYPE 0x00000007U 749 #define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) 750 #define GPIO_PIN6_INT_TYPE_V 0x00000007U 751 #define GPIO_PIN6_INT_TYPE_S 7 752 /** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 753 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 754 */ 755 #define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) 756 #define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) 757 #define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U 758 #define GPIO_PIN6_WAKEUP_ENABLE_S 10 759 /** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; 760 * reserved 761 */ 762 #define GPIO_PIN6_CONFIG 0x00000003U 763 #define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) 764 #define GPIO_PIN6_CONFIG_V 0x00000003U 765 #define GPIO_PIN6_CONFIG_S 11 766 /** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; 767 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 768 * interrupt. 769 */ 770 #define GPIO_PIN6_INT_ENA 0x0000001FU 771 #define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) 772 #define GPIO_PIN6_INT_ENA_V 0x0000001FU 773 #define GPIO_PIN6_INT_ENA_S 13 774 775 /** GPIO_PIN7_REG register 776 * GPIO pin configuration register 777 */ 778 #define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) 779 /** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 780 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 781 * posedge. 782 */ 783 #define GPIO_PIN7_SYNC2_BYPASS 0x00000003U 784 #define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) 785 #define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U 786 #define GPIO_PIN7_SYNC2_BYPASS_S 0 787 /** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 788 * set this bit to select pad driver. 1:open-drain. 0:normal. 789 */ 790 #define GPIO_PIN7_PAD_DRIVER (BIT(2)) 791 #define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) 792 #define GPIO_PIN7_PAD_DRIVER_V 0x00000001U 793 #define GPIO_PIN7_PAD_DRIVER_S 2 794 /** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 795 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 796 * posedge. 797 */ 798 #define GPIO_PIN7_SYNC1_BYPASS 0x00000003U 799 #define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) 800 #define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U 801 #define GPIO_PIN7_SYNC1_BYPASS_S 3 802 /** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 803 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 804 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 805 * at high level 806 */ 807 #define GPIO_PIN7_INT_TYPE 0x00000007U 808 #define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) 809 #define GPIO_PIN7_INT_TYPE_V 0x00000007U 810 #define GPIO_PIN7_INT_TYPE_S 7 811 /** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 812 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 813 */ 814 #define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) 815 #define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) 816 #define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U 817 #define GPIO_PIN7_WAKEUP_ENABLE_S 10 818 /** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; 819 * reserved 820 */ 821 #define GPIO_PIN7_CONFIG 0x00000003U 822 #define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) 823 #define GPIO_PIN7_CONFIG_V 0x00000003U 824 #define GPIO_PIN7_CONFIG_S 11 825 /** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; 826 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 827 * interrupt. 828 */ 829 #define GPIO_PIN7_INT_ENA 0x0000001FU 830 #define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) 831 #define GPIO_PIN7_INT_ENA_V 0x0000001FU 832 #define GPIO_PIN7_INT_ENA_S 13 833 834 /** GPIO_PIN8_REG register 835 * GPIO pin configuration register 836 */ 837 #define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) 838 /** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 839 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 840 * posedge. 841 */ 842 #define GPIO_PIN8_SYNC2_BYPASS 0x00000003U 843 #define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) 844 #define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U 845 #define GPIO_PIN8_SYNC2_BYPASS_S 0 846 /** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 847 * set this bit to select pad driver. 1:open-drain. 0:normal. 848 */ 849 #define GPIO_PIN8_PAD_DRIVER (BIT(2)) 850 #define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) 851 #define GPIO_PIN8_PAD_DRIVER_V 0x00000001U 852 #define GPIO_PIN8_PAD_DRIVER_S 2 853 /** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 854 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 855 * posedge. 856 */ 857 #define GPIO_PIN8_SYNC1_BYPASS 0x00000003U 858 #define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) 859 #define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U 860 #define GPIO_PIN8_SYNC1_BYPASS_S 3 861 /** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 862 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 863 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 864 * at high level 865 */ 866 #define GPIO_PIN8_INT_TYPE 0x00000007U 867 #define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) 868 #define GPIO_PIN8_INT_TYPE_V 0x00000007U 869 #define GPIO_PIN8_INT_TYPE_S 7 870 /** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 871 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 872 */ 873 #define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) 874 #define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) 875 #define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U 876 #define GPIO_PIN8_WAKEUP_ENABLE_S 10 877 /** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; 878 * reserved 879 */ 880 #define GPIO_PIN8_CONFIG 0x00000003U 881 #define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) 882 #define GPIO_PIN8_CONFIG_V 0x00000003U 883 #define GPIO_PIN8_CONFIG_S 11 884 /** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; 885 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 886 * interrupt. 887 */ 888 #define GPIO_PIN8_INT_ENA 0x0000001FU 889 #define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) 890 #define GPIO_PIN8_INT_ENA_V 0x0000001FU 891 #define GPIO_PIN8_INT_ENA_S 13 892 893 /** GPIO_PIN9_REG register 894 * GPIO pin configuration register 895 */ 896 #define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) 897 /** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 898 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 899 * posedge. 900 */ 901 #define GPIO_PIN9_SYNC2_BYPASS 0x00000003U 902 #define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) 903 #define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U 904 #define GPIO_PIN9_SYNC2_BYPASS_S 0 905 /** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 906 * set this bit to select pad driver. 1:open-drain. 0:normal. 907 */ 908 #define GPIO_PIN9_PAD_DRIVER (BIT(2)) 909 #define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) 910 #define GPIO_PIN9_PAD_DRIVER_V 0x00000001U 911 #define GPIO_PIN9_PAD_DRIVER_S 2 912 /** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 913 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 914 * posedge. 915 */ 916 #define GPIO_PIN9_SYNC1_BYPASS 0x00000003U 917 #define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) 918 #define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U 919 #define GPIO_PIN9_SYNC1_BYPASS_S 3 920 /** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 921 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 922 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 923 * at high level 924 */ 925 #define GPIO_PIN9_INT_TYPE 0x00000007U 926 #define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) 927 #define GPIO_PIN9_INT_TYPE_V 0x00000007U 928 #define GPIO_PIN9_INT_TYPE_S 7 929 /** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 930 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 931 */ 932 #define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) 933 #define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) 934 #define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U 935 #define GPIO_PIN9_WAKEUP_ENABLE_S 10 936 /** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; 937 * reserved 938 */ 939 #define GPIO_PIN9_CONFIG 0x00000003U 940 #define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) 941 #define GPIO_PIN9_CONFIG_V 0x00000003U 942 #define GPIO_PIN9_CONFIG_S 11 943 /** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; 944 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 945 * interrupt. 946 */ 947 #define GPIO_PIN9_INT_ENA 0x0000001FU 948 #define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) 949 #define GPIO_PIN9_INT_ENA_V 0x0000001FU 950 #define GPIO_PIN9_INT_ENA_S 13 951 952 /** GPIO_PIN10_REG register 953 * GPIO pin configuration register 954 */ 955 #define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) 956 /** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 957 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 958 * posedge. 959 */ 960 #define GPIO_PIN10_SYNC2_BYPASS 0x00000003U 961 #define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) 962 #define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U 963 #define GPIO_PIN10_SYNC2_BYPASS_S 0 964 /** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 965 * set this bit to select pad driver. 1:open-drain. 0:normal. 966 */ 967 #define GPIO_PIN10_PAD_DRIVER (BIT(2)) 968 #define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) 969 #define GPIO_PIN10_PAD_DRIVER_V 0x00000001U 970 #define GPIO_PIN10_PAD_DRIVER_S 2 971 /** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 972 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 973 * posedge. 974 */ 975 #define GPIO_PIN10_SYNC1_BYPASS 0x00000003U 976 #define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) 977 #define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U 978 #define GPIO_PIN10_SYNC1_BYPASS_S 3 979 /** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 980 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 981 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 982 * at high level 983 */ 984 #define GPIO_PIN10_INT_TYPE 0x00000007U 985 #define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) 986 #define GPIO_PIN10_INT_TYPE_V 0x00000007U 987 #define GPIO_PIN10_INT_TYPE_S 7 988 /** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 989 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 990 */ 991 #define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) 992 #define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) 993 #define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U 994 #define GPIO_PIN10_WAKEUP_ENABLE_S 10 995 /** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; 996 * reserved 997 */ 998 #define GPIO_PIN10_CONFIG 0x00000003U 999 #define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) 1000 #define GPIO_PIN10_CONFIG_V 0x00000003U 1001 #define GPIO_PIN10_CONFIG_S 11 1002 /** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1003 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1004 * interrupt. 1005 */ 1006 #define GPIO_PIN10_INT_ENA 0x0000001FU 1007 #define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) 1008 #define GPIO_PIN10_INT_ENA_V 0x0000001FU 1009 #define GPIO_PIN10_INT_ENA_S 13 1010 1011 /** GPIO_PIN11_REG register 1012 * GPIO pin configuration register 1013 */ 1014 #define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) 1015 /** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1016 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1017 * posedge. 1018 */ 1019 #define GPIO_PIN11_SYNC2_BYPASS 0x00000003U 1020 #define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) 1021 #define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U 1022 #define GPIO_PIN11_SYNC2_BYPASS_S 0 1023 /** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1024 * set this bit to select pad driver. 1:open-drain. 0:normal. 1025 */ 1026 #define GPIO_PIN11_PAD_DRIVER (BIT(2)) 1027 #define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) 1028 #define GPIO_PIN11_PAD_DRIVER_V 0x00000001U 1029 #define GPIO_PIN11_PAD_DRIVER_S 2 1030 /** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1031 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1032 * posedge. 1033 */ 1034 #define GPIO_PIN11_SYNC1_BYPASS 0x00000003U 1035 #define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) 1036 #define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U 1037 #define GPIO_PIN11_SYNC1_BYPASS_S 3 1038 /** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1039 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1040 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1041 * at high level 1042 */ 1043 #define GPIO_PIN11_INT_TYPE 0x00000007U 1044 #define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) 1045 #define GPIO_PIN11_INT_TYPE_V 0x00000007U 1046 #define GPIO_PIN11_INT_TYPE_S 7 1047 /** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1048 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1049 */ 1050 #define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) 1051 #define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) 1052 #define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U 1053 #define GPIO_PIN11_WAKEUP_ENABLE_S 10 1054 /** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; 1055 * reserved 1056 */ 1057 #define GPIO_PIN11_CONFIG 0x00000003U 1058 #define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) 1059 #define GPIO_PIN11_CONFIG_V 0x00000003U 1060 #define GPIO_PIN11_CONFIG_S 11 1061 /** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1062 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1063 * interrupt. 1064 */ 1065 #define GPIO_PIN11_INT_ENA 0x0000001FU 1066 #define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) 1067 #define GPIO_PIN11_INT_ENA_V 0x0000001FU 1068 #define GPIO_PIN11_INT_ENA_S 13 1069 1070 /** GPIO_PIN12_REG register 1071 * GPIO pin configuration register 1072 */ 1073 #define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) 1074 /** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1075 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1076 * posedge. 1077 */ 1078 #define GPIO_PIN12_SYNC2_BYPASS 0x00000003U 1079 #define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) 1080 #define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U 1081 #define GPIO_PIN12_SYNC2_BYPASS_S 0 1082 /** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1083 * set this bit to select pad driver. 1:open-drain. 0:normal. 1084 */ 1085 #define GPIO_PIN12_PAD_DRIVER (BIT(2)) 1086 #define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) 1087 #define GPIO_PIN12_PAD_DRIVER_V 0x00000001U 1088 #define GPIO_PIN12_PAD_DRIVER_S 2 1089 /** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1090 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1091 * posedge. 1092 */ 1093 #define GPIO_PIN12_SYNC1_BYPASS 0x00000003U 1094 #define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) 1095 #define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U 1096 #define GPIO_PIN12_SYNC1_BYPASS_S 3 1097 /** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1098 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1099 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1100 * at high level 1101 */ 1102 #define GPIO_PIN12_INT_TYPE 0x00000007U 1103 #define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) 1104 #define GPIO_PIN12_INT_TYPE_V 0x00000007U 1105 #define GPIO_PIN12_INT_TYPE_S 7 1106 /** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1107 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1108 */ 1109 #define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) 1110 #define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) 1111 #define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U 1112 #define GPIO_PIN12_WAKEUP_ENABLE_S 10 1113 /** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; 1114 * reserved 1115 */ 1116 #define GPIO_PIN12_CONFIG 0x00000003U 1117 #define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) 1118 #define GPIO_PIN12_CONFIG_V 0x00000003U 1119 #define GPIO_PIN12_CONFIG_S 11 1120 /** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1121 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1122 * interrupt. 1123 */ 1124 #define GPIO_PIN12_INT_ENA 0x0000001FU 1125 #define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) 1126 #define GPIO_PIN12_INT_ENA_V 0x0000001FU 1127 #define GPIO_PIN12_INT_ENA_S 13 1128 1129 /** GPIO_PIN13_REG register 1130 * GPIO pin configuration register 1131 */ 1132 #define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) 1133 /** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1134 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1135 * posedge. 1136 */ 1137 #define GPIO_PIN13_SYNC2_BYPASS 0x00000003U 1138 #define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) 1139 #define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U 1140 #define GPIO_PIN13_SYNC2_BYPASS_S 0 1141 /** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1142 * set this bit to select pad driver. 1:open-drain. 0:normal. 1143 */ 1144 #define GPIO_PIN13_PAD_DRIVER (BIT(2)) 1145 #define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) 1146 #define GPIO_PIN13_PAD_DRIVER_V 0x00000001U 1147 #define GPIO_PIN13_PAD_DRIVER_S 2 1148 /** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1149 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1150 * posedge. 1151 */ 1152 #define GPIO_PIN13_SYNC1_BYPASS 0x00000003U 1153 #define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) 1154 #define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U 1155 #define GPIO_PIN13_SYNC1_BYPASS_S 3 1156 /** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1157 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1158 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1159 * at high level 1160 */ 1161 #define GPIO_PIN13_INT_TYPE 0x00000007U 1162 #define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) 1163 #define GPIO_PIN13_INT_TYPE_V 0x00000007U 1164 #define GPIO_PIN13_INT_TYPE_S 7 1165 /** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1166 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1167 */ 1168 #define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) 1169 #define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) 1170 #define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U 1171 #define GPIO_PIN13_WAKEUP_ENABLE_S 10 1172 /** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; 1173 * reserved 1174 */ 1175 #define GPIO_PIN13_CONFIG 0x00000003U 1176 #define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) 1177 #define GPIO_PIN13_CONFIG_V 0x00000003U 1178 #define GPIO_PIN13_CONFIG_S 11 1179 /** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1180 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1181 * interrupt. 1182 */ 1183 #define GPIO_PIN13_INT_ENA 0x0000001FU 1184 #define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) 1185 #define GPIO_PIN13_INT_ENA_V 0x0000001FU 1186 #define GPIO_PIN13_INT_ENA_S 13 1187 1188 /** GPIO_PIN14_REG register 1189 * GPIO pin configuration register 1190 */ 1191 #define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) 1192 /** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1193 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1194 * posedge. 1195 */ 1196 #define GPIO_PIN14_SYNC2_BYPASS 0x00000003U 1197 #define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) 1198 #define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U 1199 #define GPIO_PIN14_SYNC2_BYPASS_S 0 1200 /** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1201 * set this bit to select pad driver. 1:open-drain. 0:normal. 1202 */ 1203 #define GPIO_PIN14_PAD_DRIVER (BIT(2)) 1204 #define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) 1205 #define GPIO_PIN14_PAD_DRIVER_V 0x00000001U 1206 #define GPIO_PIN14_PAD_DRIVER_S 2 1207 /** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1208 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1209 * posedge. 1210 */ 1211 #define GPIO_PIN14_SYNC1_BYPASS 0x00000003U 1212 #define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) 1213 #define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U 1214 #define GPIO_PIN14_SYNC1_BYPASS_S 3 1215 /** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1216 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1217 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1218 * at high level 1219 */ 1220 #define GPIO_PIN14_INT_TYPE 0x00000007U 1221 #define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) 1222 #define GPIO_PIN14_INT_TYPE_V 0x00000007U 1223 #define GPIO_PIN14_INT_TYPE_S 7 1224 /** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1225 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1226 */ 1227 #define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) 1228 #define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) 1229 #define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U 1230 #define GPIO_PIN14_WAKEUP_ENABLE_S 10 1231 /** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; 1232 * reserved 1233 */ 1234 #define GPIO_PIN14_CONFIG 0x00000003U 1235 #define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) 1236 #define GPIO_PIN14_CONFIG_V 0x00000003U 1237 #define GPIO_PIN14_CONFIG_S 11 1238 /** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1239 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1240 * interrupt. 1241 */ 1242 #define GPIO_PIN14_INT_ENA 0x0000001FU 1243 #define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) 1244 #define GPIO_PIN14_INT_ENA_V 0x0000001FU 1245 #define GPIO_PIN14_INT_ENA_S 13 1246 1247 /** GPIO_PIN15_REG register 1248 * GPIO pin configuration register 1249 */ 1250 #define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) 1251 /** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1252 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1253 * posedge. 1254 */ 1255 #define GPIO_PIN15_SYNC2_BYPASS 0x00000003U 1256 #define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) 1257 #define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U 1258 #define GPIO_PIN15_SYNC2_BYPASS_S 0 1259 /** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1260 * set this bit to select pad driver. 1:open-drain. 0:normal. 1261 */ 1262 #define GPIO_PIN15_PAD_DRIVER (BIT(2)) 1263 #define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) 1264 #define GPIO_PIN15_PAD_DRIVER_V 0x00000001U 1265 #define GPIO_PIN15_PAD_DRIVER_S 2 1266 /** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1267 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1268 * posedge. 1269 */ 1270 #define GPIO_PIN15_SYNC1_BYPASS 0x00000003U 1271 #define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) 1272 #define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U 1273 #define GPIO_PIN15_SYNC1_BYPASS_S 3 1274 /** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1275 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1276 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1277 * at high level 1278 */ 1279 #define GPIO_PIN15_INT_TYPE 0x00000007U 1280 #define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) 1281 #define GPIO_PIN15_INT_TYPE_V 0x00000007U 1282 #define GPIO_PIN15_INT_TYPE_S 7 1283 /** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1284 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1285 */ 1286 #define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) 1287 #define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) 1288 #define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U 1289 #define GPIO_PIN15_WAKEUP_ENABLE_S 10 1290 /** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; 1291 * reserved 1292 */ 1293 #define GPIO_PIN15_CONFIG 0x00000003U 1294 #define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) 1295 #define GPIO_PIN15_CONFIG_V 0x00000003U 1296 #define GPIO_PIN15_CONFIG_S 11 1297 /** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1298 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1299 * interrupt. 1300 */ 1301 #define GPIO_PIN15_INT_ENA 0x0000001FU 1302 #define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) 1303 #define GPIO_PIN15_INT_ENA_V 0x0000001FU 1304 #define GPIO_PIN15_INT_ENA_S 13 1305 1306 /** GPIO_PIN16_REG register 1307 * GPIO pin configuration register 1308 */ 1309 #define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) 1310 /** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1311 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1312 * posedge. 1313 */ 1314 #define GPIO_PIN16_SYNC2_BYPASS 0x00000003U 1315 #define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) 1316 #define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U 1317 #define GPIO_PIN16_SYNC2_BYPASS_S 0 1318 /** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1319 * set this bit to select pad driver. 1:open-drain. 0:normal. 1320 */ 1321 #define GPIO_PIN16_PAD_DRIVER (BIT(2)) 1322 #define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) 1323 #define GPIO_PIN16_PAD_DRIVER_V 0x00000001U 1324 #define GPIO_PIN16_PAD_DRIVER_S 2 1325 /** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1326 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1327 * posedge. 1328 */ 1329 #define GPIO_PIN16_SYNC1_BYPASS 0x00000003U 1330 #define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) 1331 #define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U 1332 #define GPIO_PIN16_SYNC1_BYPASS_S 3 1333 /** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1334 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1335 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1336 * at high level 1337 */ 1338 #define GPIO_PIN16_INT_TYPE 0x00000007U 1339 #define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) 1340 #define GPIO_PIN16_INT_TYPE_V 0x00000007U 1341 #define GPIO_PIN16_INT_TYPE_S 7 1342 /** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1343 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1344 */ 1345 #define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) 1346 #define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) 1347 #define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U 1348 #define GPIO_PIN16_WAKEUP_ENABLE_S 10 1349 /** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; 1350 * reserved 1351 */ 1352 #define GPIO_PIN16_CONFIG 0x00000003U 1353 #define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) 1354 #define GPIO_PIN16_CONFIG_V 0x00000003U 1355 #define GPIO_PIN16_CONFIG_S 11 1356 /** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1357 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1358 * interrupt. 1359 */ 1360 #define GPIO_PIN16_INT_ENA 0x0000001FU 1361 #define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) 1362 #define GPIO_PIN16_INT_ENA_V 0x0000001FU 1363 #define GPIO_PIN16_INT_ENA_S 13 1364 1365 /** GPIO_PIN17_REG register 1366 * GPIO pin configuration register 1367 */ 1368 #define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) 1369 /** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1370 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1371 * posedge. 1372 */ 1373 #define GPIO_PIN17_SYNC2_BYPASS 0x00000003U 1374 #define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) 1375 #define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U 1376 #define GPIO_PIN17_SYNC2_BYPASS_S 0 1377 /** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1378 * set this bit to select pad driver. 1:open-drain. 0:normal. 1379 */ 1380 #define GPIO_PIN17_PAD_DRIVER (BIT(2)) 1381 #define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) 1382 #define GPIO_PIN17_PAD_DRIVER_V 0x00000001U 1383 #define GPIO_PIN17_PAD_DRIVER_S 2 1384 /** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1385 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1386 * posedge. 1387 */ 1388 #define GPIO_PIN17_SYNC1_BYPASS 0x00000003U 1389 #define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) 1390 #define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U 1391 #define GPIO_PIN17_SYNC1_BYPASS_S 3 1392 /** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1393 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1394 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1395 * at high level 1396 */ 1397 #define GPIO_PIN17_INT_TYPE 0x00000007U 1398 #define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) 1399 #define GPIO_PIN17_INT_TYPE_V 0x00000007U 1400 #define GPIO_PIN17_INT_TYPE_S 7 1401 /** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1402 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1403 */ 1404 #define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) 1405 #define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) 1406 #define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U 1407 #define GPIO_PIN17_WAKEUP_ENABLE_S 10 1408 /** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; 1409 * reserved 1410 */ 1411 #define GPIO_PIN17_CONFIG 0x00000003U 1412 #define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) 1413 #define GPIO_PIN17_CONFIG_V 0x00000003U 1414 #define GPIO_PIN17_CONFIG_S 11 1415 /** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1416 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1417 * interrupt. 1418 */ 1419 #define GPIO_PIN17_INT_ENA 0x0000001FU 1420 #define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) 1421 #define GPIO_PIN17_INT_ENA_V 0x0000001FU 1422 #define GPIO_PIN17_INT_ENA_S 13 1423 1424 /** GPIO_PIN18_REG register 1425 * GPIO pin configuration register 1426 */ 1427 #define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) 1428 /** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1429 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1430 * posedge. 1431 */ 1432 #define GPIO_PIN18_SYNC2_BYPASS 0x00000003U 1433 #define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) 1434 #define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U 1435 #define GPIO_PIN18_SYNC2_BYPASS_S 0 1436 /** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1437 * set this bit to select pad driver. 1:open-drain. 0:normal. 1438 */ 1439 #define GPIO_PIN18_PAD_DRIVER (BIT(2)) 1440 #define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) 1441 #define GPIO_PIN18_PAD_DRIVER_V 0x00000001U 1442 #define GPIO_PIN18_PAD_DRIVER_S 2 1443 /** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1444 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1445 * posedge. 1446 */ 1447 #define GPIO_PIN18_SYNC1_BYPASS 0x00000003U 1448 #define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) 1449 #define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U 1450 #define GPIO_PIN18_SYNC1_BYPASS_S 3 1451 /** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1452 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1453 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1454 * at high level 1455 */ 1456 #define GPIO_PIN18_INT_TYPE 0x00000007U 1457 #define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) 1458 #define GPIO_PIN18_INT_TYPE_V 0x00000007U 1459 #define GPIO_PIN18_INT_TYPE_S 7 1460 /** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1461 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1462 */ 1463 #define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) 1464 #define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) 1465 #define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U 1466 #define GPIO_PIN18_WAKEUP_ENABLE_S 10 1467 /** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; 1468 * reserved 1469 */ 1470 #define GPIO_PIN18_CONFIG 0x00000003U 1471 #define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) 1472 #define GPIO_PIN18_CONFIG_V 0x00000003U 1473 #define GPIO_PIN18_CONFIG_S 11 1474 /** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1475 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1476 * interrupt. 1477 */ 1478 #define GPIO_PIN18_INT_ENA 0x0000001FU 1479 #define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) 1480 #define GPIO_PIN18_INT_ENA_V 0x0000001FU 1481 #define GPIO_PIN18_INT_ENA_S 13 1482 1483 /** GPIO_PIN19_REG register 1484 * GPIO pin configuration register 1485 */ 1486 #define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) 1487 /** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1488 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1489 * posedge. 1490 */ 1491 #define GPIO_PIN19_SYNC2_BYPASS 0x00000003U 1492 #define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) 1493 #define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U 1494 #define GPIO_PIN19_SYNC2_BYPASS_S 0 1495 /** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1496 * set this bit to select pad driver. 1:open-drain. 0:normal. 1497 */ 1498 #define GPIO_PIN19_PAD_DRIVER (BIT(2)) 1499 #define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) 1500 #define GPIO_PIN19_PAD_DRIVER_V 0x00000001U 1501 #define GPIO_PIN19_PAD_DRIVER_S 2 1502 /** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1503 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1504 * posedge. 1505 */ 1506 #define GPIO_PIN19_SYNC1_BYPASS 0x00000003U 1507 #define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) 1508 #define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U 1509 #define GPIO_PIN19_SYNC1_BYPASS_S 3 1510 /** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1511 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1512 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1513 * at high level 1514 */ 1515 #define GPIO_PIN19_INT_TYPE 0x00000007U 1516 #define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) 1517 #define GPIO_PIN19_INT_TYPE_V 0x00000007U 1518 #define GPIO_PIN19_INT_TYPE_S 7 1519 /** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1520 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1521 */ 1522 #define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) 1523 #define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) 1524 #define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U 1525 #define GPIO_PIN19_WAKEUP_ENABLE_S 10 1526 /** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; 1527 * reserved 1528 */ 1529 #define GPIO_PIN19_CONFIG 0x00000003U 1530 #define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) 1531 #define GPIO_PIN19_CONFIG_V 0x00000003U 1532 #define GPIO_PIN19_CONFIG_S 11 1533 /** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1534 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1535 * interrupt. 1536 */ 1537 #define GPIO_PIN19_INT_ENA 0x0000001FU 1538 #define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) 1539 #define GPIO_PIN19_INT_ENA_V 0x0000001FU 1540 #define GPIO_PIN19_INT_ENA_S 13 1541 1542 /** GPIO_PIN20_REG register 1543 * GPIO pin configuration register 1544 */ 1545 #define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) 1546 /** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1547 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1548 * posedge. 1549 */ 1550 #define GPIO_PIN20_SYNC2_BYPASS 0x00000003U 1551 #define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) 1552 #define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U 1553 #define GPIO_PIN20_SYNC2_BYPASS_S 0 1554 /** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1555 * set this bit to select pad driver. 1:open-drain. 0:normal. 1556 */ 1557 #define GPIO_PIN20_PAD_DRIVER (BIT(2)) 1558 #define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) 1559 #define GPIO_PIN20_PAD_DRIVER_V 0x00000001U 1560 #define GPIO_PIN20_PAD_DRIVER_S 2 1561 /** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1562 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1563 * posedge. 1564 */ 1565 #define GPIO_PIN20_SYNC1_BYPASS 0x00000003U 1566 #define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) 1567 #define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U 1568 #define GPIO_PIN20_SYNC1_BYPASS_S 3 1569 /** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1570 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1571 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1572 * at high level 1573 */ 1574 #define GPIO_PIN20_INT_TYPE 0x00000007U 1575 #define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) 1576 #define GPIO_PIN20_INT_TYPE_V 0x00000007U 1577 #define GPIO_PIN20_INT_TYPE_S 7 1578 /** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1579 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1580 */ 1581 #define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) 1582 #define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) 1583 #define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U 1584 #define GPIO_PIN20_WAKEUP_ENABLE_S 10 1585 /** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; 1586 * reserved 1587 */ 1588 #define GPIO_PIN20_CONFIG 0x00000003U 1589 #define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) 1590 #define GPIO_PIN20_CONFIG_V 0x00000003U 1591 #define GPIO_PIN20_CONFIG_S 11 1592 /** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1593 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1594 * interrupt. 1595 */ 1596 #define GPIO_PIN20_INT_ENA 0x0000001FU 1597 #define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) 1598 #define GPIO_PIN20_INT_ENA_V 0x0000001FU 1599 #define GPIO_PIN20_INT_ENA_S 13 1600 1601 /** GPIO_PIN21_REG register 1602 * GPIO pin configuration register 1603 */ 1604 #define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) 1605 /** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1606 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1607 * posedge. 1608 */ 1609 #define GPIO_PIN21_SYNC2_BYPASS 0x00000003U 1610 #define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) 1611 #define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U 1612 #define GPIO_PIN21_SYNC2_BYPASS_S 0 1613 /** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1614 * set this bit to select pad driver. 1:open-drain. 0:normal. 1615 */ 1616 #define GPIO_PIN21_PAD_DRIVER (BIT(2)) 1617 #define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) 1618 #define GPIO_PIN21_PAD_DRIVER_V 0x00000001U 1619 #define GPIO_PIN21_PAD_DRIVER_S 2 1620 /** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1621 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1622 * posedge. 1623 */ 1624 #define GPIO_PIN21_SYNC1_BYPASS 0x00000003U 1625 #define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) 1626 #define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U 1627 #define GPIO_PIN21_SYNC1_BYPASS_S 3 1628 /** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1629 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1630 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1631 * at high level 1632 */ 1633 #define GPIO_PIN21_INT_TYPE 0x00000007U 1634 #define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) 1635 #define GPIO_PIN21_INT_TYPE_V 0x00000007U 1636 #define GPIO_PIN21_INT_TYPE_S 7 1637 /** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1638 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1639 */ 1640 #define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) 1641 #define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) 1642 #define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U 1643 #define GPIO_PIN21_WAKEUP_ENABLE_S 10 1644 /** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; 1645 * reserved 1646 */ 1647 #define GPIO_PIN21_CONFIG 0x00000003U 1648 #define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) 1649 #define GPIO_PIN21_CONFIG_V 0x00000003U 1650 #define GPIO_PIN21_CONFIG_S 11 1651 /** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1652 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1653 * interrupt. 1654 */ 1655 #define GPIO_PIN21_INT_ENA 0x0000001FU 1656 #define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) 1657 #define GPIO_PIN21_INT_ENA_V 0x0000001FU 1658 #define GPIO_PIN21_INT_ENA_S 13 1659 1660 /** GPIO_PIN22_REG register 1661 * GPIO pin configuration register 1662 */ 1663 #define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) 1664 /** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1665 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1666 * posedge. 1667 */ 1668 #define GPIO_PIN22_SYNC2_BYPASS 0x00000003U 1669 #define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) 1670 #define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U 1671 #define GPIO_PIN22_SYNC2_BYPASS_S 0 1672 /** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1673 * set this bit to select pad driver. 1:open-drain. 0:normal. 1674 */ 1675 #define GPIO_PIN22_PAD_DRIVER (BIT(2)) 1676 #define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) 1677 #define GPIO_PIN22_PAD_DRIVER_V 0x00000001U 1678 #define GPIO_PIN22_PAD_DRIVER_S 2 1679 /** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1680 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1681 * posedge. 1682 */ 1683 #define GPIO_PIN22_SYNC1_BYPASS 0x00000003U 1684 #define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) 1685 #define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U 1686 #define GPIO_PIN22_SYNC1_BYPASS_S 3 1687 /** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1688 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1689 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1690 * at high level 1691 */ 1692 #define GPIO_PIN22_INT_TYPE 0x00000007U 1693 #define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) 1694 #define GPIO_PIN22_INT_TYPE_V 0x00000007U 1695 #define GPIO_PIN22_INT_TYPE_S 7 1696 /** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1697 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1698 */ 1699 #define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) 1700 #define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) 1701 #define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U 1702 #define GPIO_PIN22_WAKEUP_ENABLE_S 10 1703 /** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; 1704 * reserved 1705 */ 1706 #define GPIO_PIN22_CONFIG 0x00000003U 1707 #define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) 1708 #define GPIO_PIN22_CONFIG_V 0x00000003U 1709 #define GPIO_PIN22_CONFIG_S 11 1710 /** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1711 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1712 * interrupt. 1713 */ 1714 #define GPIO_PIN22_INT_ENA 0x0000001FU 1715 #define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) 1716 #define GPIO_PIN22_INT_ENA_V 0x0000001FU 1717 #define GPIO_PIN22_INT_ENA_S 13 1718 1719 /** GPIO_PIN23_REG register 1720 * GPIO pin configuration register 1721 */ 1722 #define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) 1723 /** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1724 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1725 * posedge. 1726 */ 1727 #define GPIO_PIN23_SYNC2_BYPASS 0x00000003U 1728 #define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) 1729 #define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U 1730 #define GPIO_PIN23_SYNC2_BYPASS_S 0 1731 /** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1732 * set this bit to select pad driver. 1:open-drain. 0:normal. 1733 */ 1734 #define GPIO_PIN23_PAD_DRIVER (BIT(2)) 1735 #define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) 1736 #define GPIO_PIN23_PAD_DRIVER_V 0x00000001U 1737 #define GPIO_PIN23_PAD_DRIVER_S 2 1738 /** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1739 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1740 * posedge. 1741 */ 1742 #define GPIO_PIN23_SYNC1_BYPASS 0x00000003U 1743 #define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) 1744 #define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U 1745 #define GPIO_PIN23_SYNC1_BYPASS_S 3 1746 /** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1747 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1748 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1749 * at high level 1750 */ 1751 #define GPIO_PIN23_INT_TYPE 0x00000007U 1752 #define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) 1753 #define GPIO_PIN23_INT_TYPE_V 0x00000007U 1754 #define GPIO_PIN23_INT_TYPE_S 7 1755 /** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1756 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1757 */ 1758 #define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) 1759 #define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) 1760 #define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U 1761 #define GPIO_PIN23_WAKEUP_ENABLE_S 10 1762 /** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; 1763 * reserved 1764 */ 1765 #define GPIO_PIN23_CONFIG 0x00000003U 1766 #define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) 1767 #define GPIO_PIN23_CONFIG_V 0x00000003U 1768 #define GPIO_PIN23_CONFIG_S 11 1769 /** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1770 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1771 * interrupt. 1772 */ 1773 #define GPIO_PIN23_INT_ENA 0x0000001FU 1774 #define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) 1775 #define GPIO_PIN23_INT_ENA_V 0x0000001FU 1776 #define GPIO_PIN23_INT_ENA_S 13 1777 1778 /** GPIO_PIN24_REG register 1779 * GPIO pin configuration register 1780 */ 1781 #define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) 1782 /** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1783 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1784 * posedge. 1785 */ 1786 #define GPIO_PIN24_SYNC2_BYPASS 0x00000003U 1787 #define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) 1788 #define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U 1789 #define GPIO_PIN24_SYNC2_BYPASS_S 0 1790 /** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1791 * set this bit to select pad driver. 1:open-drain. 0:normal. 1792 */ 1793 #define GPIO_PIN24_PAD_DRIVER (BIT(2)) 1794 #define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) 1795 #define GPIO_PIN24_PAD_DRIVER_V 0x00000001U 1796 #define GPIO_PIN24_PAD_DRIVER_S 2 1797 /** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1798 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1799 * posedge. 1800 */ 1801 #define GPIO_PIN24_SYNC1_BYPASS 0x00000003U 1802 #define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) 1803 #define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U 1804 #define GPIO_PIN24_SYNC1_BYPASS_S 3 1805 /** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1806 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1807 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1808 * at high level 1809 */ 1810 #define GPIO_PIN24_INT_TYPE 0x00000007U 1811 #define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) 1812 #define GPIO_PIN24_INT_TYPE_V 0x00000007U 1813 #define GPIO_PIN24_INT_TYPE_S 7 1814 /** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1815 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1816 */ 1817 #define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) 1818 #define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) 1819 #define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U 1820 #define GPIO_PIN24_WAKEUP_ENABLE_S 10 1821 /** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; 1822 * reserved 1823 */ 1824 #define GPIO_PIN24_CONFIG 0x00000003U 1825 #define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) 1826 #define GPIO_PIN24_CONFIG_V 0x00000003U 1827 #define GPIO_PIN24_CONFIG_S 11 1828 /** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1829 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1830 * interrupt. 1831 */ 1832 #define GPIO_PIN24_INT_ENA 0x0000001FU 1833 #define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) 1834 #define GPIO_PIN24_INT_ENA_V 0x0000001FU 1835 #define GPIO_PIN24_INT_ENA_S 13 1836 1837 /** GPIO_PIN25_REG register 1838 * GPIO pin configuration register 1839 */ 1840 #define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) 1841 /** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1842 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1843 * posedge. 1844 */ 1845 #define GPIO_PIN25_SYNC2_BYPASS 0x00000003U 1846 #define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) 1847 #define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U 1848 #define GPIO_PIN25_SYNC2_BYPASS_S 0 1849 /** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1850 * set this bit to select pad driver. 1:open-drain. 0:normal. 1851 */ 1852 #define GPIO_PIN25_PAD_DRIVER (BIT(2)) 1853 #define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) 1854 #define GPIO_PIN25_PAD_DRIVER_V 0x00000001U 1855 #define GPIO_PIN25_PAD_DRIVER_S 2 1856 /** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1857 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1858 * posedge. 1859 */ 1860 #define GPIO_PIN25_SYNC1_BYPASS 0x00000003U 1861 #define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) 1862 #define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U 1863 #define GPIO_PIN25_SYNC1_BYPASS_S 3 1864 /** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1865 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1866 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1867 * at high level 1868 */ 1869 #define GPIO_PIN25_INT_TYPE 0x00000007U 1870 #define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) 1871 #define GPIO_PIN25_INT_TYPE_V 0x00000007U 1872 #define GPIO_PIN25_INT_TYPE_S 7 1873 /** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1874 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1875 */ 1876 #define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) 1877 #define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) 1878 #define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U 1879 #define GPIO_PIN25_WAKEUP_ENABLE_S 10 1880 /** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; 1881 * reserved 1882 */ 1883 #define GPIO_PIN25_CONFIG 0x00000003U 1884 #define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) 1885 #define GPIO_PIN25_CONFIG_V 0x00000003U 1886 #define GPIO_PIN25_CONFIG_S 11 1887 /** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1888 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1889 * interrupt. 1890 */ 1891 #define GPIO_PIN25_INT_ENA 0x0000001FU 1892 #define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) 1893 #define GPIO_PIN25_INT_ENA_V 0x0000001FU 1894 #define GPIO_PIN25_INT_ENA_S 13 1895 1896 /** GPIO_PIN26_REG register 1897 * GPIO pin configuration register 1898 */ 1899 #define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) 1900 /** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1901 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1902 * posedge. 1903 */ 1904 #define GPIO_PIN26_SYNC2_BYPASS 0x00000003U 1905 #define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) 1906 #define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U 1907 #define GPIO_PIN26_SYNC2_BYPASS_S 0 1908 /** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1909 * set this bit to select pad driver. 1:open-drain. 0:normal. 1910 */ 1911 #define GPIO_PIN26_PAD_DRIVER (BIT(2)) 1912 #define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) 1913 #define GPIO_PIN26_PAD_DRIVER_V 0x00000001U 1914 #define GPIO_PIN26_PAD_DRIVER_S 2 1915 /** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1916 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1917 * posedge. 1918 */ 1919 #define GPIO_PIN26_SYNC1_BYPASS 0x00000003U 1920 #define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) 1921 #define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U 1922 #define GPIO_PIN26_SYNC1_BYPASS_S 3 1923 /** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1924 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1925 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1926 * at high level 1927 */ 1928 #define GPIO_PIN26_INT_TYPE 0x00000007U 1929 #define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) 1930 #define GPIO_PIN26_INT_TYPE_V 0x00000007U 1931 #define GPIO_PIN26_INT_TYPE_S 7 1932 /** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1933 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1934 */ 1935 #define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) 1936 #define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) 1937 #define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U 1938 #define GPIO_PIN26_WAKEUP_ENABLE_S 10 1939 /** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; 1940 * reserved 1941 */ 1942 #define GPIO_PIN26_CONFIG 0x00000003U 1943 #define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) 1944 #define GPIO_PIN26_CONFIG_V 0x00000003U 1945 #define GPIO_PIN26_CONFIG_S 11 1946 /** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; 1947 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 1948 * interrupt. 1949 */ 1950 #define GPIO_PIN26_INT_ENA 0x0000001FU 1951 #define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) 1952 #define GPIO_PIN26_INT_ENA_V 0x0000001FU 1953 #define GPIO_PIN26_INT_ENA_S 13 1954 1955 /** GPIO_PIN27_REG register 1956 * GPIO pin configuration register 1957 */ 1958 #define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) 1959 /** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 1960 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1961 * posedge. 1962 */ 1963 #define GPIO_PIN27_SYNC2_BYPASS 0x00000003U 1964 #define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) 1965 #define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U 1966 #define GPIO_PIN27_SYNC2_BYPASS_S 0 1967 /** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 1968 * set this bit to select pad driver. 1:open-drain. 0:normal. 1969 */ 1970 #define GPIO_PIN27_PAD_DRIVER (BIT(2)) 1971 #define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) 1972 #define GPIO_PIN27_PAD_DRIVER_V 0x00000001U 1973 #define GPIO_PIN27_PAD_DRIVER_S 2 1974 /** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 1975 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 1976 * posedge. 1977 */ 1978 #define GPIO_PIN27_SYNC1_BYPASS 0x00000003U 1979 #define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) 1980 #define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U 1981 #define GPIO_PIN27_SYNC1_BYPASS_S 3 1982 /** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 1983 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 1984 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 1985 * at high level 1986 */ 1987 #define GPIO_PIN27_INT_TYPE 0x00000007U 1988 #define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) 1989 #define GPIO_PIN27_INT_TYPE_V 0x00000007U 1990 #define GPIO_PIN27_INT_TYPE_S 7 1991 /** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 1992 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 1993 */ 1994 #define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) 1995 #define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) 1996 #define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U 1997 #define GPIO_PIN27_WAKEUP_ENABLE_S 10 1998 /** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; 1999 * reserved 2000 */ 2001 #define GPIO_PIN27_CONFIG 0x00000003U 2002 #define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) 2003 #define GPIO_PIN27_CONFIG_V 0x00000003U 2004 #define GPIO_PIN27_CONFIG_S 11 2005 /** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2006 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2007 * interrupt. 2008 */ 2009 #define GPIO_PIN27_INT_ENA 0x0000001FU 2010 #define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) 2011 #define GPIO_PIN27_INT_ENA_V 0x0000001FU 2012 #define GPIO_PIN27_INT_ENA_S 13 2013 2014 /** GPIO_PIN28_REG register 2015 * GPIO pin configuration register 2016 */ 2017 #define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) 2018 /** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 2019 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2020 * posedge. 2021 */ 2022 #define GPIO_PIN28_SYNC2_BYPASS 0x00000003U 2023 #define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) 2024 #define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U 2025 #define GPIO_PIN28_SYNC2_BYPASS_S 0 2026 /** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 2027 * set this bit to select pad driver. 1:open-drain. 0:normal. 2028 */ 2029 #define GPIO_PIN28_PAD_DRIVER (BIT(2)) 2030 #define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) 2031 #define GPIO_PIN28_PAD_DRIVER_V 0x00000001U 2032 #define GPIO_PIN28_PAD_DRIVER_S 2 2033 /** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 2034 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2035 * posedge. 2036 */ 2037 #define GPIO_PIN28_SYNC1_BYPASS 0x00000003U 2038 #define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) 2039 #define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U 2040 #define GPIO_PIN28_SYNC1_BYPASS_S 3 2041 /** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 2042 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 2043 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 2044 * at high level 2045 */ 2046 #define GPIO_PIN28_INT_TYPE 0x00000007U 2047 #define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) 2048 #define GPIO_PIN28_INT_TYPE_V 0x00000007U 2049 #define GPIO_PIN28_INT_TYPE_S 7 2050 /** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 2051 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 2052 */ 2053 #define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) 2054 #define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) 2055 #define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U 2056 #define GPIO_PIN28_WAKEUP_ENABLE_S 10 2057 /** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; 2058 * reserved 2059 */ 2060 #define GPIO_PIN28_CONFIG 0x00000003U 2061 #define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) 2062 #define GPIO_PIN28_CONFIG_V 0x00000003U 2063 #define GPIO_PIN28_CONFIG_S 11 2064 /** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2065 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2066 * interrupt. 2067 */ 2068 #define GPIO_PIN28_INT_ENA 0x0000001FU 2069 #define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) 2070 #define GPIO_PIN28_INT_ENA_V 0x0000001FU 2071 #define GPIO_PIN28_INT_ENA_S 13 2072 2073 /** GPIO_PIN29_REG register 2074 * GPIO pin configuration register 2075 */ 2076 #define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) 2077 /** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 2078 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2079 * posedge. 2080 */ 2081 #define GPIO_PIN29_SYNC2_BYPASS 0x00000003U 2082 #define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) 2083 #define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U 2084 #define GPIO_PIN29_SYNC2_BYPASS_S 0 2085 /** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 2086 * set this bit to select pad driver. 1:open-drain. 0:normal. 2087 */ 2088 #define GPIO_PIN29_PAD_DRIVER (BIT(2)) 2089 #define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) 2090 #define GPIO_PIN29_PAD_DRIVER_V 0x00000001U 2091 #define GPIO_PIN29_PAD_DRIVER_S 2 2092 /** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 2093 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2094 * posedge. 2095 */ 2096 #define GPIO_PIN29_SYNC1_BYPASS 0x00000003U 2097 #define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) 2098 #define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U 2099 #define GPIO_PIN29_SYNC1_BYPASS_S 3 2100 /** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 2101 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 2102 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 2103 * at high level 2104 */ 2105 #define GPIO_PIN29_INT_TYPE 0x00000007U 2106 #define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) 2107 #define GPIO_PIN29_INT_TYPE_V 0x00000007U 2108 #define GPIO_PIN29_INT_TYPE_S 7 2109 /** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 2110 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 2111 */ 2112 #define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) 2113 #define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) 2114 #define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U 2115 #define GPIO_PIN29_WAKEUP_ENABLE_S 10 2116 /** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; 2117 * reserved 2118 */ 2119 #define GPIO_PIN29_CONFIG 0x00000003U 2120 #define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) 2121 #define GPIO_PIN29_CONFIG_V 0x00000003U 2122 #define GPIO_PIN29_CONFIG_S 11 2123 /** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2124 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2125 * interrupt. 2126 */ 2127 #define GPIO_PIN29_INT_ENA 0x0000001FU 2128 #define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) 2129 #define GPIO_PIN29_INT_ENA_V 0x0000001FU 2130 #define GPIO_PIN29_INT_ENA_S 13 2131 2132 /** GPIO_PIN30_REG register 2133 * GPIO pin configuration register 2134 */ 2135 #define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) 2136 /** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 2137 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2138 * posedge. 2139 */ 2140 #define GPIO_PIN30_SYNC2_BYPASS 0x00000003U 2141 #define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) 2142 #define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U 2143 #define GPIO_PIN30_SYNC2_BYPASS_S 0 2144 /** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 2145 * set this bit to select pad driver. 1:open-drain. 0:normal. 2146 */ 2147 #define GPIO_PIN30_PAD_DRIVER (BIT(2)) 2148 #define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) 2149 #define GPIO_PIN30_PAD_DRIVER_V 0x00000001U 2150 #define GPIO_PIN30_PAD_DRIVER_S 2 2151 /** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 2152 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2153 * posedge. 2154 */ 2155 #define GPIO_PIN30_SYNC1_BYPASS 0x00000003U 2156 #define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) 2157 #define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U 2158 #define GPIO_PIN30_SYNC1_BYPASS_S 3 2159 /** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 2160 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 2161 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 2162 * at high level 2163 */ 2164 #define GPIO_PIN30_INT_TYPE 0x00000007U 2165 #define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) 2166 #define GPIO_PIN30_INT_TYPE_V 0x00000007U 2167 #define GPIO_PIN30_INT_TYPE_S 7 2168 /** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 2169 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 2170 */ 2171 #define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) 2172 #define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) 2173 #define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U 2174 #define GPIO_PIN30_WAKEUP_ENABLE_S 10 2175 /** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; 2176 * reserved 2177 */ 2178 #define GPIO_PIN30_CONFIG 0x00000003U 2179 #define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) 2180 #define GPIO_PIN30_CONFIG_V 0x00000003U 2181 #define GPIO_PIN30_CONFIG_S 11 2182 /** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2183 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2184 * interrupt. 2185 */ 2186 #define GPIO_PIN30_INT_ENA 0x0000001FU 2187 #define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) 2188 #define GPIO_PIN30_INT_ENA_V 0x0000001FU 2189 #define GPIO_PIN30_INT_ENA_S 13 2190 2191 /** GPIO_PIN31_REG register 2192 * GPIO pin configuration register 2193 */ 2194 #define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0) 2195 /** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 2196 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2197 * posedge. 2198 */ 2199 #define GPIO_PIN31_SYNC2_BYPASS 0x00000003U 2200 #define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) 2201 #define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U 2202 #define GPIO_PIN31_SYNC2_BYPASS_S 0 2203 /** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 2204 * set this bit to select pad driver. 1:open-drain. 0:normal. 2205 */ 2206 #define GPIO_PIN31_PAD_DRIVER (BIT(2)) 2207 #define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) 2208 #define GPIO_PIN31_PAD_DRIVER_V 0x00000001U 2209 #define GPIO_PIN31_PAD_DRIVER_S 2 2210 /** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 2211 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2212 * posedge. 2213 */ 2214 #define GPIO_PIN31_SYNC1_BYPASS 0x00000003U 2215 #define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) 2216 #define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U 2217 #define GPIO_PIN31_SYNC1_BYPASS_S 3 2218 /** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 2219 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 2220 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 2221 * at high level 2222 */ 2223 #define GPIO_PIN31_INT_TYPE 0x00000007U 2224 #define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) 2225 #define GPIO_PIN31_INT_TYPE_V 0x00000007U 2226 #define GPIO_PIN31_INT_TYPE_S 7 2227 /** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 2228 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 2229 */ 2230 #define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) 2231 #define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) 2232 #define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U 2233 #define GPIO_PIN31_WAKEUP_ENABLE_S 10 2234 /** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0; 2235 * reserved 2236 */ 2237 #define GPIO_PIN31_CONFIG 0x00000003U 2238 #define GPIO_PIN31_CONFIG_M (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S) 2239 #define GPIO_PIN31_CONFIG_V 0x00000003U 2240 #define GPIO_PIN31_CONFIG_S 11 2241 /** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2242 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2243 * interrupt. 2244 */ 2245 #define GPIO_PIN31_INT_ENA 0x0000001FU 2246 #define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) 2247 #define GPIO_PIN31_INT_ENA_V 0x0000001FU 2248 #define GPIO_PIN31_INT_ENA_S 13 2249 2250 /** GPIO_PIN32_REG register 2251 * GPIO pin configuration register 2252 */ 2253 #define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4) 2254 /** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 2255 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2256 * posedge. 2257 */ 2258 #define GPIO_PIN32_SYNC2_BYPASS 0x00000003U 2259 #define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) 2260 #define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003U 2261 #define GPIO_PIN32_SYNC2_BYPASS_S 0 2262 /** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 2263 * set this bit to select pad driver. 1:open-drain. 0:normal. 2264 */ 2265 #define GPIO_PIN32_PAD_DRIVER (BIT(2)) 2266 #define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) 2267 #define GPIO_PIN32_PAD_DRIVER_V 0x00000001U 2268 #define GPIO_PIN32_PAD_DRIVER_S 2 2269 /** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 2270 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2271 * posedge. 2272 */ 2273 #define GPIO_PIN32_SYNC1_BYPASS 0x00000003U 2274 #define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) 2275 #define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003U 2276 #define GPIO_PIN32_SYNC1_BYPASS_S 3 2277 /** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 2278 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 2279 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 2280 * at high level 2281 */ 2282 #define GPIO_PIN32_INT_TYPE 0x00000007U 2283 #define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) 2284 #define GPIO_PIN32_INT_TYPE_V 0x00000007U 2285 #define GPIO_PIN32_INT_TYPE_S 7 2286 /** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 2287 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 2288 */ 2289 #define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) 2290 #define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) 2291 #define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001U 2292 #define GPIO_PIN32_WAKEUP_ENABLE_S 10 2293 /** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0; 2294 * reserved 2295 */ 2296 #define GPIO_PIN32_CONFIG 0x00000003U 2297 #define GPIO_PIN32_CONFIG_M (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S) 2298 #define GPIO_PIN32_CONFIG_V 0x00000003U 2299 #define GPIO_PIN32_CONFIG_S 11 2300 /** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2301 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2302 * interrupt. 2303 */ 2304 #define GPIO_PIN32_INT_ENA 0x0000001FU 2305 #define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) 2306 #define GPIO_PIN32_INT_ENA_V 0x0000001FU 2307 #define GPIO_PIN32_INT_ENA_S 13 2308 2309 /** GPIO_PIN33_REG register 2310 * GPIO pin configuration register 2311 */ 2312 #define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8) 2313 /** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 2314 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2315 * posedge. 2316 */ 2317 #define GPIO_PIN33_SYNC2_BYPASS 0x00000003U 2318 #define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) 2319 #define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003U 2320 #define GPIO_PIN33_SYNC2_BYPASS_S 0 2321 /** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 2322 * set this bit to select pad driver. 1:open-drain. 0:normal. 2323 */ 2324 #define GPIO_PIN33_PAD_DRIVER (BIT(2)) 2325 #define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) 2326 #define GPIO_PIN33_PAD_DRIVER_V 0x00000001U 2327 #define GPIO_PIN33_PAD_DRIVER_S 2 2328 /** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 2329 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2330 * posedge. 2331 */ 2332 #define GPIO_PIN33_SYNC1_BYPASS 0x00000003U 2333 #define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) 2334 #define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003U 2335 #define GPIO_PIN33_SYNC1_BYPASS_S 3 2336 /** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 2337 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 2338 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 2339 * at high level 2340 */ 2341 #define GPIO_PIN33_INT_TYPE 0x00000007U 2342 #define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) 2343 #define GPIO_PIN33_INT_TYPE_V 0x00000007U 2344 #define GPIO_PIN33_INT_TYPE_S 7 2345 /** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 2346 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 2347 */ 2348 #define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) 2349 #define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) 2350 #define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001U 2351 #define GPIO_PIN33_WAKEUP_ENABLE_S 10 2352 /** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0; 2353 * reserved 2354 */ 2355 #define GPIO_PIN33_CONFIG 0x00000003U 2356 #define GPIO_PIN33_CONFIG_M (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S) 2357 #define GPIO_PIN33_CONFIG_V 0x00000003U 2358 #define GPIO_PIN33_CONFIG_S 11 2359 /** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2360 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2361 * interrupt. 2362 */ 2363 #define GPIO_PIN33_INT_ENA 0x0000001FU 2364 #define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) 2365 #define GPIO_PIN33_INT_ENA_V 0x0000001FU 2366 #define GPIO_PIN33_INT_ENA_S 13 2367 2368 /** GPIO_PIN34_REG register 2369 * GPIO pin configuration register 2370 */ 2371 #define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc) 2372 /** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; 2373 * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2374 * posedge. 2375 */ 2376 #define GPIO_PIN34_SYNC2_BYPASS 0x00000003U 2377 #define GPIO_PIN34_SYNC2_BYPASS_M (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S) 2378 #define GPIO_PIN34_SYNC2_BYPASS_V 0x00000003U 2379 #define GPIO_PIN34_SYNC2_BYPASS_S 0 2380 /** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0; 2381 * set this bit to select pad driver. 1:open-drain. 0:normal. 2382 */ 2383 #define GPIO_PIN34_PAD_DRIVER (BIT(2)) 2384 #define GPIO_PIN34_PAD_DRIVER_M (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S) 2385 #define GPIO_PIN34_PAD_DRIVER_V 0x00000001U 2386 #define GPIO_PIN34_PAD_DRIVER_S 2 2387 /** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; 2388 * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at 2389 * posedge. 2390 */ 2391 #define GPIO_PIN34_SYNC1_BYPASS 0x00000003U 2392 #define GPIO_PIN34_SYNC1_BYPASS_M (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S) 2393 #define GPIO_PIN34_SYNC1_BYPASS_V 0x00000003U 2394 #define GPIO_PIN34_SYNC1_BYPASS_S 3 2395 /** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0; 2396 * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at 2397 * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid 2398 * at high level 2399 */ 2400 #define GPIO_PIN34_INT_TYPE 0x00000007U 2401 #define GPIO_PIN34_INT_TYPE_M (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S) 2402 #define GPIO_PIN34_INT_TYPE_V 0x00000007U 2403 #define GPIO_PIN34_INT_TYPE_S 7 2404 /** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; 2405 * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 2406 */ 2407 #define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) 2408 #define GPIO_PIN34_WAKEUP_ENABLE_M (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S) 2409 #define GPIO_PIN34_WAKEUP_ENABLE_V 0x00000001U 2410 #define GPIO_PIN34_WAKEUP_ENABLE_S 10 2411 /** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0; 2412 * reserved 2413 */ 2414 #define GPIO_PIN34_CONFIG 0x00000003U 2415 #define GPIO_PIN34_CONFIG_M (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S) 2416 #define GPIO_PIN34_CONFIG_V 0x00000003U 2417 #define GPIO_PIN34_CONFIG_S 11 2418 /** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0; 2419 * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) 2420 * interrupt. 2421 */ 2422 #define GPIO_PIN34_INT_ENA 0x0000001FU 2423 #define GPIO_PIN34_INT_ENA_M (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S) 2424 #define GPIO_PIN34_INT_ENA_V 0x0000001FU 2425 #define GPIO_PIN34_INT_ENA_S 13 2426 2427 /** GPIO_STATUS_NEXT_REG register 2428 * GPIO interrupt source register for GPIO0-31 2429 */ 2430 #define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) 2431 /** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; 2432 * GPIO interrupt source register for GPIO0-31 2433 */ 2434 #define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU 2435 #define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) 2436 #define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU 2437 #define GPIO_STATUS_INTERRUPT_NEXT_S 0 2438 2439 /** GPIO_STATUS_NEXT1_REG register 2440 * GPIO interrupt source register for GPIO32-34 2441 */ 2442 #define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) 2443 /** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [2:0]; default: 0; 2444 * GPIO interrupt source register for GPIO32-34 2445 */ 2446 #define GPIO_STATUS_INTERRUPT_NEXT1 0x00000007U 2447 #define GPIO_STATUS_INTERRUPT_NEXT1_M (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S) 2448 #define GPIO_STATUS_INTERRUPT_NEXT1_V 0x00000007U 2449 #define GPIO_STATUS_INTERRUPT_NEXT1_S 0 2450 2451 /** GPIO_FUNC0_IN_SEL_CFG_REG register 2452 * GPIO input function configuration register 2453 */ 2454 #define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) 2455 /** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2456 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2457 * high level. s=0x3C: set this port always low level. 2458 */ 2459 #define GPIO_FUNC0_IN_SEL 0x0000003FU 2460 #define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) 2461 #define GPIO_FUNC0_IN_SEL_V 0x0000003FU 2462 #define GPIO_FUNC0_IN_SEL_S 0 2463 /** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2464 * set this bit to invert input signal. 1:invert. 0:not invert. 2465 */ 2466 #define GPIO_FUNC0_IN_INV_SEL (BIT(6)) 2467 #define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) 2468 #define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U 2469 #define GPIO_FUNC0_IN_INV_SEL_S 6 2470 /** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; 2471 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2472 */ 2473 #define GPIO_SIG0_IN_SEL (BIT(7)) 2474 #define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) 2475 #define GPIO_SIG0_IN_SEL_V 0x00000001U 2476 #define GPIO_SIG0_IN_SEL_S 7 2477 2478 /** GPIO_FUNC6_IN_SEL_CFG_REG register 2479 * GPIO input function configuration register 2480 */ 2481 #define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) 2482 /** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2483 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2484 * high level. s=0x3C: set this port always low level. 2485 */ 2486 #define GPIO_FUNC6_IN_SEL 0x0000003FU 2487 #define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) 2488 #define GPIO_FUNC6_IN_SEL_V 0x0000003FU 2489 #define GPIO_FUNC6_IN_SEL_S 0 2490 /** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2491 * set this bit to invert input signal. 1:invert. 0:not invert. 2492 */ 2493 #define GPIO_FUNC6_IN_INV_SEL (BIT(6)) 2494 #define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) 2495 #define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U 2496 #define GPIO_FUNC6_IN_INV_SEL_S 6 2497 /** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; 2498 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2499 */ 2500 #define GPIO_SIG6_IN_SEL (BIT(7)) 2501 #define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) 2502 #define GPIO_SIG6_IN_SEL_V 0x00000001U 2503 #define GPIO_SIG6_IN_SEL_S 7 2504 2505 /** GPIO_FUNC7_IN_SEL_CFG_REG register 2506 * GPIO input function configuration register 2507 */ 2508 #define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) 2509 /** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2510 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2511 * high level. s=0x3C: set this port always low level. 2512 */ 2513 #define GPIO_FUNC7_IN_SEL 0x0000003FU 2514 #define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) 2515 #define GPIO_FUNC7_IN_SEL_V 0x0000003FU 2516 #define GPIO_FUNC7_IN_SEL_S 0 2517 /** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2518 * set this bit to invert input signal. 1:invert. 0:not invert. 2519 */ 2520 #define GPIO_FUNC7_IN_INV_SEL (BIT(6)) 2521 #define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) 2522 #define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U 2523 #define GPIO_FUNC7_IN_INV_SEL_S 6 2524 /** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; 2525 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2526 */ 2527 #define GPIO_SIG7_IN_SEL (BIT(7)) 2528 #define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) 2529 #define GPIO_SIG7_IN_SEL_V 0x00000001U 2530 #define GPIO_SIG7_IN_SEL_S 7 2531 2532 /** GPIO_FUNC8_IN_SEL_CFG_REG register 2533 * GPIO input function configuration register 2534 */ 2535 #define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) 2536 /** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2537 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2538 * high level. s=0x3C: set this port always low level. 2539 */ 2540 #define GPIO_FUNC8_IN_SEL 0x0000003FU 2541 #define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) 2542 #define GPIO_FUNC8_IN_SEL_V 0x0000003FU 2543 #define GPIO_FUNC8_IN_SEL_S 0 2544 /** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2545 * set this bit to invert input signal. 1:invert. 0:not invert. 2546 */ 2547 #define GPIO_FUNC8_IN_INV_SEL (BIT(6)) 2548 #define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) 2549 #define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U 2550 #define GPIO_FUNC8_IN_INV_SEL_S 6 2551 /** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; 2552 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2553 */ 2554 #define GPIO_SIG8_IN_SEL (BIT(7)) 2555 #define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) 2556 #define GPIO_SIG8_IN_SEL_V 0x00000001U 2557 #define GPIO_SIG8_IN_SEL_S 7 2558 2559 /** GPIO_FUNC9_IN_SEL_CFG_REG register 2560 * GPIO input function configuration register 2561 */ 2562 #define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) 2563 /** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 56; 2564 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2565 * high level. s=0x3C: set this port always low level. 2566 */ 2567 #define GPIO_FUNC9_IN_SEL 0x0000003FU 2568 #define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) 2569 #define GPIO_FUNC9_IN_SEL_V 0x0000003FU 2570 #define GPIO_FUNC9_IN_SEL_S 0 2571 /** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2572 * set this bit to invert input signal. 1:invert. 0:not invert. 2573 */ 2574 #define GPIO_FUNC9_IN_INV_SEL (BIT(6)) 2575 #define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) 2576 #define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U 2577 #define GPIO_FUNC9_IN_INV_SEL_S 6 2578 /** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; 2579 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2580 */ 2581 #define GPIO_SIG9_IN_SEL (BIT(7)) 2582 #define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) 2583 #define GPIO_SIG9_IN_SEL_V 0x00000001U 2584 #define GPIO_SIG9_IN_SEL_S 7 2585 2586 /** GPIO_FUNC10_IN_SEL_CFG_REG register 2587 * GPIO input function configuration register 2588 */ 2589 #define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) 2590 /** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2591 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2592 * high level. s=0x3C: set this port always low level. 2593 */ 2594 #define GPIO_FUNC10_IN_SEL 0x0000003FU 2595 #define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) 2596 #define GPIO_FUNC10_IN_SEL_V 0x0000003FU 2597 #define GPIO_FUNC10_IN_SEL_S 0 2598 /** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2599 * set this bit to invert input signal. 1:invert. 0:not invert. 2600 */ 2601 #define GPIO_FUNC10_IN_INV_SEL (BIT(6)) 2602 #define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) 2603 #define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U 2604 #define GPIO_FUNC10_IN_INV_SEL_S 6 2605 /** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; 2606 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2607 */ 2608 #define GPIO_SIG10_IN_SEL (BIT(7)) 2609 #define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) 2610 #define GPIO_SIG10_IN_SEL_V 0x00000001U 2611 #define GPIO_SIG10_IN_SEL_S 7 2612 2613 /** GPIO_FUNC11_IN_SEL_CFG_REG register 2614 * GPIO input function configuration register 2615 */ 2616 #define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) 2617 /** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2618 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2619 * high level. s=0x3C: set this port always low level. 2620 */ 2621 #define GPIO_FUNC11_IN_SEL 0x0000003FU 2622 #define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) 2623 #define GPIO_FUNC11_IN_SEL_V 0x0000003FU 2624 #define GPIO_FUNC11_IN_SEL_S 0 2625 /** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2626 * set this bit to invert input signal. 1:invert. 0:not invert. 2627 */ 2628 #define GPIO_FUNC11_IN_INV_SEL (BIT(6)) 2629 #define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) 2630 #define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U 2631 #define GPIO_FUNC11_IN_INV_SEL_S 6 2632 /** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; 2633 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2634 */ 2635 #define GPIO_SIG11_IN_SEL (BIT(7)) 2636 #define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) 2637 #define GPIO_SIG11_IN_SEL_V 0x00000001U 2638 #define GPIO_SIG11_IN_SEL_S 7 2639 2640 /** GPIO_FUNC12_IN_SEL_CFG_REG register 2641 * GPIO input function configuration register 2642 */ 2643 #define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) 2644 /** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2645 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2646 * high level. s=0x3C: set this port always low level. 2647 */ 2648 #define GPIO_FUNC12_IN_SEL 0x0000003FU 2649 #define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) 2650 #define GPIO_FUNC12_IN_SEL_V 0x0000003FU 2651 #define GPIO_FUNC12_IN_SEL_S 0 2652 /** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2653 * set this bit to invert input signal. 1:invert. 0:not invert. 2654 */ 2655 #define GPIO_FUNC12_IN_INV_SEL (BIT(6)) 2656 #define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) 2657 #define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U 2658 #define GPIO_FUNC12_IN_INV_SEL_S 6 2659 /** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; 2660 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2661 */ 2662 #define GPIO_SIG12_IN_SEL (BIT(7)) 2663 #define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) 2664 #define GPIO_SIG12_IN_SEL_V 0x00000001U 2665 #define GPIO_SIG12_IN_SEL_S 7 2666 2667 /** GPIO_FUNC13_IN_SEL_CFG_REG register 2668 * GPIO input function configuration register 2669 */ 2670 #define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) 2671 /** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2672 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2673 * high level. s=0x3C: set this port always low level. 2674 */ 2675 #define GPIO_FUNC13_IN_SEL 0x0000003FU 2676 #define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) 2677 #define GPIO_FUNC13_IN_SEL_V 0x0000003FU 2678 #define GPIO_FUNC13_IN_SEL_S 0 2679 /** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2680 * set this bit to invert input signal. 1:invert. 0:not invert. 2681 */ 2682 #define GPIO_FUNC13_IN_INV_SEL (BIT(6)) 2683 #define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) 2684 #define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U 2685 #define GPIO_FUNC13_IN_INV_SEL_S 6 2686 /** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; 2687 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2688 */ 2689 #define GPIO_SIG13_IN_SEL (BIT(7)) 2690 #define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) 2691 #define GPIO_SIG13_IN_SEL_V 0x00000001U 2692 #define GPIO_SIG13_IN_SEL_S 7 2693 2694 /** GPIO_FUNC14_IN_SEL_CFG_REG register 2695 * GPIO input function configuration register 2696 */ 2697 #define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) 2698 /** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2699 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2700 * high level. s=0x3C: set this port always low level. 2701 */ 2702 #define GPIO_FUNC14_IN_SEL 0x0000003FU 2703 #define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) 2704 #define GPIO_FUNC14_IN_SEL_V 0x0000003FU 2705 #define GPIO_FUNC14_IN_SEL_S 0 2706 /** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2707 * set this bit to invert input signal. 1:invert. 0:not invert. 2708 */ 2709 #define GPIO_FUNC14_IN_INV_SEL (BIT(6)) 2710 #define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) 2711 #define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U 2712 #define GPIO_FUNC14_IN_INV_SEL_S 6 2713 /** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; 2714 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2715 */ 2716 #define GPIO_SIG14_IN_SEL (BIT(7)) 2717 #define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) 2718 #define GPIO_SIG14_IN_SEL_V 0x00000001U 2719 #define GPIO_SIG14_IN_SEL_S 7 2720 2721 /** GPIO_FUNC15_IN_SEL_CFG_REG register 2722 * GPIO input function configuration register 2723 */ 2724 #define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) 2725 /** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2726 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2727 * high level. s=0x3C: set this port always low level. 2728 */ 2729 #define GPIO_FUNC15_IN_SEL 0x0000003FU 2730 #define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) 2731 #define GPIO_FUNC15_IN_SEL_V 0x0000003FU 2732 #define GPIO_FUNC15_IN_SEL_S 0 2733 /** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2734 * set this bit to invert input signal. 1:invert. 0:not invert. 2735 */ 2736 #define GPIO_FUNC15_IN_INV_SEL (BIT(6)) 2737 #define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) 2738 #define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U 2739 #define GPIO_FUNC15_IN_INV_SEL_S 6 2740 /** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; 2741 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2742 */ 2743 #define GPIO_SIG15_IN_SEL (BIT(7)) 2744 #define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) 2745 #define GPIO_SIG15_IN_SEL_V 0x00000001U 2746 #define GPIO_SIG15_IN_SEL_S 7 2747 2748 /** GPIO_FUNC16_IN_SEL_CFG_REG register 2749 * GPIO input function configuration register 2750 */ 2751 #define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) 2752 /** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2753 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2754 * high level. s=0x3C: set this port always low level. 2755 */ 2756 #define GPIO_FUNC16_IN_SEL 0x0000003FU 2757 #define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) 2758 #define GPIO_FUNC16_IN_SEL_V 0x0000003FU 2759 #define GPIO_FUNC16_IN_SEL_S 0 2760 /** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2761 * set this bit to invert input signal. 1:invert. 0:not invert. 2762 */ 2763 #define GPIO_FUNC16_IN_INV_SEL (BIT(6)) 2764 #define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) 2765 #define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U 2766 #define GPIO_FUNC16_IN_INV_SEL_S 6 2767 /** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; 2768 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2769 */ 2770 #define GPIO_SIG16_IN_SEL (BIT(7)) 2771 #define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) 2772 #define GPIO_SIG16_IN_SEL_V 0x00000001U 2773 #define GPIO_SIG16_IN_SEL_S 7 2774 2775 /** GPIO_FUNC17_IN_SEL_CFG_REG register 2776 * GPIO input function configuration register 2777 */ 2778 #define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) 2779 /** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2780 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2781 * high level. s=0x3C: set this port always low level. 2782 */ 2783 #define GPIO_FUNC17_IN_SEL 0x0000003FU 2784 #define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) 2785 #define GPIO_FUNC17_IN_SEL_V 0x0000003FU 2786 #define GPIO_FUNC17_IN_SEL_S 0 2787 /** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2788 * set this bit to invert input signal. 1:invert. 0:not invert. 2789 */ 2790 #define GPIO_FUNC17_IN_INV_SEL (BIT(6)) 2791 #define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) 2792 #define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U 2793 #define GPIO_FUNC17_IN_INV_SEL_S 6 2794 /** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; 2795 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2796 */ 2797 #define GPIO_SIG17_IN_SEL (BIT(7)) 2798 #define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) 2799 #define GPIO_SIG17_IN_SEL_V 0x00000001U 2800 #define GPIO_SIG17_IN_SEL_S 7 2801 2802 /** GPIO_FUNC19_IN_SEL_CFG_REG register 2803 * GPIO input function configuration register 2804 */ 2805 #define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) 2806 /** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2807 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2808 * high level. s=0x3C: set this port always low level. 2809 */ 2810 #define GPIO_FUNC19_IN_SEL 0x0000003FU 2811 #define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) 2812 #define GPIO_FUNC19_IN_SEL_V 0x0000003FU 2813 #define GPIO_FUNC19_IN_SEL_S 0 2814 /** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2815 * set this bit to invert input signal. 1:invert. 0:not invert. 2816 */ 2817 #define GPIO_FUNC19_IN_INV_SEL (BIT(6)) 2818 #define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) 2819 #define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U 2820 #define GPIO_FUNC19_IN_INV_SEL_S 6 2821 /** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; 2822 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2823 */ 2824 #define GPIO_SIG19_IN_SEL (BIT(7)) 2825 #define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) 2826 #define GPIO_SIG19_IN_SEL_V 0x00000001U 2827 #define GPIO_SIG19_IN_SEL_S 7 2828 2829 /** GPIO_FUNC28_IN_SEL_CFG_REG register 2830 * GPIO input function configuration register 2831 */ 2832 #define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) 2833 /** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2834 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2835 * high level. s=0x3C: set this port always low level. 2836 */ 2837 #define GPIO_FUNC28_IN_SEL 0x0000003FU 2838 #define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) 2839 #define GPIO_FUNC28_IN_SEL_V 0x0000003FU 2840 #define GPIO_FUNC28_IN_SEL_S 0 2841 /** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2842 * set this bit to invert input signal. 1:invert. 0:not invert. 2843 */ 2844 #define GPIO_FUNC28_IN_INV_SEL (BIT(6)) 2845 #define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) 2846 #define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U 2847 #define GPIO_FUNC28_IN_INV_SEL_S 6 2848 /** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; 2849 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2850 */ 2851 #define GPIO_SIG28_IN_SEL (BIT(7)) 2852 #define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) 2853 #define GPIO_SIG28_IN_SEL_V 0x00000001U 2854 #define GPIO_SIG28_IN_SEL_S 7 2855 2856 /** GPIO_FUNC29_IN_SEL_CFG_REG register 2857 * GPIO input function configuration register 2858 */ 2859 #define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) 2860 /** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2861 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2862 * high level. s=0x3C: set this port always low level. 2863 */ 2864 #define GPIO_FUNC29_IN_SEL 0x0000003FU 2865 #define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) 2866 #define GPIO_FUNC29_IN_SEL_V 0x0000003FU 2867 #define GPIO_FUNC29_IN_SEL_S 0 2868 /** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2869 * set this bit to invert input signal. 1:invert. 0:not invert. 2870 */ 2871 #define GPIO_FUNC29_IN_INV_SEL (BIT(6)) 2872 #define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) 2873 #define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U 2874 #define GPIO_FUNC29_IN_INV_SEL_S 6 2875 /** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; 2876 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2877 */ 2878 #define GPIO_SIG29_IN_SEL (BIT(7)) 2879 #define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) 2880 #define GPIO_SIG29_IN_SEL_V 0x00000001U 2881 #define GPIO_SIG29_IN_SEL_S 7 2882 2883 /** GPIO_FUNC30_IN_SEL_CFG_REG register 2884 * GPIO input function configuration register 2885 */ 2886 #define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) 2887 /** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2888 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2889 * high level. s=0x3C: set this port always low level. 2890 */ 2891 #define GPIO_FUNC30_IN_SEL 0x0000003FU 2892 #define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) 2893 #define GPIO_FUNC30_IN_SEL_V 0x0000003FU 2894 #define GPIO_FUNC30_IN_SEL_S 0 2895 /** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2896 * set this bit to invert input signal. 1:invert. 0:not invert. 2897 */ 2898 #define GPIO_FUNC30_IN_INV_SEL (BIT(6)) 2899 #define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) 2900 #define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U 2901 #define GPIO_FUNC30_IN_INV_SEL_S 6 2902 /** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; 2903 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2904 */ 2905 #define GPIO_SIG30_IN_SEL (BIT(7)) 2906 #define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) 2907 #define GPIO_SIG30_IN_SEL_V 0x00000001U 2908 #define GPIO_SIG30_IN_SEL_S 7 2909 2910 /** GPIO_FUNC31_IN_SEL_CFG_REG register 2911 * GPIO input function configuration register 2912 */ 2913 #define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) 2914 /** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2915 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2916 * high level. s=0x3C: set this port always low level. 2917 */ 2918 #define GPIO_FUNC31_IN_SEL 0x0000003FU 2919 #define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) 2920 #define GPIO_FUNC31_IN_SEL_V 0x0000003FU 2921 #define GPIO_FUNC31_IN_SEL_S 0 2922 /** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2923 * set this bit to invert input signal. 1:invert. 0:not invert. 2924 */ 2925 #define GPIO_FUNC31_IN_INV_SEL (BIT(6)) 2926 #define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) 2927 #define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U 2928 #define GPIO_FUNC31_IN_INV_SEL_S 6 2929 /** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; 2930 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2931 */ 2932 #define GPIO_SIG31_IN_SEL (BIT(7)) 2933 #define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) 2934 #define GPIO_SIG31_IN_SEL_V 0x00000001U 2935 #define GPIO_SIG31_IN_SEL_S 7 2936 2937 /** GPIO_FUNC32_IN_SEL_CFG_REG register 2938 * GPIO input function configuration register 2939 */ 2940 #define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) 2941 /** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2942 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2943 * high level. s=0x3C: set this port always low level. 2944 */ 2945 #define GPIO_FUNC32_IN_SEL 0x0000003FU 2946 #define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) 2947 #define GPIO_FUNC32_IN_SEL_V 0x0000003FU 2948 #define GPIO_FUNC32_IN_SEL_S 0 2949 /** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2950 * set this bit to invert input signal. 1:invert. 0:not invert. 2951 */ 2952 #define GPIO_FUNC32_IN_INV_SEL (BIT(6)) 2953 #define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) 2954 #define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U 2955 #define GPIO_FUNC32_IN_INV_SEL_S 6 2956 /** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; 2957 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2958 */ 2959 #define GPIO_SIG32_IN_SEL (BIT(7)) 2960 #define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) 2961 #define GPIO_SIG32_IN_SEL_V 0x00000001U 2962 #define GPIO_SIG32_IN_SEL_S 7 2963 2964 /** GPIO_FUNC33_IN_SEL_CFG_REG register 2965 * GPIO input function configuration register 2966 */ 2967 #define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) 2968 /** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2969 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2970 * high level. s=0x3C: set this port always low level. 2971 */ 2972 #define GPIO_FUNC33_IN_SEL 0x0000003FU 2973 #define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) 2974 #define GPIO_FUNC33_IN_SEL_V 0x0000003FU 2975 #define GPIO_FUNC33_IN_SEL_S 0 2976 /** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 2977 * set this bit to invert input signal. 1:invert. 0:not invert. 2978 */ 2979 #define GPIO_FUNC33_IN_INV_SEL (BIT(6)) 2980 #define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) 2981 #define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U 2982 #define GPIO_FUNC33_IN_INV_SEL_S 6 2983 /** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; 2984 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 2985 */ 2986 #define GPIO_SIG33_IN_SEL (BIT(7)) 2987 #define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) 2988 #define GPIO_SIG33_IN_SEL_V 0x00000001U 2989 #define GPIO_SIG33_IN_SEL_S 7 2990 2991 /** GPIO_FUNC34_IN_SEL_CFG_REG register 2992 * GPIO input function configuration register 2993 */ 2994 #define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) 2995 /** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 60; 2996 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 2997 * high level. s=0x3C: set this port always low level. 2998 */ 2999 #define GPIO_FUNC34_IN_SEL 0x0000003FU 3000 #define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) 3001 #define GPIO_FUNC34_IN_SEL_V 0x0000003FU 3002 #define GPIO_FUNC34_IN_SEL_S 0 3003 /** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3004 * set this bit to invert input signal. 1:invert. 0:not invert. 3005 */ 3006 #define GPIO_FUNC34_IN_INV_SEL (BIT(6)) 3007 #define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) 3008 #define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U 3009 #define GPIO_FUNC34_IN_INV_SEL_S 6 3010 /** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; 3011 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3012 */ 3013 #define GPIO_SIG34_IN_SEL (BIT(7)) 3014 #define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) 3015 #define GPIO_SIG34_IN_SEL_V 0x00000001U 3016 #define GPIO_SIG34_IN_SEL_S 7 3017 3018 /** GPIO_FUNC35_IN_SEL_CFG_REG register 3019 * GPIO input function configuration register 3020 */ 3021 #define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) 3022 /** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3023 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3024 * high level. s=0x3C: set this port always low level. 3025 */ 3026 #define GPIO_FUNC35_IN_SEL 0x0000003FU 3027 #define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) 3028 #define GPIO_FUNC35_IN_SEL_V 0x0000003FU 3029 #define GPIO_FUNC35_IN_SEL_S 0 3030 /** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3031 * set this bit to invert input signal. 1:invert. 0:not invert. 3032 */ 3033 #define GPIO_FUNC35_IN_INV_SEL (BIT(6)) 3034 #define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) 3035 #define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U 3036 #define GPIO_FUNC35_IN_INV_SEL_S 6 3037 /** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; 3038 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3039 */ 3040 #define GPIO_SIG35_IN_SEL (BIT(7)) 3041 #define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) 3042 #define GPIO_SIG35_IN_SEL_V 0x00000001U 3043 #define GPIO_SIG35_IN_SEL_S 7 3044 3045 /** GPIO_FUNC40_IN_SEL_CFG_REG register 3046 * GPIO input function configuration register 3047 */ 3048 #define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) 3049 /** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3050 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3051 * high level. s=0x3C: set this port always low level. 3052 */ 3053 #define GPIO_FUNC40_IN_SEL 0x0000003FU 3054 #define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) 3055 #define GPIO_FUNC40_IN_SEL_V 0x0000003FU 3056 #define GPIO_FUNC40_IN_SEL_S 0 3057 /** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3058 * set this bit to invert input signal. 1:invert. 0:not invert. 3059 */ 3060 #define GPIO_FUNC40_IN_INV_SEL (BIT(6)) 3061 #define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) 3062 #define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U 3063 #define GPIO_FUNC40_IN_INV_SEL_S 6 3064 /** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; 3065 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3066 */ 3067 #define GPIO_SIG40_IN_SEL (BIT(7)) 3068 #define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) 3069 #define GPIO_SIG40_IN_SEL_V 0x00000001U 3070 #define GPIO_SIG40_IN_SEL_S 7 3071 3072 /** GPIO_FUNC41_IN_SEL_CFG_REG register 3073 * GPIO input function configuration register 3074 */ 3075 #define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) 3076 /** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3077 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3078 * high level. s=0x3C: set this port always low level. 3079 */ 3080 #define GPIO_FUNC41_IN_SEL 0x0000003FU 3081 #define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) 3082 #define GPIO_FUNC41_IN_SEL_V 0x0000003FU 3083 #define GPIO_FUNC41_IN_SEL_S 0 3084 /** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3085 * set this bit to invert input signal. 1:invert. 0:not invert. 3086 */ 3087 #define GPIO_FUNC41_IN_INV_SEL (BIT(6)) 3088 #define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) 3089 #define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U 3090 #define GPIO_FUNC41_IN_INV_SEL_S 6 3091 /** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; 3092 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3093 */ 3094 #define GPIO_SIG41_IN_SEL (BIT(7)) 3095 #define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) 3096 #define GPIO_SIG41_IN_SEL_V 0x00000001U 3097 #define GPIO_SIG41_IN_SEL_S 7 3098 3099 /** GPIO_FUNC42_IN_SEL_CFG_REG register 3100 * GPIO input function configuration register 3101 */ 3102 #define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) 3103 /** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3104 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3105 * high level. s=0x3C: set this port always low level. 3106 */ 3107 #define GPIO_FUNC42_IN_SEL 0x0000003FU 3108 #define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) 3109 #define GPIO_FUNC42_IN_SEL_V 0x0000003FU 3110 #define GPIO_FUNC42_IN_SEL_S 0 3111 /** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3112 * set this bit to invert input signal. 1:invert. 0:not invert. 3113 */ 3114 #define GPIO_FUNC42_IN_INV_SEL (BIT(6)) 3115 #define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) 3116 #define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U 3117 #define GPIO_FUNC42_IN_INV_SEL_S 6 3118 /** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; 3119 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3120 */ 3121 #define GPIO_SIG42_IN_SEL (BIT(7)) 3122 #define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) 3123 #define GPIO_SIG42_IN_SEL_V 0x00000001U 3124 #define GPIO_SIG42_IN_SEL_S 7 3125 3126 /** GPIO_FUNC45_IN_SEL_CFG_REG register 3127 * GPIO input function configuration register 3128 */ 3129 #define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) 3130 /** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 56; 3131 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3132 * high level. s=0x3C: set this port always low level. 3133 */ 3134 #define GPIO_FUNC45_IN_SEL 0x0000003FU 3135 #define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) 3136 #define GPIO_FUNC45_IN_SEL_V 0x0000003FU 3137 #define GPIO_FUNC45_IN_SEL_S 0 3138 /** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3139 * set this bit to invert input signal. 1:invert. 0:not invert. 3140 */ 3141 #define GPIO_FUNC45_IN_INV_SEL (BIT(6)) 3142 #define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) 3143 #define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U 3144 #define GPIO_FUNC45_IN_INV_SEL_S 6 3145 /** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; 3146 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3147 */ 3148 #define GPIO_SIG45_IN_SEL (BIT(7)) 3149 #define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) 3150 #define GPIO_SIG45_IN_SEL_V 0x00000001U 3151 #define GPIO_SIG45_IN_SEL_S 7 3152 3153 /** GPIO_FUNC46_IN_SEL_CFG_REG register 3154 * GPIO input function configuration register 3155 */ 3156 #define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) 3157 /** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 56; 3158 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3159 * high level. s=0x3C: set this port always low level. 3160 */ 3161 #define GPIO_FUNC46_IN_SEL 0x0000003FU 3162 #define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) 3163 #define GPIO_FUNC46_IN_SEL_V 0x0000003FU 3164 #define GPIO_FUNC46_IN_SEL_S 0 3165 /** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3166 * set this bit to invert input signal. 1:invert. 0:not invert. 3167 */ 3168 #define GPIO_FUNC46_IN_INV_SEL (BIT(6)) 3169 #define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) 3170 #define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U 3171 #define GPIO_FUNC46_IN_INV_SEL_S 6 3172 /** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; 3173 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3174 */ 3175 #define GPIO_SIG46_IN_SEL (BIT(7)) 3176 #define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) 3177 #define GPIO_SIG46_IN_SEL_V 0x00000001U 3178 #define GPIO_SIG46_IN_SEL_S 7 3179 3180 /** GPIO_FUNC47_IN_SEL_CFG_REG register 3181 * GPIO input function configuration register 3182 */ 3183 #define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) 3184 /** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3185 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3186 * high level. s=0x3C: set this port always low level. 3187 */ 3188 #define GPIO_FUNC47_IN_SEL 0x0000003FU 3189 #define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) 3190 #define GPIO_FUNC47_IN_SEL_V 0x0000003FU 3191 #define GPIO_FUNC47_IN_SEL_S 0 3192 /** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3193 * set this bit to invert input signal. 1:invert. 0:not invert. 3194 */ 3195 #define GPIO_FUNC47_IN_INV_SEL (BIT(6)) 3196 #define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) 3197 #define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U 3198 #define GPIO_FUNC47_IN_INV_SEL_S 6 3199 /** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; 3200 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3201 */ 3202 #define GPIO_SIG47_IN_SEL (BIT(7)) 3203 #define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) 3204 #define GPIO_SIG47_IN_SEL_V 0x00000001U 3205 #define GPIO_SIG47_IN_SEL_S 7 3206 3207 /** GPIO_FUNC48_IN_SEL_CFG_REG register 3208 * GPIO input function configuration register 3209 */ 3210 #define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) 3211 /** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3212 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3213 * high level. s=0x3C: set this port always low level. 3214 */ 3215 #define GPIO_FUNC48_IN_SEL 0x0000003FU 3216 #define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) 3217 #define GPIO_FUNC48_IN_SEL_V 0x0000003FU 3218 #define GPIO_FUNC48_IN_SEL_S 0 3219 /** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3220 * set this bit to invert input signal. 1:invert. 0:not invert. 3221 */ 3222 #define GPIO_FUNC48_IN_INV_SEL (BIT(6)) 3223 #define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) 3224 #define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U 3225 #define GPIO_FUNC48_IN_INV_SEL_S 6 3226 /** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; 3227 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3228 */ 3229 #define GPIO_SIG48_IN_SEL (BIT(7)) 3230 #define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) 3231 #define GPIO_SIG48_IN_SEL_V 0x00000001U 3232 #define GPIO_SIG48_IN_SEL_S 7 3233 3234 /** GPIO_FUNC49_IN_SEL_CFG_REG register 3235 * GPIO input function configuration register 3236 */ 3237 #define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) 3238 /** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3239 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3240 * high level. s=0x3C: set this port always low level. 3241 */ 3242 #define GPIO_FUNC49_IN_SEL 0x0000003FU 3243 #define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) 3244 #define GPIO_FUNC49_IN_SEL_V 0x0000003FU 3245 #define GPIO_FUNC49_IN_SEL_S 0 3246 /** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3247 * set this bit to invert input signal. 1:invert. 0:not invert. 3248 */ 3249 #define GPIO_FUNC49_IN_INV_SEL (BIT(6)) 3250 #define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) 3251 #define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U 3252 #define GPIO_FUNC49_IN_INV_SEL_S 6 3253 /** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; 3254 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3255 */ 3256 #define GPIO_SIG49_IN_SEL (BIT(7)) 3257 #define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) 3258 #define GPIO_SIG49_IN_SEL_V 0x00000001U 3259 #define GPIO_SIG49_IN_SEL_S 7 3260 3261 /** GPIO_FUNC50_IN_SEL_CFG_REG register 3262 * GPIO input function configuration register 3263 */ 3264 #define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) 3265 /** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3266 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3267 * high level. s=0x3C: set this port always low level. 3268 */ 3269 #define GPIO_FUNC50_IN_SEL 0x0000003FU 3270 #define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) 3271 #define GPIO_FUNC50_IN_SEL_V 0x0000003FU 3272 #define GPIO_FUNC50_IN_SEL_S 0 3273 /** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3274 * set this bit to invert input signal. 1:invert. 0:not invert. 3275 */ 3276 #define GPIO_FUNC50_IN_INV_SEL (BIT(6)) 3277 #define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) 3278 #define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U 3279 #define GPIO_FUNC50_IN_INV_SEL_S 6 3280 /** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; 3281 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3282 */ 3283 #define GPIO_SIG50_IN_SEL (BIT(7)) 3284 #define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) 3285 #define GPIO_SIG50_IN_SEL_V 0x00000001U 3286 #define GPIO_SIG50_IN_SEL_S 7 3287 3288 /** GPIO_FUNC51_IN_SEL_CFG_REG register 3289 * GPIO input function configuration register 3290 */ 3291 #define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) 3292 /** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3293 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3294 * high level. s=0x3C: set this port always low level. 3295 */ 3296 #define GPIO_FUNC51_IN_SEL 0x0000003FU 3297 #define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) 3298 #define GPIO_FUNC51_IN_SEL_V 0x0000003FU 3299 #define GPIO_FUNC51_IN_SEL_S 0 3300 /** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3301 * set this bit to invert input signal. 1:invert. 0:not invert. 3302 */ 3303 #define GPIO_FUNC51_IN_INV_SEL (BIT(6)) 3304 #define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) 3305 #define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U 3306 #define GPIO_FUNC51_IN_INV_SEL_S 6 3307 /** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; 3308 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3309 */ 3310 #define GPIO_SIG51_IN_SEL (BIT(7)) 3311 #define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) 3312 #define GPIO_SIG51_IN_SEL_V 0x00000001U 3313 #define GPIO_SIG51_IN_SEL_S 7 3314 3315 /** GPIO_FUNC52_IN_SEL_CFG_REG register 3316 * GPIO input function configuration register 3317 */ 3318 #define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) 3319 /** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3320 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3321 * high level. s=0x3C: set this port always low level. 3322 */ 3323 #define GPIO_FUNC52_IN_SEL 0x0000003FU 3324 #define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) 3325 #define GPIO_FUNC52_IN_SEL_V 0x0000003FU 3326 #define GPIO_FUNC52_IN_SEL_S 0 3327 /** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3328 * set this bit to invert input signal. 1:invert. 0:not invert. 3329 */ 3330 #define GPIO_FUNC52_IN_INV_SEL (BIT(6)) 3331 #define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) 3332 #define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U 3333 #define GPIO_FUNC52_IN_INV_SEL_S 6 3334 /** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; 3335 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3336 */ 3337 #define GPIO_SIG52_IN_SEL (BIT(7)) 3338 #define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) 3339 #define GPIO_SIG52_IN_SEL_V 0x00000001U 3340 #define GPIO_SIG52_IN_SEL_S 7 3341 3342 /** GPIO_FUNC53_IN_SEL_CFG_REG register 3343 * GPIO input function configuration register 3344 */ 3345 #define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) 3346 /** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3347 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3348 * high level. s=0x3C: set this port always low level. 3349 */ 3350 #define GPIO_FUNC53_IN_SEL 0x0000003FU 3351 #define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) 3352 #define GPIO_FUNC53_IN_SEL_V 0x0000003FU 3353 #define GPIO_FUNC53_IN_SEL_S 0 3354 /** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3355 * set this bit to invert input signal. 1:invert. 0:not invert. 3356 */ 3357 #define GPIO_FUNC53_IN_INV_SEL (BIT(6)) 3358 #define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) 3359 #define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U 3360 #define GPIO_FUNC53_IN_INV_SEL_S 6 3361 /** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; 3362 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3363 */ 3364 #define GPIO_SIG53_IN_SEL (BIT(7)) 3365 #define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) 3366 #define GPIO_SIG53_IN_SEL_V 0x00000001U 3367 #define GPIO_SIG53_IN_SEL_S 7 3368 3369 /** GPIO_FUNC54_IN_SEL_CFG_REG register 3370 * GPIO input function configuration register 3371 */ 3372 #define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) 3373 /** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3374 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3375 * high level. s=0x3C: set this port always low level. 3376 */ 3377 #define GPIO_FUNC54_IN_SEL 0x0000003FU 3378 #define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) 3379 #define GPIO_FUNC54_IN_SEL_V 0x0000003FU 3380 #define GPIO_FUNC54_IN_SEL_S 0 3381 /** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3382 * set this bit to invert input signal. 1:invert. 0:not invert. 3383 */ 3384 #define GPIO_FUNC54_IN_INV_SEL (BIT(6)) 3385 #define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) 3386 #define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U 3387 #define GPIO_FUNC54_IN_INV_SEL_S 6 3388 /** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; 3389 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3390 */ 3391 #define GPIO_SIG54_IN_SEL (BIT(7)) 3392 #define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) 3393 #define GPIO_SIG54_IN_SEL_V 0x00000001U 3394 #define GPIO_SIG54_IN_SEL_S 7 3395 3396 /** GPIO_FUNC55_IN_SEL_CFG_REG register 3397 * GPIO input function configuration register 3398 */ 3399 #define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) 3400 /** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3401 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3402 * high level. s=0x3C: set this port always low level. 3403 */ 3404 #define GPIO_FUNC55_IN_SEL 0x0000003FU 3405 #define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) 3406 #define GPIO_FUNC55_IN_SEL_V 0x0000003FU 3407 #define GPIO_FUNC55_IN_SEL_S 0 3408 /** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3409 * set this bit to invert input signal. 1:invert. 0:not invert. 3410 */ 3411 #define GPIO_FUNC55_IN_INV_SEL (BIT(6)) 3412 #define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) 3413 #define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U 3414 #define GPIO_FUNC55_IN_INV_SEL_S 6 3415 /** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0; 3416 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3417 */ 3418 #define GPIO_SIG55_IN_SEL (BIT(7)) 3419 #define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) 3420 #define GPIO_SIG55_IN_SEL_V 0x00000001U 3421 #define GPIO_SIG55_IN_SEL_S 7 3422 3423 /** GPIO_FUNC56_IN_SEL_CFG_REG register 3424 * GPIO input function configuration register 3425 */ 3426 #define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) 3427 /** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3428 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3429 * high level. s=0x3C: set this port always low level. 3430 */ 3431 #define GPIO_FUNC56_IN_SEL 0x0000003FU 3432 #define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) 3433 #define GPIO_FUNC56_IN_SEL_V 0x0000003FU 3434 #define GPIO_FUNC56_IN_SEL_S 0 3435 /** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3436 * set this bit to invert input signal. 1:invert. 0:not invert. 3437 */ 3438 #define GPIO_FUNC56_IN_INV_SEL (BIT(6)) 3439 #define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) 3440 #define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U 3441 #define GPIO_FUNC56_IN_INV_SEL_S 6 3442 /** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0; 3443 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3444 */ 3445 #define GPIO_SIG56_IN_SEL (BIT(7)) 3446 #define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) 3447 #define GPIO_SIG56_IN_SEL_V 0x00000001U 3448 #define GPIO_SIG56_IN_SEL_S 7 3449 3450 /** GPIO_FUNC57_IN_SEL_CFG_REG register 3451 * GPIO input function configuration register 3452 */ 3453 #define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) 3454 /** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3455 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3456 * high level. s=0x3C: set this port always low level. 3457 */ 3458 #define GPIO_FUNC57_IN_SEL 0x0000003FU 3459 #define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) 3460 #define GPIO_FUNC57_IN_SEL_V 0x0000003FU 3461 #define GPIO_FUNC57_IN_SEL_S 0 3462 /** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3463 * set this bit to invert input signal. 1:invert. 0:not invert. 3464 */ 3465 #define GPIO_FUNC57_IN_INV_SEL (BIT(6)) 3466 #define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) 3467 #define GPIO_FUNC57_IN_INV_SEL_V 0x00000001U 3468 #define GPIO_FUNC57_IN_INV_SEL_S 6 3469 /** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0; 3470 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3471 */ 3472 #define GPIO_SIG57_IN_SEL (BIT(7)) 3473 #define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) 3474 #define GPIO_SIG57_IN_SEL_V 0x00000001U 3475 #define GPIO_SIG57_IN_SEL_S 7 3476 3477 /** GPIO_FUNC58_IN_SEL_CFG_REG register 3478 * GPIO input function configuration register 3479 */ 3480 #define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) 3481 /** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3482 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3483 * high level. s=0x3C: set this port always low level. 3484 */ 3485 #define GPIO_FUNC58_IN_SEL 0x0000003FU 3486 #define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) 3487 #define GPIO_FUNC58_IN_SEL_V 0x0000003FU 3488 #define GPIO_FUNC58_IN_SEL_S 0 3489 /** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3490 * set this bit to invert input signal. 1:invert. 0:not invert. 3491 */ 3492 #define GPIO_FUNC58_IN_INV_SEL (BIT(6)) 3493 #define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) 3494 #define GPIO_FUNC58_IN_INV_SEL_V 0x00000001U 3495 #define GPIO_FUNC58_IN_INV_SEL_S 6 3496 /** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0; 3497 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3498 */ 3499 #define GPIO_SIG58_IN_SEL (BIT(7)) 3500 #define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) 3501 #define GPIO_SIG58_IN_SEL_V 0x00000001U 3502 #define GPIO_SIG58_IN_SEL_S 7 3503 3504 /** GPIO_FUNC59_IN_SEL_CFG_REG register 3505 * GPIO input function configuration register 3506 */ 3507 #define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) 3508 /** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3509 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3510 * high level. s=0x3C: set this port always low level. 3511 */ 3512 #define GPIO_FUNC59_IN_SEL 0x0000003FU 3513 #define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) 3514 #define GPIO_FUNC59_IN_SEL_V 0x0000003FU 3515 #define GPIO_FUNC59_IN_SEL_S 0 3516 /** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3517 * set this bit to invert input signal. 1:invert. 0:not invert. 3518 */ 3519 #define GPIO_FUNC59_IN_INV_SEL (BIT(6)) 3520 #define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) 3521 #define GPIO_FUNC59_IN_INV_SEL_V 0x00000001U 3522 #define GPIO_FUNC59_IN_INV_SEL_S 6 3523 /** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0; 3524 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3525 */ 3526 #define GPIO_SIG59_IN_SEL (BIT(7)) 3527 #define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) 3528 #define GPIO_SIG59_IN_SEL_V 0x00000001U 3529 #define GPIO_SIG59_IN_SEL_S 7 3530 3531 /** GPIO_FUNC60_IN_SEL_CFG_REG register 3532 * GPIO input function configuration register 3533 */ 3534 #define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) 3535 /** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3536 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3537 * high level. s=0x3C: set this port always low level. 3538 */ 3539 #define GPIO_FUNC60_IN_SEL 0x0000003FU 3540 #define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) 3541 #define GPIO_FUNC60_IN_SEL_V 0x0000003FU 3542 #define GPIO_FUNC60_IN_SEL_S 0 3543 /** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3544 * set this bit to invert input signal. 1:invert. 0:not invert. 3545 */ 3546 #define GPIO_FUNC60_IN_INV_SEL (BIT(6)) 3547 #define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) 3548 #define GPIO_FUNC60_IN_INV_SEL_V 0x00000001U 3549 #define GPIO_FUNC60_IN_INV_SEL_S 6 3550 /** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0; 3551 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3552 */ 3553 #define GPIO_SIG60_IN_SEL (BIT(7)) 3554 #define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) 3555 #define GPIO_SIG60_IN_SEL_V 0x00000001U 3556 #define GPIO_SIG60_IN_SEL_S 7 3557 3558 /** GPIO_FUNC61_IN_SEL_CFG_REG register 3559 * GPIO input function configuration register 3560 */ 3561 #define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) 3562 /** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3563 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3564 * high level. s=0x3C: set this port always low level. 3565 */ 3566 #define GPIO_FUNC61_IN_SEL 0x0000003FU 3567 #define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) 3568 #define GPIO_FUNC61_IN_SEL_V 0x0000003FU 3569 #define GPIO_FUNC61_IN_SEL_S 0 3570 /** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3571 * set this bit to invert input signal. 1:invert. 0:not invert. 3572 */ 3573 #define GPIO_FUNC61_IN_INV_SEL (BIT(6)) 3574 #define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) 3575 #define GPIO_FUNC61_IN_INV_SEL_V 0x00000001U 3576 #define GPIO_FUNC61_IN_INV_SEL_S 6 3577 /** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0; 3578 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3579 */ 3580 #define GPIO_SIG61_IN_SEL (BIT(7)) 3581 #define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) 3582 #define GPIO_SIG61_IN_SEL_V 0x00000001U 3583 #define GPIO_SIG61_IN_SEL_S 7 3584 3585 /** GPIO_FUNC62_IN_SEL_CFG_REG register 3586 * GPIO input function configuration register 3587 */ 3588 #define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) 3589 /** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3590 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3591 * high level. s=0x3C: set this port always low level. 3592 */ 3593 #define GPIO_FUNC62_IN_SEL 0x0000003FU 3594 #define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) 3595 #define GPIO_FUNC62_IN_SEL_V 0x0000003FU 3596 #define GPIO_FUNC62_IN_SEL_S 0 3597 /** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3598 * set this bit to invert input signal. 1:invert. 0:not invert. 3599 */ 3600 #define GPIO_FUNC62_IN_INV_SEL (BIT(6)) 3601 #define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) 3602 #define GPIO_FUNC62_IN_INV_SEL_V 0x00000001U 3603 #define GPIO_FUNC62_IN_INV_SEL_S 6 3604 /** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0; 3605 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3606 */ 3607 #define GPIO_SIG62_IN_SEL (BIT(7)) 3608 #define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) 3609 #define GPIO_SIG62_IN_SEL_V 0x00000001U 3610 #define GPIO_SIG62_IN_SEL_S 7 3611 3612 /** GPIO_FUNC63_IN_SEL_CFG_REG register 3613 * GPIO input function configuration register 3614 */ 3615 #define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) 3616 /** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3617 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3618 * high level. s=0x3C: set this port always low level. 3619 */ 3620 #define GPIO_FUNC63_IN_SEL 0x0000003FU 3621 #define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) 3622 #define GPIO_FUNC63_IN_SEL_V 0x0000003FU 3623 #define GPIO_FUNC63_IN_SEL_S 0 3624 /** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3625 * set this bit to invert input signal. 1:invert. 0:not invert. 3626 */ 3627 #define GPIO_FUNC63_IN_INV_SEL (BIT(6)) 3628 #define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) 3629 #define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U 3630 #define GPIO_FUNC63_IN_INV_SEL_S 6 3631 /** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; 3632 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3633 */ 3634 #define GPIO_SIG63_IN_SEL (BIT(7)) 3635 #define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) 3636 #define GPIO_SIG63_IN_SEL_V 0x00000001U 3637 #define GPIO_SIG63_IN_SEL_S 7 3638 3639 /** GPIO_FUNC64_IN_SEL_CFG_REG register 3640 * GPIO input function configuration register 3641 */ 3642 #define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) 3643 /** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3644 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3645 * high level. s=0x3C: set this port always low level. 3646 */ 3647 #define GPIO_FUNC64_IN_SEL 0x0000003FU 3648 #define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) 3649 #define GPIO_FUNC64_IN_SEL_V 0x0000003FU 3650 #define GPIO_FUNC64_IN_SEL_S 0 3651 /** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3652 * set this bit to invert input signal. 1:invert. 0:not invert. 3653 */ 3654 #define GPIO_FUNC64_IN_INV_SEL (BIT(6)) 3655 #define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) 3656 #define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U 3657 #define GPIO_FUNC64_IN_INV_SEL_S 6 3658 /** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; 3659 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3660 */ 3661 #define GPIO_SIG64_IN_SEL (BIT(7)) 3662 #define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) 3663 #define GPIO_SIG64_IN_SEL_V 0x00000001U 3664 #define GPIO_SIG64_IN_SEL_S 7 3665 3666 /** GPIO_FUNC65_IN_SEL_CFG_REG register 3667 * GPIO input function configuration register 3668 */ 3669 #define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) 3670 /** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3671 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3672 * high level. s=0x3C: set this port always low level. 3673 */ 3674 #define GPIO_FUNC65_IN_SEL 0x0000003FU 3675 #define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) 3676 #define GPIO_FUNC65_IN_SEL_V 0x0000003FU 3677 #define GPIO_FUNC65_IN_SEL_S 0 3678 /** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3679 * set this bit to invert input signal. 1:invert. 0:not invert. 3680 */ 3681 #define GPIO_FUNC65_IN_INV_SEL (BIT(6)) 3682 #define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) 3683 #define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U 3684 #define GPIO_FUNC65_IN_INV_SEL_S 6 3685 /** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; 3686 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3687 */ 3688 #define GPIO_SIG65_IN_SEL (BIT(7)) 3689 #define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) 3690 #define GPIO_SIG65_IN_SEL_V 0x00000001U 3691 #define GPIO_SIG65_IN_SEL_S 7 3692 3693 /** GPIO_FUNC66_IN_SEL_CFG_REG register 3694 * GPIO input function configuration register 3695 */ 3696 #define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) 3697 /** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3698 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3699 * high level. s=0x3C: set this port always low level. 3700 */ 3701 #define GPIO_FUNC66_IN_SEL 0x0000003FU 3702 #define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) 3703 #define GPIO_FUNC66_IN_SEL_V 0x0000003FU 3704 #define GPIO_FUNC66_IN_SEL_S 0 3705 /** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3706 * set this bit to invert input signal. 1:invert. 0:not invert. 3707 */ 3708 #define GPIO_FUNC66_IN_INV_SEL (BIT(6)) 3709 #define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) 3710 #define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U 3711 #define GPIO_FUNC66_IN_INV_SEL_S 6 3712 /** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; 3713 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3714 */ 3715 #define GPIO_SIG66_IN_SEL (BIT(7)) 3716 #define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) 3717 #define GPIO_SIG66_IN_SEL_V 0x00000001U 3718 #define GPIO_SIG66_IN_SEL_S 7 3719 3720 /** GPIO_FUNC67_IN_SEL_CFG_REG register 3721 * GPIO input function configuration register 3722 */ 3723 #define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) 3724 /** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3725 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3726 * high level. s=0x3C: set this port always low level. 3727 */ 3728 #define GPIO_FUNC67_IN_SEL 0x0000003FU 3729 #define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) 3730 #define GPIO_FUNC67_IN_SEL_V 0x0000003FU 3731 #define GPIO_FUNC67_IN_SEL_S 0 3732 /** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3733 * set this bit to invert input signal. 1:invert. 0:not invert. 3734 */ 3735 #define GPIO_FUNC67_IN_INV_SEL (BIT(6)) 3736 #define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) 3737 #define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U 3738 #define GPIO_FUNC67_IN_INV_SEL_S 6 3739 /** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; 3740 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3741 */ 3742 #define GPIO_SIG67_IN_SEL (BIT(7)) 3743 #define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) 3744 #define GPIO_SIG67_IN_SEL_V 0x00000001U 3745 #define GPIO_SIG67_IN_SEL_S 7 3746 3747 /** GPIO_FUNC68_IN_SEL_CFG_REG register 3748 * GPIO input function configuration register 3749 */ 3750 #define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) 3751 /** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3752 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3753 * high level. s=0x3C: set this port always low level. 3754 */ 3755 #define GPIO_FUNC68_IN_SEL 0x0000003FU 3756 #define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) 3757 #define GPIO_FUNC68_IN_SEL_V 0x0000003FU 3758 #define GPIO_FUNC68_IN_SEL_S 0 3759 /** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3760 * set this bit to invert input signal. 1:invert. 0:not invert. 3761 */ 3762 #define GPIO_FUNC68_IN_INV_SEL (BIT(6)) 3763 #define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) 3764 #define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U 3765 #define GPIO_FUNC68_IN_INV_SEL_S 6 3766 /** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; 3767 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3768 */ 3769 #define GPIO_SIG68_IN_SEL (BIT(7)) 3770 #define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) 3771 #define GPIO_SIG68_IN_SEL_V 0x00000001U 3772 #define GPIO_SIG68_IN_SEL_S 7 3773 3774 /** GPIO_FUNC69_IN_SEL_CFG_REG register 3775 * GPIO input function configuration register 3776 */ 3777 #define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) 3778 /** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3779 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3780 * high level. s=0x3C: set this port always low level. 3781 */ 3782 #define GPIO_FUNC69_IN_SEL 0x0000003FU 3783 #define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) 3784 #define GPIO_FUNC69_IN_SEL_V 0x0000003FU 3785 #define GPIO_FUNC69_IN_SEL_S 0 3786 /** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3787 * set this bit to invert input signal. 1:invert. 0:not invert. 3788 */ 3789 #define GPIO_FUNC69_IN_INV_SEL (BIT(6)) 3790 #define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) 3791 #define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U 3792 #define GPIO_FUNC69_IN_INV_SEL_S 6 3793 /** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; 3794 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3795 */ 3796 #define GPIO_SIG69_IN_SEL (BIT(7)) 3797 #define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) 3798 #define GPIO_SIG69_IN_SEL_V 0x00000001U 3799 #define GPIO_SIG69_IN_SEL_S 7 3800 3801 /** GPIO_FUNC70_IN_SEL_CFG_REG register 3802 * GPIO input function configuration register 3803 */ 3804 #define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) 3805 /** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3806 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3807 * high level. s=0x3C: set this port always low level. 3808 */ 3809 #define GPIO_FUNC70_IN_SEL 0x0000003FU 3810 #define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) 3811 #define GPIO_FUNC70_IN_SEL_V 0x0000003FU 3812 #define GPIO_FUNC70_IN_SEL_S 0 3813 /** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3814 * set this bit to invert input signal. 1:invert. 0:not invert. 3815 */ 3816 #define GPIO_FUNC70_IN_INV_SEL (BIT(6)) 3817 #define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) 3818 #define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U 3819 #define GPIO_FUNC70_IN_INV_SEL_S 6 3820 /** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; 3821 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3822 */ 3823 #define GPIO_SIG70_IN_SEL (BIT(7)) 3824 #define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) 3825 #define GPIO_SIG70_IN_SEL_V 0x00000001U 3826 #define GPIO_SIG70_IN_SEL_S 7 3827 3828 /** GPIO_FUNC71_IN_SEL_CFG_REG register 3829 * GPIO input function configuration register 3830 */ 3831 #define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) 3832 /** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3833 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3834 * high level. s=0x3C: set this port always low level. 3835 */ 3836 #define GPIO_FUNC71_IN_SEL 0x0000003FU 3837 #define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) 3838 #define GPIO_FUNC71_IN_SEL_V 0x0000003FU 3839 #define GPIO_FUNC71_IN_SEL_S 0 3840 /** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3841 * set this bit to invert input signal. 1:invert. 0:not invert. 3842 */ 3843 #define GPIO_FUNC71_IN_INV_SEL (BIT(6)) 3844 #define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) 3845 #define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U 3846 #define GPIO_FUNC71_IN_INV_SEL_S 6 3847 /** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; 3848 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3849 */ 3850 #define GPIO_SIG71_IN_SEL (BIT(7)) 3851 #define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) 3852 #define GPIO_SIG71_IN_SEL_V 0x00000001U 3853 #define GPIO_SIG71_IN_SEL_S 7 3854 3855 /** GPIO_FUNC72_IN_SEL_CFG_REG register 3856 * GPIO input function configuration register 3857 */ 3858 #define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) 3859 /** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3860 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3861 * high level. s=0x3C: set this port always low level. 3862 */ 3863 #define GPIO_FUNC72_IN_SEL 0x0000003FU 3864 #define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) 3865 #define GPIO_FUNC72_IN_SEL_V 0x0000003FU 3866 #define GPIO_FUNC72_IN_SEL_S 0 3867 /** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3868 * set this bit to invert input signal. 1:invert. 0:not invert. 3869 */ 3870 #define GPIO_FUNC72_IN_INV_SEL (BIT(6)) 3871 #define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) 3872 #define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U 3873 #define GPIO_FUNC72_IN_INV_SEL_S 6 3874 /** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; 3875 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3876 */ 3877 #define GPIO_SIG72_IN_SEL (BIT(7)) 3878 #define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) 3879 #define GPIO_SIG72_IN_SEL_V 0x00000001U 3880 #define GPIO_SIG72_IN_SEL_S 7 3881 3882 /** GPIO_FUNC73_IN_SEL_CFG_REG register 3883 * GPIO input function configuration register 3884 */ 3885 #define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) 3886 /** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 56; 3887 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3888 * high level. s=0x3C: set this port always low level. 3889 */ 3890 #define GPIO_FUNC73_IN_SEL 0x0000003FU 3891 #define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) 3892 #define GPIO_FUNC73_IN_SEL_V 0x0000003FU 3893 #define GPIO_FUNC73_IN_SEL_S 0 3894 /** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3895 * set this bit to invert input signal. 1:invert. 0:not invert. 3896 */ 3897 #define GPIO_FUNC73_IN_INV_SEL (BIT(6)) 3898 #define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) 3899 #define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U 3900 #define GPIO_FUNC73_IN_INV_SEL_S 6 3901 /** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; 3902 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3903 */ 3904 #define GPIO_SIG73_IN_SEL (BIT(7)) 3905 #define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) 3906 #define GPIO_SIG73_IN_SEL_V 0x00000001U 3907 #define GPIO_SIG73_IN_SEL_S 7 3908 3909 /** GPIO_FUNC77_IN_SEL_CFG_REG register 3910 * GPIO input function configuration register 3911 */ 3912 #define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) 3913 /** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 56; 3914 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3915 * high level. s=0x3C: set this port always low level. 3916 */ 3917 #define GPIO_FUNC77_IN_SEL 0x0000003FU 3918 #define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) 3919 #define GPIO_FUNC77_IN_SEL_V 0x0000003FU 3920 #define GPIO_FUNC77_IN_SEL_S 0 3921 /** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3922 * set this bit to invert input signal. 1:invert. 0:not invert. 3923 */ 3924 #define GPIO_FUNC77_IN_INV_SEL (BIT(6)) 3925 #define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) 3926 #define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U 3927 #define GPIO_FUNC77_IN_INV_SEL_S 6 3928 /** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; 3929 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3930 */ 3931 #define GPIO_SIG77_IN_SEL (BIT(7)) 3932 #define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) 3933 #define GPIO_SIG77_IN_SEL_V 0x00000001U 3934 #define GPIO_SIG77_IN_SEL_S 7 3935 3936 /** GPIO_FUNC81_IN_SEL_CFG_REG register 3937 * GPIO input function configuration register 3938 */ 3939 #define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) 3940 /** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3941 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3942 * high level. s=0x3C: set this port always low level. 3943 */ 3944 #define GPIO_FUNC81_IN_SEL 0x0000003FU 3945 #define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) 3946 #define GPIO_FUNC81_IN_SEL_V 0x0000003FU 3947 #define GPIO_FUNC81_IN_SEL_S 0 3948 /** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3949 * set this bit to invert input signal. 1:invert. 0:not invert. 3950 */ 3951 #define GPIO_FUNC81_IN_INV_SEL (BIT(6)) 3952 #define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) 3953 #define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U 3954 #define GPIO_FUNC81_IN_INV_SEL_S 6 3955 /** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; 3956 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3957 */ 3958 #define GPIO_SIG81_IN_SEL (BIT(7)) 3959 #define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) 3960 #define GPIO_SIG81_IN_SEL_V 0x00000001U 3961 #define GPIO_SIG81_IN_SEL_S 7 3962 3963 /** GPIO_FUNC82_IN_SEL_CFG_REG register 3964 * GPIO input function configuration register 3965 */ 3966 #define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) 3967 /** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3968 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3969 * high level. s=0x3C: set this port always low level. 3970 */ 3971 #define GPIO_FUNC82_IN_SEL 0x0000003FU 3972 #define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) 3973 #define GPIO_FUNC82_IN_SEL_V 0x0000003FU 3974 #define GPIO_FUNC82_IN_SEL_S 0 3975 /** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 3976 * set this bit to invert input signal. 1:invert. 0:not invert. 3977 */ 3978 #define GPIO_FUNC82_IN_INV_SEL (BIT(6)) 3979 #define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) 3980 #define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U 3981 #define GPIO_FUNC82_IN_INV_SEL_S 6 3982 /** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; 3983 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 3984 */ 3985 #define GPIO_SIG82_IN_SEL (BIT(7)) 3986 #define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) 3987 #define GPIO_SIG82_IN_SEL_V 0x00000001U 3988 #define GPIO_SIG82_IN_SEL_S 7 3989 3990 /** GPIO_FUNC87_IN_SEL_CFG_REG register 3991 * GPIO input function configuration register 3992 */ 3993 #define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) 3994 /** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 60; 3995 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 3996 * high level. s=0x3C: set this port always low level. 3997 */ 3998 #define GPIO_FUNC87_IN_SEL 0x0000003FU 3999 #define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) 4000 #define GPIO_FUNC87_IN_SEL_V 0x0000003FU 4001 #define GPIO_FUNC87_IN_SEL_S 0 4002 /** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4003 * set this bit to invert input signal. 1:invert. 0:not invert. 4004 */ 4005 #define GPIO_FUNC87_IN_INV_SEL (BIT(6)) 4006 #define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) 4007 #define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U 4008 #define GPIO_FUNC87_IN_INV_SEL_S 6 4009 /** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; 4010 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4011 */ 4012 #define GPIO_SIG87_IN_SEL (BIT(7)) 4013 #define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) 4014 #define GPIO_SIG87_IN_SEL_V 0x00000001U 4015 #define GPIO_SIG87_IN_SEL_S 7 4016 4017 /** GPIO_FUNC88_IN_SEL_CFG_REG register 4018 * GPIO input function configuration register 4019 */ 4020 #define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) 4021 /** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4022 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4023 * high level. s=0x3C: set this port always low level. 4024 */ 4025 #define GPIO_FUNC88_IN_SEL 0x0000003FU 4026 #define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) 4027 #define GPIO_FUNC88_IN_SEL_V 0x0000003FU 4028 #define GPIO_FUNC88_IN_SEL_S 0 4029 /** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4030 * set this bit to invert input signal. 1:invert. 0:not invert. 4031 */ 4032 #define GPIO_FUNC88_IN_INV_SEL (BIT(6)) 4033 #define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) 4034 #define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U 4035 #define GPIO_FUNC88_IN_INV_SEL_S 6 4036 /** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; 4037 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4038 */ 4039 #define GPIO_SIG88_IN_SEL (BIT(7)) 4040 #define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) 4041 #define GPIO_SIG88_IN_SEL_V 0x00000001U 4042 #define GPIO_SIG88_IN_SEL_S 7 4043 4044 /** GPIO_FUNC89_IN_SEL_CFG_REG register 4045 * GPIO input function configuration register 4046 */ 4047 #define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) 4048 /** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4049 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4050 * high level. s=0x3C: set this port always low level. 4051 */ 4052 #define GPIO_FUNC89_IN_SEL 0x0000003FU 4053 #define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) 4054 #define GPIO_FUNC89_IN_SEL_V 0x0000003FU 4055 #define GPIO_FUNC89_IN_SEL_S 0 4056 /** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4057 * set this bit to invert input signal. 1:invert. 0:not invert. 4058 */ 4059 #define GPIO_FUNC89_IN_INV_SEL (BIT(6)) 4060 #define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) 4061 #define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U 4062 #define GPIO_FUNC89_IN_INV_SEL_S 6 4063 /** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; 4064 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4065 */ 4066 #define GPIO_SIG89_IN_SEL (BIT(7)) 4067 #define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) 4068 #define GPIO_SIG89_IN_SEL_V 0x00000001U 4069 #define GPIO_SIG89_IN_SEL_S 7 4070 4071 /** GPIO_FUNC90_IN_SEL_CFG_REG register 4072 * GPIO input function configuration register 4073 */ 4074 #define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) 4075 /** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4076 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4077 * high level. s=0x3C: set this port always low level. 4078 */ 4079 #define GPIO_FUNC90_IN_SEL 0x0000003FU 4080 #define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) 4081 #define GPIO_FUNC90_IN_SEL_V 0x0000003FU 4082 #define GPIO_FUNC90_IN_SEL_S 0 4083 /** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4084 * set this bit to invert input signal. 1:invert. 0:not invert. 4085 */ 4086 #define GPIO_FUNC90_IN_INV_SEL (BIT(6)) 4087 #define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) 4088 #define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U 4089 #define GPIO_FUNC90_IN_INV_SEL_S 6 4090 /** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; 4091 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4092 */ 4093 #define GPIO_SIG90_IN_SEL (BIT(7)) 4094 #define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) 4095 #define GPIO_SIG90_IN_SEL_V 0x00000001U 4096 #define GPIO_SIG90_IN_SEL_S 7 4097 4098 /** GPIO_FUNC91_IN_SEL_CFG_REG register 4099 * GPIO input function configuration register 4100 */ 4101 #define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) 4102 /** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4103 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4104 * high level. s=0x3C: set this port always low level. 4105 */ 4106 #define GPIO_FUNC91_IN_SEL 0x0000003FU 4107 #define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) 4108 #define GPIO_FUNC91_IN_SEL_V 0x0000003FU 4109 #define GPIO_FUNC91_IN_SEL_S 0 4110 /** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4111 * set this bit to invert input signal. 1:invert. 0:not invert. 4112 */ 4113 #define GPIO_FUNC91_IN_INV_SEL (BIT(6)) 4114 #define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) 4115 #define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U 4116 #define GPIO_FUNC91_IN_INV_SEL_S 6 4117 /** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; 4118 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4119 */ 4120 #define GPIO_SIG91_IN_SEL (BIT(7)) 4121 #define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) 4122 #define GPIO_SIG91_IN_SEL_V 0x00000001U 4123 #define GPIO_SIG91_IN_SEL_S 7 4124 4125 /** GPIO_FUNC92_IN_SEL_CFG_REG register 4126 * GPIO input function configuration register 4127 */ 4128 #define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) 4129 /** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4130 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4131 * high level. s=0x3C: set this port always low level. 4132 */ 4133 #define GPIO_FUNC92_IN_SEL 0x0000003FU 4134 #define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) 4135 #define GPIO_FUNC92_IN_SEL_V 0x0000003FU 4136 #define GPIO_FUNC92_IN_SEL_S 0 4137 /** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4138 * set this bit to invert input signal. 1:invert. 0:not invert. 4139 */ 4140 #define GPIO_FUNC92_IN_INV_SEL (BIT(6)) 4141 #define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) 4142 #define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U 4143 #define GPIO_FUNC92_IN_INV_SEL_S 6 4144 /** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; 4145 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4146 */ 4147 #define GPIO_SIG92_IN_SEL (BIT(7)) 4148 #define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) 4149 #define GPIO_SIG92_IN_SEL_V 0x00000001U 4150 #define GPIO_SIG92_IN_SEL_S 7 4151 4152 /** GPIO_FUNC93_IN_SEL_CFG_REG register 4153 * GPIO input function configuration register 4154 */ 4155 #define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) 4156 /** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4157 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4158 * high level. s=0x3C: set this port always low level. 4159 */ 4160 #define GPIO_FUNC93_IN_SEL 0x0000003FU 4161 #define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) 4162 #define GPIO_FUNC93_IN_SEL_V 0x0000003FU 4163 #define GPIO_FUNC93_IN_SEL_S 0 4164 /** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4165 * set this bit to invert input signal. 1:invert. 0:not invert. 4166 */ 4167 #define GPIO_FUNC93_IN_INV_SEL (BIT(6)) 4168 #define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) 4169 #define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U 4170 #define GPIO_FUNC93_IN_INV_SEL_S 6 4171 /** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; 4172 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4173 */ 4174 #define GPIO_SIG93_IN_SEL (BIT(7)) 4175 #define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) 4176 #define GPIO_SIG93_IN_SEL_V 0x00000001U 4177 #define GPIO_SIG93_IN_SEL_S 7 4178 4179 /** GPIO_FUNC94_IN_SEL_CFG_REG register 4180 * GPIO input function configuration register 4181 */ 4182 #define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) 4183 /** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4184 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4185 * high level. s=0x3C: set this port always low level. 4186 */ 4187 #define GPIO_FUNC94_IN_SEL 0x0000003FU 4188 #define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) 4189 #define GPIO_FUNC94_IN_SEL_V 0x0000003FU 4190 #define GPIO_FUNC94_IN_SEL_S 0 4191 /** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4192 * set this bit to invert input signal. 1:invert. 0:not invert. 4193 */ 4194 #define GPIO_FUNC94_IN_INV_SEL (BIT(6)) 4195 #define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) 4196 #define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U 4197 #define GPIO_FUNC94_IN_INV_SEL_S 6 4198 /** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; 4199 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4200 */ 4201 #define GPIO_SIG94_IN_SEL (BIT(7)) 4202 #define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) 4203 #define GPIO_SIG94_IN_SEL_V 0x00000001U 4204 #define GPIO_SIG94_IN_SEL_S 7 4205 4206 /** GPIO_FUNC95_IN_SEL_CFG_REG register 4207 * GPIO input function configuration register 4208 */ 4209 #define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) 4210 /** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4211 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4212 * high level. s=0x3C: set this port always low level. 4213 */ 4214 #define GPIO_FUNC95_IN_SEL 0x0000003FU 4215 #define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) 4216 #define GPIO_FUNC95_IN_SEL_V 0x0000003FU 4217 #define GPIO_FUNC95_IN_SEL_S 0 4218 /** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4219 * set this bit to invert input signal. 1:invert. 0:not invert. 4220 */ 4221 #define GPIO_FUNC95_IN_INV_SEL (BIT(6)) 4222 #define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) 4223 #define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U 4224 #define GPIO_FUNC95_IN_INV_SEL_S 6 4225 /** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; 4226 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4227 */ 4228 #define GPIO_SIG95_IN_SEL (BIT(7)) 4229 #define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) 4230 #define GPIO_SIG95_IN_SEL_V 0x00000001U 4231 #define GPIO_SIG95_IN_SEL_S 7 4232 4233 /** GPIO_FUNC97_IN_SEL_CFG_REG register 4234 * GPIO input function configuration register 4235 */ 4236 #define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) 4237 /** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4238 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4239 * high level. s=0x3C: set this port always low level. 4240 */ 4241 #define GPIO_FUNC97_IN_SEL 0x0000003FU 4242 #define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) 4243 #define GPIO_FUNC97_IN_SEL_V 0x0000003FU 4244 #define GPIO_FUNC97_IN_SEL_S 0 4245 /** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4246 * set this bit to invert input signal. 1:invert. 0:not invert. 4247 */ 4248 #define GPIO_FUNC97_IN_INV_SEL (BIT(6)) 4249 #define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) 4250 #define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U 4251 #define GPIO_FUNC97_IN_INV_SEL_S 6 4252 /** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; 4253 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4254 */ 4255 #define GPIO_SIG97_IN_SEL (BIT(7)) 4256 #define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) 4257 #define GPIO_SIG97_IN_SEL_V 0x00000001U 4258 #define GPIO_SIG97_IN_SEL_S 7 4259 4260 /** GPIO_FUNC98_IN_SEL_CFG_REG register 4261 * GPIO input function configuration register 4262 */ 4263 #define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) 4264 /** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4265 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4266 * high level. s=0x3C: set this port always low level. 4267 */ 4268 #define GPIO_FUNC98_IN_SEL 0x0000003FU 4269 #define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) 4270 #define GPIO_FUNC98_IN_SEL_V 0x0000003FU 4271 #define GPIO_FUNC98_IN_SEL_S 0 4272 /** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4273 * set this bit to invert input signal. 1:invert. 0:not invert. 4274 */ 4275 #define GPIO_FUNC98_IN_INV_SEL (BIT(6)) 4276 #define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) 4277 #define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U 4278 #define GPIO_FUNC98_IN_INV_SEL_S 6 4279 /** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; 4280 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4281 */ 4282 #define GPIO_SIG98_IN_SEL (BIT(7)) 4283 #define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) 4284 #define GPIO_SIG98_IN_SEL_V 0x00000001U 4285 #define GPIO_SIG98_IN_SEL_S 7 4286 4287 /** GPIO_FUNC99_IN_SEL_CFG_REG register 4288 * GPIO input function configuration register 4289 */ 4290 #define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) 4291 /** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4292 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4293 * high level. s=0x3C: set this port always low level. 4294 */ 4295 #define GPIO_FUNC99_IN_SEL 0x0000003FU 4296 #define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) 4297 #define GPIO_FUNC99_IN_SEL_V 0x0000003FU 4298 #define GPIO_FUNC99_IN_SEL_S 0 4299 /** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4300 * set this bit to invert input signal. 1:invert. 0:not invert. 4301 */ 4302 #define GPIO_FUNC99_IN_INV_SEL (BIT(6)) 4303 #define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) 4304 #define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U 4305 #define GPIO_FUNC99_IN_INV_SEL_S 6 4306 /** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; 4307 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4308 */ 4309 #define GPIO_SIG99_IN_SEL (BIT(7)) 4310 #define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) 4311 #define GPIO_SIG99_IN_SEL_V 0x00000001U 4312 #define GPIO_SIG99_IN_SEL_S 7 4313 4314 /** GPIO_FUNC100_IN_SEL_CFG_REG register 4315 * GPIO input function configuration register 4316 */ 4317 #define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) 4318 /** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4319 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4320 * high level. s=0x3C: set this port always low level. 4321 */ 4322 #define GPIO_FUNC100_IN_SEL 0x0000003FU 4323 #define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) 4324 #define GPIO_FUNC100_IN_SEL_V 0x0000003FU 4325 #define GPIO_FUNC100_IN_SEL_S 0 4326 /** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4327 * set this bit to invert input signal. 1:invert. 0:not invert. 4328 */ 4329 #define GPIO_FUNC100_IN_INV_SEL (BIT(6)) 4330 #define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) 4331 #define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U 4332 #define GPIO_FUNC100_IN_INV_SEL_S 6 4333 /** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; 4334 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4335 */ 4336 #define GPIO_SIG100_IN_SEL (BIT(7)) 4337 #define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) 4338 #define GPIO_SIG100_IN_SEL_V 0x00000001U 4339 #define GPIO_SIG100_IN_SEL_S 7 4340 4341 /** GPIO_FUNC101_IN_SEL_CFG_REG register 4342 * GPIO input function configuration register 4343 */ 4344 #define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) 4345 /** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4346 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4347 * high level. s=0x3C: set this port always low level. 4348 */ 4349 #define GPIO_FUNC101_IN_SEL 0x0000003FU 4350 #define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) 4351 #define GPIO_FUNC101_IN_SEL_V 0x0000003FU 4352 #define GPIO_FUNC101_IN_SEL_S 0 4353 /** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4354 * set this bit to invert input signal. 1:invert. 0:not invert. 4355 */ 4356 #define GPIO_FUNC101_IN_INV_SEL (BIT(6)) 4357 #define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) 4358 #define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U 4359 #define GPIO_FUNC101_IN_INV_SEL_S 6 4360 /** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; 4361 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4362 */ 4363 #define GPIO_SIG101_IN_SEL (BIT(7)) 4364 #define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) 4365 #define GPIO_SIG101_IN_SEL_V 0x00000001U 4366 #define GPIO_SIG101_IN_SEL_S 7 4367 4368 /** GPIO_FUNC102_IN_SEL_CFG_REG register 4369 * GPIO input function configuration register 4370 */ 4371 #define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) 4372 /** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4373 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4374 * high level. s=0x3C: set this port always low level. 4375 */ 4376 #define GPIO_FUNC102_IN_SEL 0x0000003FU 4377 #define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) 4378 #define GPIO_FUNC102_IN_SEL_V 0x0000003FU 4379 #define GPIO_FUNC102_IN_SEL_S 0 4380 /** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4381 * set this bit to invert input signal. 1:invert. 0:not invert. 4382 */ 4383 #define GPIO_FUNC102_IN_INV_SEL (BIT(6)) 4384 #define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) 4385 #define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U 4386 #define GPIO_FUNC102_IN_INV_SEL_S 6 4387 /** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; 4388 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4389 */ 4390 #define GPIO_SIG102_IN_SEL (BIT(7)) 4391 #define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) 4392 #define GPIO_SIG102_IN_SEL_V 0x00000001U 4393 #define GPIO_SIG102_IN_SEL_S 7 4394 4395 /** GPIO_FUNC103_IN_SEL_CFG_REG register 4396 * GPIO input function configuration register 4397 */ 4398 #define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) 4399 /** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4400 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4401 * high level. s=0x3C: set this port always low level. 4402 */ 4403 #define GPIO_FUNC103_IN_SEL 0x0000003FU 4404 #define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) 4405 #define GPIO_FUNC103_IN_SEL_V 0x0000003FU 4406 #define GPIO_FUNC103_IN_SEL_S 0 4407 /** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4408 * set this bit to invert input signal. 1:invert. 0:not invert. 4409 */ 4410 #define GPIO_FUNC103_IN_INV_SEL (BIT(6)) 4411 #define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) 4412 #define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U 4413 #define GPIO_FUNC103_IN_INV_SEL_S 6 4414 /** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; 4415 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4416 */ 4417 #define GPIO_SIG103_IN_SEL (BIT(7)) 4418 #define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) 4419 #define GPIO_SIG103_IN_SEL_V 0x00000001U 4420 #define GPIO_SIG103_IN_SEL_S 7 4421 4422 /** GPIO_FUNC104_IN_SEL_CFG_REG register 4423 * GPIO input function configuration register 4424 */ 4425 #define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) 4426 /** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4427 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4428 * high level. s=0x3C: set this port always low level. 4429 */ 4430 #define GPIO_FUNC104_IN_SEL 0x0000003FU 4431 #define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) 4432 #define GPIO_FUNC104_IN_SEL_V 0x0000003FU 4433 #define GPIO_FUNC104_IN_SEL_S 0 4434 /** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4435 * set this bit to invert input signal. 1:invert. 0:not invert. 4436 */ 4437 #define GPIO_FUNC104_IN_INV_SEL (BIT(6)) 4438 #define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) 4439 #define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U 4440 #define GPIO_FUNC104_IN_INV_SEL_S 6 4441 /** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; 4442 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4443 */ 4444 #define GPIO_SIG104_IN_SEL (BIT(7)) 4445 #define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) 4446 #define GPIO_SIG104_IN_SEL_V 0x00000001U 4447 #define GPIO_SIG104_IN_SEL_S 7 4448 4449 /** GPIO_FUNC105_IN_SEL_CFG_REG register 4450 * GPIO input function configuration register 4451 */ 4452 #define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) 4453 /** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4454 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4455 * high level. s=0x3C: set this port always low level. 4456 */ 4457 #define GPIO_FUNC105_IN_SEL 0x0000003FU 4458 #define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) 4459 #define GPIO_FUNC105_IN_SEL_V 0x0000003FU 4460 #define GPIO_FUNC105_IN_SEL_S 0 4461 /** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4462 * set this bit to invert input signal. 1:invert. 0:not invert. 4463 */ 4464 #define GPIO_FUNC105_IN_INV_SEL (BIT(6)) 4465 #define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) 4466 #define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U 4467 #define GPIO_FUNC105_IN_INV_SEL_S 6 4468 /** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; 4469 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4470 */ 4471 #define GPIO_SIG105_IN_SEL (BIT(7)) 4472 #define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) 4473 #define GPIO_SIG105_IN_SEL_V 0x00000001U 4474 #define GPIO_SIG105_IN_SEL_S 7 4475 4476 /** GPIO_FUNC106_IN_SEL_CFG_REG register 4477 * GPIO input function configuration register 4478 */ 4479 #define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) 4480 /** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4481 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4482 * high level. s=0x3C: set this port always low level. 4483 */ 4484 #define GPIO_FUNC106_IN_SEL 0x0000003FU 4485 #define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) 4486 #define GPIO_FUNC106_IN_SEL_V 0x0000003FU 4487 #define GPIO_FUNC106_IN_SEL_S 0 4488 /** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4489 * set this bit to invert input signal. 1:invert. 0:not invert. 4490 */ 4491 #define GPIO_FUNC106_IN_INV_SEL (BIT(6)) 4492 #define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) 4493 #define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U 4494 #define GPIO_FUNC106_IN_INV_SEL_S 6 4495 /** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; 4496 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4497 */ 4498 #define GPIO_SIG106_IN_SEL (BIT(7)) 4499 #define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) 4500 #define GPIO_SIG106_IN_SEL_V 0x00000001U 4501 #define GPIO_SIG106_IN_SEL_S 7 4502 4503 /** GPIO_FUNC107_IN_SEL_CFG_REG register 4504 * GPIO input function configuration register 4505 */ 4506 #define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) 4507 /** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4508 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4509 * high level. s=0x3C: set this port always low level. 4510 */ 4511 #define GPIO_FUNC107_IN_SEL 0x0000003FU 4512 #define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) 4513 #define GPIO_FUNC107_IN_SEL_V 0x0000003FU 4514 #define GPIO_FUNC107_IN_SEL_S 0 4515 /** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4516 * set this bit to invert input signal. 1:invert. 0:not invert. 4517 */ 4518 #define GPIO_FUNC107_IN_INV_SEL (BIT(6)) 4519 #define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) 4520 #define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U 4521 #define GPIO_FUNC107_IN_INV_SEL_S 6 4522 /** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; 4523 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4524 */ 4525 #define GPIO_SIG107_IN_SEL (BIT(7)) 4526 #define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) 4527 #define GPIO_SIG107_IN_SEL_V 0x00000001U 4528 #define GPIO_SIG107_IN_SEL_S 7 4529 4530 /** GPIO_FUNC108_IN_SEL_CFG_REG register 4531 * GPIO input function configuration register 4532 */ 4533 #define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) 4534 /** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4535 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4536 * high level. s=0x3C: set this port always low level. 4537 */ 4538 #define GPIO_FUNC108_IN_SEL 0x0000003FU 4539 #define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) 4540 #define GPIO_FUNC108_IN_SEL_V 0x0000003FU 4541 #define GPIO_FUNC108_IN_SEL_S 0 4542 /** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4543 * set this bit to invert input signal. 1:invert. 0:not invert. 4544 */ 4545 #define GPIO_FUNC108_IN_INV_SEL (BIT(6)) 4546 #define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) 4547 #define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U 4548 #define GPIO_FUNC108_IN_INV_SEL_S 6 4549 /** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; 4550 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4551 */ 4552 #define GPIO_SIG108_IN_SEL (BIT(7)) 4553 #define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) 4554 #define GPIO_SIG108_IN_SEL_V 0x00000001U 4555 #define GPIO_SIG108_IN_SEL_S 7 4556 4557 /** GPIO_FUNC109_IN_SEL_CFG_REG register 4558 * GPIO input function configuration register 4559 */ 4560 #define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) 4561 /** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4562 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4563 * high level. s=0x3C: set this port always low level. 4564 */ 4565 #define GPIO_FUNC109_IN_SEL 0x0000003FU 4566 #define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) 4567 #define GPIO_FUNC109_IN_SEL_V 0x0000003FU 4568 #define GPIO_FUNC109_IN_SEL_S 0 4569 /** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4570 * set this bit to invert input signal. 1:invert. 0:not invert. 4571 */ 4572 #define GPIO_FUNC109_IN_INV_SEL (BIT(6)) 4573 #define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) 4574 #define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U 4575 #define GPIO_FUNC109_IN_INV_SEL_S 6 4576 /** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; 4577 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4578 */ 4579 #define GPIO_SIG109_IN_SEL (BIT(7)) 4580 #define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) 4581 #define GPIO_SIG109_IN_SEL_V 0x00000001U 4582 #define GPIO_SIG109_IN_SEL_S 7 4583 4584 /** GPIO_FUNC110_IN_SEL_CFG_REG register 4585 * GPIO input function configuration register 4586 */ 4587 #define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) 4588 /** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4589 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4590 * high level. s=0x3C: set this port always low level. 4591 */ 4592 #define GPIO_FUNC110_IN_SEL 0x0000003FU 4593 #define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) 4594 #define GPIO_FUNC110_IN_SEL_V 0x0000003FU 4595 #define GPIO_FUNC110_IN_SEL_S 0 4596 /** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4597 * set this bit to invert input signal. 1:invert. 0:not invert. 4598 */ 4599 #define GPIO_FUNC110_IN_INV_SEL (BIT(6)) 4600 #define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) 4601 #define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U 4602 #define GPIO_FUNC110_IN_INV_SEL_S 6 4603 /** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; 4604 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4605 */ 4606 #define GPIO_SIG110_IN_SEL (BIT(7)) 4607 #define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) 4608 #define GPIO_SIG110_IN_SEL_V 0x00000001U 4609 #define GPIO_SIG110_IN_SEL_S 7 4610 4611 /** GPIO_FUNC111_IN_SEL_CFG_REG register 4612 * GPIO input function configuration register 4613 */ 4614 #define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) 4615 /** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4616 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4617 * high level. s=0x3C: set this port always low level. 4618 */ 4619 #define GPIO_FUNC111_IN_SEL 0x0000003FU 4620 #define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) 4621 #define GPIO_FUNC111_IN_SEL_V 0x0000003FU 4622 #define GPIO_FUNC111_IN_SEL_S 0 4623 /** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4624 * set this bit to invert input signal. 1:invert. 0:not invert. 4625 */ 4626 #define GPIO_FUNC111_IN_INV_SEL (BIT(6)) 4627 #define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) 4628 #define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U 4629 #define GPIO_FUNC111_IN_INV_SEL_S 6 4630 /** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; 4631 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4632 */ 4633 #define GPIO_SIG111_IN_SEL (BIT(7)) 4634 #define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) 4635 #define GPIO_SIG111_IN_SEL_V 0x00000001U 4636 #define GPIO_SIG111_IN_SEL_S 7 4637 4638 /** GPIO_FUNC112_IN_SEL_CFG_REG register 4639 * GPIO input function configuration register 4640 */ 4641 #define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) 4642 /** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4643 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4644 * high level. s=0x3C: set this port always low level. 4645 */ 4646 #define GPIO_FUNC112_IN_SEL 0x0000003FU 4647 #define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) 4648 #define GPIO_FUNC112_IN_SEL_V 0x0000003FU 4649 #define GPIO_FUNC112_IN_SEL_S 0 4650 /** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4651 * set this bit to invert input signal. 1:invert. 0:not invert. 4652 */ 4653 #define GPIO_FUNC112_IN_INV_SEL (BIT(6)) 4654 #define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) 4655 #define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U 4656 #define GPIO_FUNC112_IN_INV_SEL_S 6 4657 /** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; 4658 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4659 */ 4660 #define GPIO_SIG112_IN_SEL (BIT(7)) 4661 #define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) 4662 #define GPIO_SIG112_IN_SEL_V 0x00000001U 4663 #define GPIO_SIG112_IN_SEL_S 7 4664 4665 /** GPIO_FUNC113_IN_SEL_CFG_REG register 4666 * GPIO input function configuration register 4667 */ 4668 #define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) 4669 /** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4670 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4671 * high level. s=0x3C: set this port always low level. 4672 */ 4673 #define GPIO_FUNC113_IN_SEL 0x0000003FU 4674 #define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) 4675 #define GPIO_FUNC113_IN_SEL_V 0x0000003FU 4676 #define GPIO_FUNC113_IN_SEL_S 0 4677 /** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4678 * set this bit to invert input signal. 1:invert. 0:not invert. 4679 */ 4680 #define GPIO_FUNC113_IN_INV_SEL (BIT(6)) 4681 #define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) 4682 #define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U 4683 #define GPIO_FUNC113_IN_INV_SEL_S 6 4684 /** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; 4685 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4686 */ 4687 #define GPIO_SIG113_IN_SEL (BIT(7)) 4688 #define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) 4689 #define GPIO_SIG113_IN_SEL_V 0x00000001U 4690 #define GPIO_SIG113_IN_SEL_S 7 4691 4692 /** GPIO_FUNC114_IN_SEL_CFG_REG register 4693 * GPIO input function configuration register 4694 */ 4695 #define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) 4696 /** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4697 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4698 * high level. s=0x3C: set this port always low level. 4699 */ 4700 #define GPIO_FUNC114_IN_SEL 0x0000003FU 4701 #define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) 4702 #define GPIO_FUNC114_IN_SEL_V 0x0000003FU 4703 #define GPIO_FUNC114_IN_SEL_S 0 4704 /** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4705 * set this bit to invert input signal. 1:invert. 0:not invert. 4706 */ 4707 #define GPIO_FUNC114_IN_INV_SEL (BIT(6)) 4708 #define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) 4709 #define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U 4710 #define GPIO_FUNC114_IN_INV_SEL_S 6 4711 /** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; 4712 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4713 */ 4714 #define GPIO_SIG114_IN_SEL (BIT(7)) 4715 #define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) 4716 #define GPIO_SIG114_IN_SEL_V 0x00000001U 4717 #define GPIO_SIG114_IN_SEL_S 7 4718 4719 /** GPIO_FUNC115_IN_SEL_CFG_REG register 4720 * GPIO input function configuration register 4721 */ 4722 #define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) 4723 /** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4724 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4725 * high level. s=0x3C: set this port always low level. 4726 */ 4727 #define GPIO_FUNC115_IN_SEL 0x0000003FU 4728 #define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) 4729 #define GPIO_FUNC115_IN_SEL_V 0x0000003FU 4730 #define GPIO_FUNC115_IN_SEL_S 0 4731 /** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4732 * set this bit to invert input signal. 1:invert. 0:not invert. 4733 */ 4734 #define GPIO_FUNC115_IN_INV_SEL (BIT(6)) 4735 #define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) 4736 #define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U 4737 #define GPIO_FUNC115_IN_INV_SEL_S 6 4738 /** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; 4739 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4740 */ 4741 #define GPIO_SIG115_IN_SEL (BIT(7)) 4742 #define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) 4743 #define GPIO_SIG115_IN_SEL_V 0x00000001U 4744 #define GPIO_SIG115_IN_SEL_S 7 4745 4746 /** GPIO_FUNC116_IN_SEL_CFG_REG register 4747 * GPIO input function configuration register 4748 */ 4749 #define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) 4750 /** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4751 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4752 * high level. s=0x3C: set this port always low level. 4753 */ 4754 #define GPIO_FUNC116_IN_SEL 0x0000003FU 4755 #define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) 4756 #define GPIO_FUNC116_IN_SEL_V 0x0000003FU 4757 #define GPIO_FUNC116_IN_SEL_S 0 4758 /** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4759 * set this bit to invert input signal. 1:invert. 0:not invert. 4760 */ 4761 #define GPIO_FUNC116_IN_INV_SEL (BIT(6)) 4762 #define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) 4763 #define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U 4764 #define GPIO_FUNC116_IN_INV_SEL_S 6 4765 /** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; 4766 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4767 */ 4768 #define GPIO_SIG116_IN_SEL (BIT(7)) 4769 #define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) 4770 #define GPIO_SIG116_IN_SEL_V 0x00000001U 4771 #define GPIO_SIG116_IN_SEL_S 7 4772 4773 /** GPIO_FUNC117_IN_SEL_CFG_REG register 4774 * GPIO input function configuration register 4775 */ 4776 #define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) 4777 /** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4778 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4779 * high level. s=0x3C: set this port always low level. 4780 */ 4781 #define GPIO_FUNC117_IN_SEL 0x0000003FU 4782 #define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) 4783 #define GPIO_FUNC117_IN_SEL_V 0x0000003FU 4784 #define GPIO_FUNC117_IN_SEL_S 0 4785 /** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4786 * set this bit to invert input signal. 1:invert. 0:not invert. 4787 */ 4788 #define GPIO_FUNC117_IN_INV_SEL (BIT(6)) 4789 #define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) 4790 #define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U 4791 #define GPIO_FUNC117_IN_INV_SEL_S 6 4792 /** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; 4793 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4794 */ 4795 #define GPIO_SIG117_IN_SEL (BIT(7)) 4796 #define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) 4797 #define GPIO_SIG117_IN_SEL_V 0x00000001U 4798 #define GPIO_SIG117_IN_SEL_S 7 4799 4800 /** GPIO_FUNC118_IN_SEL_CFG_REG register 4801 * GPIO input function configuration register 4802 */ 4803 #define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) 4804 /** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4805 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4806 * high level. s=0x3C: set this port always low level. 4807 */ 4808 #define GPIO_FUNC118_IN_SEL 0x0000003FU 4809 #define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) 4810 #define GPIO_FUNC118_IN_SEL_V 0x0000003FU 4811 #define GPIO_FUNC118_IN_SEL_S 0 4812 /** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4813 * set this bit to invert input signal. 1:invert. 0:not invert. 4814 */ 4815 #define GPIO_FUNC118_IN_INV_SEL (BIT(6)) 4816 #define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) 4817 #define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U 4818 #define GPIO_FUNC118_IN_INV_SEL_S 6 4819 /** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; 4820 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4821 */ 4822 #define GPIO_SIG118_IN_SEL (BIT(7)) 4823 #define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) 4824 #define GPIO_SIG118_IN_SEL_V 0x00000001U 4825 #define GPIO_SIG118_IN_SEL_S 7 4826 4827 /** GPIO_FUNC119_IN_SEL_CFG_REG register 4828 * GPIO input function configuration register 4829 */ 4830 #define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) 4831 /** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4832 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4833 * high level. s=0x3C: set this port always low level. 4834 */ 4835 #define GPIO_FUNC119_IN_SEL 0x0000003FU 4836 #define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) 4837 #define GPIO_FUNC119_IN_SEL_V 0x0000003FU 4838 #define GPIO_FUNC119_IN_SEL_S 0 4839 /** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4840 * set this bit to invert input signal. 1:invert. 0:not invert. 4841 */ 4842 #define GPIO_FUNC119_IN_INV_SEL (BIT(6)) 4843 #define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) 4844 #define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U 4845 #define GPIO_FUNC119_IN_INV_SEL_S 6 4846 /** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; 4847 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4848 */ 4849 #define GPIO_SIG119_IN_SEL (BIT(7)) 4850 #define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) 4851 #define GPIO_SIG119_IN_SEL_V 0x00000001U 4852 #define GPIO_SIG119_IN_SEL_S 7 4853 4854 /** GPIO_FUNC120_IN_SEL_CFG_REG register 4855 * GPIO input function configuration register 4856 */ 4857 #define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) 4858 /** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4859 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4860 * high level. s=0x3C: set this port always low level. 4861 */ 4862 #define GPIO_FUNC120_IN_SEL 0x0000003FU 4863 #define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) 4864 #define GPIO_FUNC120_IN_SEL_V 0x0000003FU 4865 #define GPIO_FUNC120_IN_SEL_S 0 4866 /** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4867 * set this bit to invert input signal. 1:invert. 0:not invert. 4868 */ 4869 #define GPIO_FUNC120_IN_INV_SEL (BIT(6)) 4870 #define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) 4871 #define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U 4872 #define GPIO_FUNC120_IN_INV_SEL_S 6 4873 /** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; 4874 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4875 */ 4876 #define GPIO_SIG120_IN_SEL (BIT(7)) 4877 #define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) 4878 #define GPIO_SIG120_IN_SEL_V 0x00000001U 4879 #define GPIO_SIG120_IN_SEL_S 7 4880 4881 /** GPIO_FUNC121_IN_SEL_CFG_REG register 4882 * GPIO input function configuration register 4883 */ 4884 #define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) 4885 /** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4886 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4887 * high level. s=0x3C: set this port always low level. 4888 */ 4889 #define GPIO_FUNC121_IN_SEL 0x0000003FU 4890 #define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) 4891 #define GPIO_FUNC121_IN_SEL_V 0x0000003FU 4892 #define GPIO_FUNC121_IN_SEL_S 0 4893 /** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4894 * set this bit to invert input signal. 1:invert. 0:not invert. 4895 */ 4896 #define GPIO_FUNC121_IN_INV_SEL (BIT(6)) 4897 #define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) 4898 #define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U 4899 #define GPIO_FUNC121_IN_INV_SEL_S 6 4900 /** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; 4901 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4902 */ 4903 #define GPIO_SIG121_IN_SEL (BIT(7)) 4904 #define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) 4905 #define GPIO_SIG121_IN_SEL_V 0x00000001U 4906 #define GPIO_SIG121_IN_SEL_S 7 4907 4908 /** GPIO_FUNC122_IN_SEL_CFG_REG register 4909 * GPIO input function configuration register 4910 */ 4911 #define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) 4912 /** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4913 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4914 * high level. s=0x3C: set this port always low level. 4915 */ 4916 #define GPIO_FUNC122_IN_SEL 0x0000003FU 4917 #define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) 4918 #define GPIO_FUNC122_IN_SEL_V 0x0000003FU 4919 #define GPIO_FUNC122_IN_SEL_S 0 4920 /** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4921 * set this bit to invert input signal. 1:invert. 0:not invert. 4922 */ 4923 #define GPIO_FUNC122_IN_INV_SEL (BIT(6)) 4924 #define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) 4925 #define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U 4926 #define GPIO_FUNC122_IN_INV_SEL_S 6 4927 /** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; 4928 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4929 */ 4930 #define GPIO_SIG122_IN_SEL (BIT(7)) 4931 #define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) 4932 #define GPIO_SIG122_IN_SEL_V 0x00000001U 4933 #define GPIO_SIG122_IN_SEL_S 7 4934 4935 /** GPIO_FUNC123_IN_SEL_CFG_REG register 4936 * GPIO input function configuration register 4937 */ 4938 #define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) 4939 /** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4940 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4941 * high level. s=0x3C: set this port always low level. 4942 */ 4943 #define GPIO_FUNC123_IN_SEL 0x0000003FU 4944 #define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) 4945 #define GPIO_FUNC123_IN_SEL_V 0x0000003FU 4946 #define GPIO_FUNC123_IN_SEL_S 0 4947 /** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4948 * set this bit to invert input signal. 1:invert. 0:not invert. 4949 */ 4950 #define GPIO_FUNC123_IN_INV_SEL (BIT(6)) 4951 #define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) 4952 #define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U 4953 #define GPIO_FUNC123_IN_INV_SEL_S 6 4954 /** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; 4955 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4956 */ 4957 #define GPIO_SIG123_IN_SEL (BIT(7)) 4958 #define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) 4959 #define GPIO_SIG123_IN_SEL_V 0x00000001U 4960 #define GPIO_SIG123_IN_SEL_S 7 4961 4962 /** GPIO_FUNC124_IN_SEL_CFG_REG register 4963 * GPIO input function configuration register 4964 */ 4965 #define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) 4966 /** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 60; 4967 * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always 4968 * high level. s=0x3C: set this port always low level. 4969 */ 4970 #define GPIO_FUNC124_IN_SEL 0x0000003FU 4971 #define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) 4972 #define GPIO_FUNC124_IN_SEL_V 0x0000003FU 4973 #define GPIO_FUNC124_IN_SEL_S 0 4974 /** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; 4975 * set this bit to invert input signal. 1:invert. 0:not invert. 4976 */ 4977 #define GPIO_FUNC124_IN_INV_SEL (BIT(6)) 4978 #define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) 4979 #define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U 4980 #define GPIO_FUNC124_IN_INV_SEL_S 6 4981 /** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; 4982 * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 4983 */ 4984 #define GPIO_SIG124_IN_SEL (BIT(7)) 4985 #define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) 4986 #define GPIO_SIG124_IN_SEL_V 0x00000001U 4987 #define GPIO_SIG124_IN_SEL_S 7 4988 4989 /** GPIO_FUNC0_OUT_SEL_CFG_REG register 4990 * GPIO output function select register 4991 */ 4992 #define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) 4993 /** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 4994 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 4995 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 4996 * GPIO_OUT_REG[n]. 4997 */ 4998 #define GPIO_FUNC0_OUT_SEL 0x000000FFU 4999 #define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) 5000 #define GPIO_FUNC0_OUT_SEL_V 0x000000FFU 5001 #define GPIO_FUNC0_OUT_SEL_S 0 5002 /** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5003 * set this bit to invert output signal.1:invert.0:not invert. 5004 */ 5005 #define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) 5006 #define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) 5007 #define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U 5008 #define GPIO_FUNC0_OUT_INV_SEL_S 8 5009 /** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; 5010 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5011 * enable signal.0:use peripheral output enable signal. 5012 */ 5013 #define GPIO_FUNC0_OEN_SEL (BIT(9)) 5014 #define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) 5015 #define GPIO_FUNC0_OEN_SEL_V 0x00000001U 5016 #define GPIO_FUNC0_OEN_SEL_S 9 5017 /** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5018 * set this bit to invert output enable signal.1:invert.0:not invert. 5019 */ 5020 #define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) 5021 #define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) 5022 #define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U 5023 #define GPIO_FUNC0_OEN_INV_SEL_S 10 5024 5025 /** GPIO_FUNC1_OUT_SEL_CFG_REG register 5026 * GPIO output function select register 5027 */ 5028 #define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) 5029 /** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5030 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5031 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5032 * GPIO_OUT_REG[n]. 5033 */ 5034 #define GPIO_FUNC1_OUT_SEL 0x000000FFU 5035 #define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) 5036 #define GPIO_FUNC1_OUT_SEL_V 0x000000FFU 5037 #define GPIO_FUNC1_OUT_SEL_S 0 5038 /** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5039 * set this bit to invert output signal.1:invert.0:not invert. 5040 */ 5041 #define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) 5042 #define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) 5043 #define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U 5044 #define GPIO_FUNC1_OUT_INV_SEL_S 8 5045 /** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; 5046 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5047 * enable signal.0:use peripheral output enable signal. 5048 */ 5049 #define GPIO_FUNC1_OEN_SEL (BIT(9)) 5050 #define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) 5051 #define GPIO_FUNC1_OEN_SEL_V 0x00000001U 5052 #define GPIO_FUNC1_OEN_SEL_S 9 5053 /** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5054 * set this bit to invert output enable signal.1:invert.0:not invert. 5055 */ 5056 #define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) 5057 #define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) 5058 #define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U 5059 #define GPIO_FUNC1_OEN_INV_SEL_S 10 5060 5061 /** GPIO_FUNC2_OUT_SEL_CFG_REG register 5062 * GPIO output function select register 5063 */ 5064 #define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) 5065 /** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5066 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5067 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5068 * GPIO_OUT_REG[n]. 5069 */ 5070 #define GPIO_FUNC2_OUT_SEL 0x000000FFU 5071 #define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) 5072 #define GPIO_FUNC2_OUT_SEL_V 0x000000FFU 5073 #define GPIO_FUNC2_OUT_SEL_S 0 5074 /** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5075 * set this bit to invert output signal.1:invert.0:not invert. 5076 */ 5077 #define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) 5078 #define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) 5079 #define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U 5080 #define GPIO_FUNC2_OUT_INV_SEL_S 8 5081 /** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; 5082 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5083 * enable signal.0:use peripheral output enable signal. 5084 */ 5085 #define GPIO_FUNC2_OEN_SEL (BIT(9)) 5086 #define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) 5087 #define GPIO_FUNC2_OEN_SEL_V 0x00000001U 5088 #define GPIO_FUNC2_OEN_SEL_S 9 5089 /** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5090 * set this bit to invert output enable signal.1:invert.0:not invert. 5091 */ 5092 #define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) 5093 #define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) 5094 #define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U 5095 #define GPIO_FUNC2_OEN_INV_SEL_S 10 5096 5097 /** GPIO_FUNC3_OUT_SEL_CFG_REG register 5098 * GPIO output function select register 5099 */ 5100 #define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) 5101 /** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5102 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5103 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5104 * GPIO_OUT_REG[n]. 5105 */ 5106 #define GPIO_FUNC3_OUT_SEL 0x000000FFU 5107 #define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) 5108 #define GPIO_FUNC3_OUT_SEL_V 0x000000FFU 5109 #define GPIO_FUNC3_OUT_SEL_S 0 5110 /** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5111 * set this bit to invert output signal.1:invert.0:not invert. 5112 */ 5113 #define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) 5114 #define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) 5115 #define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U 5116 #define GPIO_FUNC3_OUT_INV_SEL_S 8 5117 /** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; 5118 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5119 * enable signal.0:use peripheral output enable signal. 5120 */ 5121 #define GPIO_FUNC3_OEN_SEL (BIT(9)) 5122 #define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) 5123 #define GPIO_FUNC3_OEN_SEL_V 0x00000001U 5124 #define GPIO_FUNC3_OEN_SEL_S 9 5125 /** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5126 * set this bit to invert output enable signal.1:invert.0:not invert. 5127 */ 5128 #define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) 5129 #define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) 5130 #define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U 5131 #define GPIO_FUNC3_OEN_INV_SEL_S 10 5132 5133 /** GPIO_FUNC4_OUT_SEL_CFG_REG register 5134 * GPIO output function select register 5135 */ 5136 #define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) 5137 /** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5138 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5139 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5140 * GPIO_OUT_REG[n]. 5141 */ 5142 #define GPIO_FUNC4_OUT_SEL 0x000000FFU 5143 #define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) 5144 #define GPIO_FUNC4_OUT_SEL_V 0x000000FFU 5145 #define GPIO_FUNC4_OUT_SEL_S 0 5146 /** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5147 * set this bit to invert output signal.1:invert.0:not invert. 5148 */ 5149 #define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) 5150 #define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) 5151 #define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U 5152 #define GPIO_FUNC4_OUT_INV_SEL_S 8 5153 /** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; 5154 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5155 * enable signal.0:use peripheral output enable signal. 5156 */ 5157 #define GPIO_FUNC4_OEN_SEL (BIT(9)) 5158 #define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) 5159 #define GPIO_FUNC4_OEN_SEL_V 0x00000001U 5160 #define GPIO_FUNC4_OEN_SEL_S 9 5161 /** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5162 * set this bit to invert output enable signal.1:invert.0:not invert. 5163 */ 5164 #define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) 5165 #define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) 5166 #define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U 5167 #define GPIO_FUNC4_OEN_INV_SEL_S 10 5168 5169 /** GPIO_FUNC5_OUT_SEL_CFG_REG register 5170 * GPIO output function select register 5171 */ 5172 #define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) 5173 /** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5174 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5175 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5176 * GPIO_OUT_REG[n]. 5177 */ 5178 #define GPIO_FUNC5_OUT_SEL 0x000000FFU 5179 #define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) 5180 #define GPIO_FUNC5_OUT_SEL_V 0x000000FFU 5181 #define GPIO_FUNC5_OUT_SEL_S 0 5182 /** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5183 * set this bit to invert output signal.1:invert.0:not invert. 5184 */ 5185 #define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) 5186 #define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) 5187 #define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U 5188 #define GPIO_FUNC5_OUT_INV_SEL_S 8 5189 /** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; 5190 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5191 * enable signal.0:use peripheral output enable signal. 5192 */ 5193 #define GPIO_FUNC5_OEN_SEL (BIT(9)) 5194 #define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) 5195 #define GPIO_FUNC5_OEN_SEL_V 0x00000001U 5196 #define GPIO_FUNC5_OEN_SEL_S 9 5197 /** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5198 * set this bit to invert output enable signal.1:invert.0:not invert. 5199 */ 5200 #define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) 5201 #define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) 5202 #define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U 5203 #define GPIO_FUNC5_OEN_INV_SEL_S 10 5204 5205 /** GPIO_FUNC6_OUT_SEL_CFG_REG register 5206 * GPIO output function select register 5207 */ 5208 #define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) 5209 /** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5210 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5211 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5212 * GPIO_OUT_REG[n]. 5213 */ 5214 #define GPIO_FUNC6_OUT_SEL 0x000000FFU 5215 #define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) 5216 #define GPIO_FUNC6_OUT_SEL_V 0x000000FFU 5217 #define GPIO_FUNC6_OUT_SEL_S 0 5218 /** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5219 * set this bit to invert output signal.1:invert.0:not invert. 5220 */ 5221 #define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) 5222 #define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) 5223 #define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U 5224 #define GPIO_FUNC6_OUT_INV_SEL_S 8 5225 /** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; 5226 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5227 * enable signal.0:use peripheral output enable signal. 5228 */ 5229 #define GPIO_FUNC6_OEN_SEL (BIT(9)) 5230 #define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) 5231 #define GPIO_FUNC6_OEN_SEL_V 0x00000001U 5232 #define GPIO_FUNC6_OEN_SEL_S 9 5233 /** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5234 * set this bit to invert output enable signal.1:invert.0:not invert. 5235 */ 5236 #define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) 5237 #define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) 5238 #define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U 5239 #define GPIO_FUNC6_OEN_INV_SEL_S 10 5240 5241 /** GPIO_FUNC7_OUT_SEL_CFG_REG register 5242 * GPIO output function select register 5243 */ 5244 #define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) 5245 /** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5246 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5247 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5248 * GPIO_OUT_REG[n]. 5249 */ 5250 #define GPIO_FUNC7_OUT_SEL 0x000000FFU 5251 #define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) 5252 #define GPIO_FUNC7_OUT_SEL_V 0x000000FFU 5253 #define GPIO_FUNC7_OUT_SEL_S 0 5254 /** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5255 * set this bit to invert output signal.1:invert.0:not invert. 5256 */ 5257 #define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) 5258 #define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) 5259 #define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U 5260 #define GPIO_FUNC7_OUT_INV_SEL_S 8 5261 /** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; 5262 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5263 * enable signal.0:use peripheral output enable signal. 5264 */ 5265 #define GPIO_FUNC7_OEN_SEL (BIT(9)) 5266 #define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) 5267 #define GPIO_FUNC7_OEN_SEL_V 0x00000001U 5268 #define GPIO_FUNC7_OEN_SEL_S 9 5269 /** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5270 * set this bit to invert output enable signal.1:invert.0:not invert. 5271 */ 5272 #define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) 5273 #define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) 5274 #define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U 5275 #define GPIO_FUNC7_OEN_INV_SEL_S 10 5276 5277 /** GPIO_FUNC8_OUT_SEL_CFG_REG register 5278 * GPIO output function select register 5279 */ 5280 #define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) 5281 /** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5282 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5283 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5284 * GPIO_OUT_REG[n]. 5285 */ 5286 #define GPIO_FUNC8_OUT_SEL 0x000000FFU 5287 #define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) 5288 #define GPIO_FUNC8_OUT_SEL_V 0x000000FFU 5289 #define GPIO_FUNC8_OUT_SEL_S 0 5290 /** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5291 * set this bit to invert output signal.1:invert.0:not invert. 5292 */ 5293 #define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) 5294 #define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) 5295 #define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U 5296 #define GPIO_FUNC8_OUT_INV_SEL_S 8 5297 /** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; 5298 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5299 * enable signal.0:use peripheral output enable signal. 5300 */ 5301 #define GPIO_FUNC8_OEN_SEL (BIT(9)) 5302 #define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) 5303 #define GPIO_FUNC8_OEN_SEL_V 0x00000001U 5304 #define GPIO_FUNC8_OEN_SEL_S 9 5305 /** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5306 * set this bit to invert output enable signal.1:invert.0:not invert. 5307 */ 5308 #define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) 5309 #define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) 5310 #define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U 5311 #define GPIO_FUNC8_OEN_INV_SEL_S 10 5312 5313 /** GPIO_FUNC9_OUT_SEL_CFG_REG register 5314 * GPIO output function select register 5315 */ 5316 #define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) 5317 /** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5318 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5319 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5320 * GPIO_OUT_REG[n]. 5321 */ 5322 #define GPIO_FUNC9_OUT_SEL 0x000000FFU 5323 #define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) 5324 #define GPIO_FUNC9_OUT_SEL_V 0x000000FFU 5325 #define GPIO_FUNC9_OUT_SEL_S 0 5326 /** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5327 * set this bit to invert output signal.1:invert.0:not invert. 5328 */ 5329 #define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) 5330 #define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) 5331 #define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U 5332 #define GPIO_FUNC9_OUT_INV_SEL_S 8 5333 /** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; 5334 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5335 * enable signal.0:use peripheral output enable signal. 5336 */ 5337 #define GPIO_FUNC9_OEN_SEL (BIT(9)) 5338 #define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) 5339 #define GPIO_FUNC9_OEN_SEL_V 0x00000001U 5340 #define GPIO_FUNC9_OEN_SEL_S 9 5341 /** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5342 * set this bit to invert output enable signal.1:invert.0:not invert. 5343 */ 5344 #define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) 5345 #define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) 5346 #define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U 5347 #define GPIO_FUNC9_OEN_INV_SEL_S 10 5348 5349 /** GPIO_FUNC10_OUT_SEL_CFG_REG register 5350 * GPIO output function select register 5351 */ 5352 #define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) 5353 /** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5354 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5355 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5356 * GPIO_OUT_REG[n]. 5357 */ 5358 #define GPIO_FUNC10_OUT_SEL 0x000000FFU 5359 #define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) 5360 #define GPIO_FUNC10_OUT_SEL_V 0x000000FFU 5361 #define GPIO_FUNC10_OUT_SEL_S 0 5362 /** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5363 * set this bit to invert output signal.1:invert.0:not invert. 5364 */ 5365 #define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) 5366 #define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) 5367 #define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U 5368 #define GPIO_FUNC10_OUT_INV_SEL_S 8 5369 /** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; 5370 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5371 * enable signal.0:use peripheral output enable signal. 5372 */ 5373 #define GPIO_FUNC10_OEN_SEL (BIT(9)) 5374 #define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) 5375 #define GPIO_FUNC10_OEN_SEL_V 0x00000001U 5376 #define GPIO_FUNC10_OEN_SEL_S 9 5377 /** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5378 * set this bit to invert output enable signal.1:invert.0:not invert. 5379 */ 5380 #define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) 5381 #define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) 5382 #define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U 5383 #define GPIO_FUNC10_OEN_INV_SEL_S 10 5384 5385 /** GPIO_FUNC11_OUT_SEL_CFG_REG register 5386 * GPIO output function select register 5387 */ 5388 #define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) 5389 /** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5390 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5391 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5392 * GPIO_OUT_REG[n]. 5393 */ 5394 #define GPIO_FUNC11_OUT_SEL 0x000000FFU 5395 #define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) 5396 #define GPIO_FUNC11_OUT_SEL_V 0x000000FFU 5397 #define GPIO_FUNC11_OUT_SEL_S 0 5398 /** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5399 * set this bit to invert output signal.1:invert.0:not invert. 5400 */ 5401 #define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) 5402 #define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) 5403 #define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U 5404 #define GPIO_FUNC11_OUT_INV_SEL_S 8 5405 /** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; 5406 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5407 * enable signal.0:use peripheral output enable signal. 5408 */ 5409 #define GPIO_FUNC11_OEN_SEL (BIT(9)) 5410 #define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) 5411 #define GPIO_FUNC11_OEN_SEL_V 0x00000001U 5412 #define GPIO_FUNC11_OEN_SEL_S 9 5413 /** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5414 * set this bit to invert output enable signal.1:invert.0:not invert. 5415 */ 5416 #define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) 5417 #define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) 5418 #define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U 5419 #define GPIO_FUNC11_OEN_INV_SEL_S 10 5420 5421 /** GPIO_FUNC12_OUT_SEL_CFG_REG register 5422 * GPIO output function select register 5423 */ 5424 #define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) 5425 /** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5426 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5427 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5428 * GPIO_OUT_REG[n]. 5429 */ 5430 #define GPIO_FUNC12_OUT_SEL 0x000000FFU 5431 #define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) 5432 #define GPIO_FUNC12_OUT_SEL_V 0x000000FFU 5433 #define GPIO_FUNC12_OUT_SEL_S 0 5434 /** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5435 * set this bit to invert output signal.1:invert.0:not invert. 5436 */ 5437 #define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) 5438 #define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) 5439 #define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U 5440 #define GPIO_FUNC12_OUT_INV_SEL_S 8 5441 /** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; 5442 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5443 * enable signal.0:use peripheral output enable signal. 5444 */ 5445 #define GPIO_FUNC12_OEN_SEL (BIT(9)) 5446 #define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) 5447 #define GPIO_FUNC12_OEN_SEL_V 0x00000001U 5448 #define GPIO_FUNC12_OEN_SEL_S 9 5449 /** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5450 * set this bit to invert output enable signal.1:invert.0:not invert. 5451 */ 5452 #define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) 5453 #define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) 5454 #define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U 5455 #define GPIO_FUNC12_OEN_INV_SEL_S 10 5456 5457 /** GPIO_FUNC13_OUT_SEL_CFG_REG register 5458 * GPIO output function select register 5459 */ 5460 #define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) 5461 /** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5462 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5463 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5464 * GPIO_OUT_REG[n]. 5465 */ 5466 #define GPIO_FUNC13_OUT_SEL 0x000000FFU 5467 #define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) 5468 #define GPIO_FUNC13_OUT_SEL_V 0x000000FFU 5469 #define GPIO_FUNC13_OUT_SEL_S 0 5470 /** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5471 * set this bit to invert output signal.1:invert.0:not invert. 5472 */ 5473 #define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) 5474 #define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) 5475 #define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U 5476 #define GPIO_FUNC13_OUT_INV_SEL_S 8 5477 /** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; 5478 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5479 * enable signal.0:use peripheral output enable signal. 5480 */ 5481 #define GPIO_FUNC13_OEN_SEL (BIT(9)) 5482 #define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) 5483 #define GPIO_FUNC13_OEN_SEL_V 0x00000001U 5484 #define GPIO_FUNC13_OEN_SEL_S 9 5485 /** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5486 * set this bit to invert output enable signal.1:invert.0:not invert. 5487 */ 5488 #define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) 5489 #define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) 5490 #define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U 5491 #define GPIO_FUNC13_OEN_INV_SEL_S 10 5492 5493 /** GPIO_FUNC14_OUT_SEL_CFG_REG register 5494 * GPIO output function select register 5495 */ 5496 #define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) 5497 /** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5498 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5499 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5500 * GPIO_OUT_REG[n]. 5501 */ 5502 #define GPIO_FUNC14_OUT_SEL 0x000000FFU 5503 #define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) 5504 #define GPIO_FUNC14_OUT_SEL_V 0x000000FFU 5505 #define GPIO_FUNC14_OUT_SEL_S 0 5506 /** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5507 * set this bit to invert output signal.1:invert.0:not invert. 5508 */ 5509 #define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) 5510 #define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) 5511 #define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U 5512 #define GPIO_FUNC14_OUT_INV_SEL_S 8 5513 /** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; 5514 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5515 * enable signal.0:use peripheral output enable signal. 5516 */ 5517 #define GPIO_FUNC14_OEN_SEL (BIT(9)) 5518 #define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) 5519 #define GPIO_FUNC14_OEN_SEL_V 0x00000001U 5520 #define GPIO_FUNC14_OEN_SEL_S 9 5521 /** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5522 * set this bit to invert output enable signal.1:invert.0:not invert. 5523 */ 5524 #define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) 5525 #define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) 5526 #define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U 5527 #define GPIO_FUNC14_OEN_INV_SEL_S 10 5528 5529 /** GPIO_FUNC15_OUT_SEL_CFG_REG register 5530 * GPIO output function select register 5531 */ 5532 #define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) 5533 /** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5534 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5535 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5536 * GPIO_OUT_REG[n]. 5537 */ 5538 #define GPIO_FUNC15_OUT_SEL 0x000000FFU 5539 #define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) 5540 #define GPIO_FUNC15_OUT_SEL_V 0x000000FFU 5541 #define GPIO_FUNC15_OUT_SEL_S 0 5542 /** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5543 * set this bit to invert output signal.1:invert.0:not invert. 5544 */ 5545 #define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) 5546 #define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) 5547 #define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U 5548 #define GPIO_FUNC15_OUT_INV_SEL_S 8 5549 /** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; 5550 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5551 * enable signal.0:use peripheral output enable signal. 5552 */ 5553 #define GPIO_FUNC15_OEN_SEL (BIT(9)) 5554 #define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) 5555 #define GPIO_FUNC15_OEN_SEL_V 0x00000001U 5556 #define GPIO_FUNC15_OEN_SEL_S 9 5557 /** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5558 * set this bit to invert output enable signal.1:invert.0:not invert. 5559 */ 5560 #define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) 5561 #define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) 5562 #define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U 5563 #define GPIO_FUNC15_OEN_INV_SEL_S 10 5564 5565 /** GPIO_FUNC16_OUT_SEL_CFG_REG register 5566 * GPIO output function select register 5567 */ 5568 #define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) 5569 /** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5570 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5571 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5572 * GPIO_OUT_REG[n]. 5573 */ 5574 #define GPIO_FUNC16_OUT_SEL 0x000000FFU 5575 #define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) 5576 #define GPIO_FUNC16_OUT_SEL_V 0x000000FFU 5577 #define GPIO_FUNC16_OUT_SEL_S 0 5578 /** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5579 * set this bit to invert output signal.1:invert.0:not invert. 5580 */ 5581 #define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) 5582 #define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) 5583 #define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U 5584 #define GPIO_FUNC16_OUT_INV_SEL_S 8 5585 /** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; 5586 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5587 * enable signal.0:use peripheral output enable signal. 5588 */ 5589 #define GPIO_FUNC16_OEN_SEL (BIT(9)) 5590 #define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) 5591 #define GPIO_FUNC16_OEN_SEL_V 0x00000001U 5592 #define GPIO_FUNC16_OEN_SEL_S 9 5593 /** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5594 * set this bit to invert output enable signal.1:invert.0:not invert. 5595 */ 5596 #define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) 5597 #define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) 5598 #define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U 5599 #define GPIO_FUNC16_OEN_INV_SEL_S 10 5600 5601 /** GPIO_FUNC17_OUT_SEL_CFG_REG register 5602 * GPIO output function select register 5603 */ 5604 #define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) 5605 /** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5606 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5607 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5608 * GPIO_OUT_REG[n]. 5609 */ 5610 #define GPIO_FUNC17_OUT_SEL 0x000000FFU 5611 #define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) 5612 #define GPIO_FUNC17_OUT_SEL_V 0x000000FFU 5613 #define GPIO_FUNC17_OUT_SEL_S 0 5614 /** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5615 * set this bit to invert output signal.1:invert.0:not invert. 5616 */ 5617 #define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) 5618 #define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) 5619 #define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U 5620 #define GPIO_FUNC17_OUT_INV_SEL_S 8 5621 /** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; 5622 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5623 * enable signal.0:use peripheral output enable signal. 5624 */ 5625 #define GPIO_FUNC17_OEN_SEL (BIT(9)) 5626 #define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) 5627 #define GPIO_FUNC17_OEN_SEL_V 0x00000001U 5628 #define GPIO_FUNC17_OEN_SEL_S 9 5629 /** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5630 * set this bit to invert output enable signal.1:invert.0:not invert. 5631 */ 5632 #define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) 5633 #define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) 5634 #define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U 5635 #define GPIO_FUNC17_OEN_INV_SEL_S 10 5636 5637 /** GPIO_FUNC18_OUT_SEL_CFG_REG register 5638 * GPIO output function select register 5639 */ 5640 #define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) 5641 /** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5642 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5643 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5644 * GPIO_OUT_REG[n]. 5645 */ 5646 #define GPIO_FUNC18_OUT_SEL 0x000000FFU 5647 #define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) 5648 #define GPIO_FUNC18_OUT_SEL_V 0x000000FFU 5649 #define GPIO_FUNC18_OUT_SEL_S 0 5650 /** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5651 * set this bit to invert output signal.1:invert.0:not invert. 5652 */ 5653 #define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) 5654 #define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) 5655 #define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U 5656 #define GPIO_FUNC18_OUT_INV_SEL_S 8 5657 /** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; 5658 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5659 * enable signal.0:use peripheral output enable signal. 5660 */ 5661 #define GPIO_FUNC18_OEN_SEL (BIT(9)) 5662 #define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) 5663 #define GPIO_FUNC18_OEN_SEL_V 0x00000001U 5664 #define GPIO_FUNC18_OEN_SEL_S 9 5665 /** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5666 * set this bit to invert output enable signal.1:invert.0:not invert. 5667 */ 5668 #define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) 5669 #define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) 5670 #define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U 5671 #define GPIO_FUNC18_OEN_INV_SEL_S 10 5672 5673 /** GPIO_FUNC19_OUT_SEL_CFG_REG register 5674 * GPIO output function select register 5675 */ 5676 #define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) 5677 /** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5678 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5679 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5680 * GPIO_OUT_REG[n]. 5681 */ 5682 #define GPIO_FUNC19_OUT_SEL 0x000000FFU 5683 #define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) 5684 #define GPIO_FUNC19_OUT_SEL_V 0x000000FFU 5685 #define GPIO_FUNC19_OUT_SEL_S 0 5686 /** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5687 * set this bit to invert output signal.1:invert.0:not invert. 5688 */ 5689 #define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) 5690 #define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) 5691 #define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U 5692 #define GPIO_FUNC19_OUT_INV_SEL_S 8 5693 /** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; 5694 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5695 * enable signal.0:use peripheral output enable signal. 5696 */ 5697 #define GPIO_FUNC19_OEN_SEL (BIT(9)) 5698 #define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) 5699 #define GPIO_FUNC19_OEN_SEL_V 0x00000001U 5700 #define GPIO_FUNC19_OEN_SEL_S 9 5701 /** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5702 * set this bit to invert output enable signal.1:invert.0:not invert. 5703 */ 5704 #define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) 5705 #define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) 5706 #define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U 5707 #define GPIO_FUNC19_OEN_INV_SEL_S 10 5708 5709 /** GPIO_FUNC20_OUT_SEL_CFG_REG register 5710 * GPIO output function select register 5711 */ 5712 #define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) 5713 /** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5714 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5715 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5716 * GPIO_OUT_REG[n]. 5717 */ 5718 #define GPIO_FUNC20_OUT_SEL 0x000000FFU 5719 #define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) 5720 #define GPIO_FUNC20_OUT_SEL_V 0x000000FFU 5721 #define GPIO_FUNC20_OUT_SEL_S 0 5722 /** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5723 * set this bit to invert output signal.1:invert.0:not invert. 5724 */ 5725 #define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) 5726 #define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) 5727 #define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U 5728 #define GPIO_FUNC20_OUT_INV_SEL_S 8 5729 /** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; 5730 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5731 * enable signal.0:use peripheral output enable signal. 5732 */ 5733 #define GPIO_FUNC20_OEN_SEL (BIT(9)) 5734 #define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) 5735 #define GPIO_FUNC20_OEN_SEL_V 0x00000001U 5736 #define GPIO_FUNC20_OEN_SEL_S 9 5737 /** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5738 * set this bit to invert output enable signal.1:invert.0:not invert. 5739 */ 5740 #define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) 5741 #define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) 5742 #define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U 5743 #define GPIO_FUNC20_OEN_INV_SEL_S 10 5744 5745 /** GPIO_FUNC21_OUT_SEL_CFG_REG register 5746 * GPIO output function select register 5747 */ 5748 #define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) 5749 /** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5750 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5751 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5752 * GPIO_OUT_REG[n]. 5753 */ 5754 #define GPIO_FUNC21_OUT_SEL 0x000000FFU 5755 #define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) 5756 #define GPIO_FUNC21_OUT_SEL_V 0x000000FFU 5757 #define GPIO_FUNC21_OUT_SEL_S 0 5758 /** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5759 * set this bit to invert output signal.1:invert.0:not invert. 5760 */ 5761 #define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) 5762 #define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) 5763 #define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U 5764 #define GPIO_FUNC21_OUT_INV_SEL_S 8 5765 /** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; 5766 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5767 * enable signal.0:use peripheral output enable signal. 5768 */ 5769 #define GPIO_FUNC21_OEN_SEL (BIT(9)) 5770 #define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) 5771 #define GPIO_FUNC21_OEN_SEL_V 0x00000001U 5772 #define GPIO_FUNC21_OEN_SEL_S 9 5773 /** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5774 * set this bit to invert output enable signal.1:invert.0:not invert. 5775 */ 5776 #define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) 5777 #define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) 5778 #define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U 5779 #define GPIO_FUNC21_OEN_INV_SEL_S 10 5780 5781 /** GPIO_FUNC22_OUT_SEL_CFG_REG register 5782 * GPIO output function select register 5783 */ 5784 #define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) 5785 /** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5786 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5787 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5788 * GPIO_OUT_REG[n]. 5789 */ 5790 #define GPIO_FUNC22_OUT_SEL 0x000000FFU 5791 #define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) 5792 #define GPIO_FUNC22_OUT_SEL_V 0x000000FFU 5793 #define GPIO_FUNC22_OUT_SEL_S 0 5794 /** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5795 * set this bit to invert output signal.1:invert.0:not invert. 5796 */ 5797 #define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) 5798 #define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) 5799 #define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U 5800 #define GPIO_FUNC22_OUT_INV_SEL_S 8 5801 /** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; 5802 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5803 * enable signal.0:use peripheral output enable signal. 5804 */ 5805 #define GPIO_FUNC22_OEN_SEL (BIT(9)) 5806 #define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) 5807 #define GPIO_FUNC22_OEN_SEL_V 0x00000001U 5808 #define GPIO_FUNC22_OEN_SEL_S 9 5809 /** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5810 * set this bit to invert output enable signal.1:invert.0:not invert. 5811 */ 5812 #define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) 5813 #define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) 5814 #define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U 5815 #define GPIO_FUNC22_OEN_INV_SEL_S 10 5816 5817 /** GPIO_FUNC23_OUT_SEL_CFG_REG register 5818 * GPIO output function select register 5819 */ 5820 #define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) 5821 /** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5822 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5823 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5824 * GPIO_OUT_REG[n]. 5825 */ 5826 #define GPIO_FUNC23_OUT_SEL 0x000000FFU 5827 #define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) 5828 #define GPIO_FUNC23_OUT_SEL_V 0x000000FFU 5829 #define GPIO_FUNC23_OUT_SEL_S 0 5830 /** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5831 * set this bit to invert output signal.1:invert.0:not invert. 5832 */ 5833 #define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) 5834 #define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) 5835 #define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U 5836 #define GPIO_FUNC23_OUT_INV_SEL_S 8 5837 /** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; 5838 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5839 * enable signal.0:use peripheral output enable signal. 5840 */ 5841 #define GPIO_FUNC23_OEN_SEL (BIT(9)) 5842 #define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) 5843 #define GPIO_FUNC23_OEN_SEL_V 0x00000001U 5844 #define GPIO_FUNC23_OEN_SEL_S 9 5845 /** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5846 * set this bit to invert output enable signal.1:invert.0:not invert. 5847 */ 5848 #define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) 5849 #define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) 5850 #define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U 5851 #define GPIO_FUNC23_OEN_INV_SEL_S 10 5852 5853 /** GPIO_FUNC24_OUT_SEL_CFG_REG register 5854 * GPIO output function select register 5855 */ 5856 #define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) 5857 /** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5858 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5859 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5860 * GPIO_OUT_REG[n]. 5861 */ 5862 #define GPIO_FUNC24_OUT_SEL 0x000000FFU 5863 #define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) 5864 #define GPIO_FUNC24_OUT_SEL_V 0x000000FFU 5865 #define GPIO_FUNC24_OUT_SEL_S 0 5866 /** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5867 * set this bit to invert output signal.1:invert.0:not invert. 5868 */ 5869 #define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) 5870 #define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) 5871 #define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U 5872 #define GPIO_FUNC24_OUT_INV_SEL_S 8 5873 /** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; 5874 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5875 * enable signal.0:use peripheral output enable signal. 5876 */ 5877 #define GPIO_FUNC24_OEN_SEL (BIT(9)) 5878 #define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) 5879 #define GPIO_FUNC24_OEN_SEL_V 0x00000001U 5880 #define GPIO_FUNC24_OEN_SEL_S 9 5881 /** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5882 * set this bit to invert output enable signal.1:invert.0:not invert. 5883 */ 5884 #define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) 5885 #define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) 5886 #define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U 5887 #define GPIO_FUNC24_OEN_INV_SEL_S 10 5888 5889 /** GPIO_FUNC25_OUT_SEL_CFG_REG register 5890 * GPIO output function select register 5891 */ 5892 #define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) 5893 /** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5894 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5895 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5896 * GPIO_OUT_REG[n]. 5897 */ 5898 #define GPIO_FUNC25_OUT_SEL 0x000000FFU 5899 #define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) 5900 #define GPIO_FUNC25_OUT_SEL_V 0x000000FFU 5901 #define GPIO_FUNC25_OUT_SEL_S 0 5902 /** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5903 * set this bit to invert output signal.1:invert.0:not invert. 5904 */ 5905 #define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) 5906 #define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) 5907 #define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U 5908 #define GPIO_FUNC25_OUT_INV_SEL_S 8 5909 /** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; 5910 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5911 * enable signal.0:use peripheral output enable signal. 5912 */ 5913 #define GPIO_FUNC25_OEN_SEL (BIT(9)) 5914 #define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) 5915 #define GPIO_FUNC25_OEN_SEL_V 0x00000001U 5916 #define GPIO_FUNC25_OEN_SEL_S 9 5917 /** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5918 * set this bit to invert output enable signal.1:invert.0:not invert. 5919 */ 5920 #define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) 5921 #define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) 5922 #define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U 5923 #define GPIO_FUNC25_OEN_INV_SEL_S 10 5924 5925 /** GPIO_FUNC26_OUT_SEL_CFG_REG register 5926 * GPIO output function select register 5927 */ 5928 #define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) 5929 /** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5930 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5931 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5932 * GPIO_OUT_REG[n]. 5933 */ 5934 #define GPIO_FUNC26_OUT_SEL 0x000000FFU 5935 #define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) 5936 #define GPIO_FUNC26_OUT_SEL_V 0x000000FFU 5937 #define GPIO_FUNC26_OUT_SEL_S 0 5938 /** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5939 * set this bit to invert output signal.1:invert.0:not invert. 5940 */ 5941 #define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) 5942 #define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) 5943 #define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U 5944 #define GPIO_FUNC26_OUT_INV_SEL_S 8 5945 /** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; 5946 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5947 * enable signal.0:use peripheral output enable signal. 5948 */ 5949 #define GPIO_FUNC26_OEN_SEL (BIT(9)) 5950 #define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) 5951 #define GPIO_FUNC26_OEN_SEL_V 0x00000001U 5952 #define GPIO_FUNC26_OEN_SEL_S 9 5953 /** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5954 * set this bit to invert output enable signal.1:invert.0:not invert. 5955 */ 5956 #define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) 5957 #define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) 5958 #define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U 5959 #define GPIO_FUNC26_OEN_INV_SEL_S 10 5960 5961 /** GPIO_FUNC27_OUT_SEL_CFG_REG register 5962 * GPIO output function select register 5963 */ 5964 #define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) 5965 /** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 5966 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 5967 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 5968 * GPIO_OUT_REG[n]. 5969 */ 5970 #define GPIO_FUNC27_OUT_SEL 0x000000FFU 5971 #define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) 5972 #define GPIO_FUNC27_OUT_SEL_V 0x000000FFU 5973 #define GPIO_FUNC27_OUT_SEL_S 0 5974 /** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 5975 * set this bit to invert output signal.1:invert.0:not invert. 5976 */ 5977 #define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) 5978 #define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) 5979 #define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U 5980 #define GPIO_FUNC27_OUT_INV_SEL_S 8 5981 /** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; 5982 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 5983 * enable signal.0:use peripheral output enable signal. 5984 */ 5985 #define GPIO_FUNC27_OEN_SEL (BIT(9)) 5986 #define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) 5987 #define GPIO_FUNC27_OEN_SEL_V 0x00000001U 5988 #define GPIO_FUNC27_OEN_SEL_S 9 5989 /** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 5990 * set this bit to invert output enable signal.1:invert.0:not invert. 5991 */ 5992 #define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) 5993 #define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) 5994 #define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U 5995 #define GPIO_FUNC27_OEN_INV_SEL_S 10 5996 5997 /** GPIO_FUNC28_OUT_SEL_CFG_REG register 5998 * GPIO output function select register 5999 */ 6000 #define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) 6001 /** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 6002 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 6003 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 6004 * GPIO_OUT_REG[n]. 6005 */ 6006 #define GPIO_FUNC28_OUT_SEL 0x000000FFU 6007 #define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) 6008 #define GPIO_FUNC28_OUT_SEL_V 0x000000FFU 6009 #define GPIO_FUNC28_OUT_SEL_S 0 6010 /** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 6011 * set this bit to invert output signal.1:invert.0:not invert. 6012 */ 6013 #define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) 6014 #define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) 6015 #define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U 6016 #define GPIO_FUNC28_OUT_INV_SEL_S 8 6017 /** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; 6018 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 6019 * enable signal.0:use peripheral output enable signal. 6020 */ 6021 #define GPIO_FUNC28_OEN_SEL (BIT(9)) 6022 #define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) 6023 #define GPIO_FUNC28_OEN_SEL_V 0x00000001U 6024 #define GPIO_FUNC28_OEN_SEL_S 9 6025 /** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 6026 * set this bit to invert output enable signal.1:invert.0:not invert. 6027 */ 6028 #define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) 6029 #define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) 6030 #define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U 6031 #define GPIO_FUNC28_OEN_INV_SEL_S 10 6032 6033 /** GPIO_FUNC29_OUT_SEL_CFG_REG register 6034 * GPIO output function select register 6035 */ 6036 #define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) 6037 /** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 6038 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 6039 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 6040 * GPIO_OUT_REG[n]. 6041 */ 6042 #define GPIO_FUNC29_OUT_SEL 0x000000FFU 6043 #define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) 6044 #define GPIO_FUNC29_OUT_SEL_V 0x000000FFU 6045 #define GPIO_FUNC29_OUT_SEL_S 0 6046 /** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 6047 * set this bit to invert output signal.1:invert.0:not invert. 6048 */ 6049 #define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) 6050 #define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) 6051 #define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U 6052 #define GPIO_FUNC29_OUT_INV_SEL_S 8 6053 /** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; 6054 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 6055 * enable signal.0:use peripheral output enable signal. 6056 */ 6057 #define GPIO_FUNC29_OEN_SEL (BIT(9)) 6058 #define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) 6059 #define GPIO_FUNC29_OEN_SEL_V 0x00000001U 6060 #define GPIO_FUNC29_OEN_SEL_S 9 6061 /** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 6062 * set this bit to invert output enable signal.1:invert.0:not invert. 6063 */ 6064 #define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) 6065 #define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) 6066 #define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U 6067 #define GPIO_FUNC29_OEN_INV_SEL_S 10 6068 6069 /** GPIO_FUNC30_OUT_SEL_CFG_REG register 6070 * GPIO output function select register 6071 */ 6072 #define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) 6073 /** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 6074 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 6075 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 6076 * GPIO_OUT_REG[n]. 6077 */ 6078 #define GPIO_FUNC30_OUT_SEL 0x000000FFU 6079 #define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) 6080 #define GPIO_FUNC30_OUT_SEL_V 0x000000FFU 6081 #define GPIO_FUNC30_OUT_SEL_S 0 6082 /** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 6083 * set this bit to invert output signal.1:invert.0:not invert. 6084 */ 6085 #define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) 6086 #define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) 6087 #define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U 6088 #define GPIO_FUNC30_OUT_INV_SEL_S 8 6089 /** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0; 6090 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 6091 * enable signal.0:use peripheral output enable signal. 6092 */ 6093 #define GPIO_FUNC30_OEN_SEL (BIT(9)) 6094 #define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) 6095 #define GPIO_FUNC30_OEN_SEL_V 0x00000001U 6096 #define GPIO_FUNC30_OEN_SEL_S 9 6097 /** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 6098 * set this bit to invert output enable signal.1:invert.0:not invert. 6099 */ 6100 #define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) 6101 #define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) 6102 #define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001U 6103 #define GPIO_FUNC30_OEN_INV_SEL_S 10 6104 6105 /** GPIO_FUNC31_OUT_SEL_CFG_REG register 6106 * GPIO output function select register 6107 */ 6108 #define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0) 6109 /** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 6110 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 6111 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 6112 * GPIO_OUT_REG[n]. 6113 */ 6114 #define GPIO_FUNC31_OUT_SEL 0x000000FFU 6115 #define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) 6116 #define GPIO_FUNC31_OUT_SEL_V 0x000000FFU 6117 #define GPIO_FUNC31_OUT_SEL_S 0 6118 /** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 6119 * set this bit to invert output signal.1:invert.0:not invert. 6120 */ 6121 #define GPIO_FUNC31_OUT_INV_SEL (BIT(8)) 6122 #define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) 6123 #define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U 6124 #define GPIO_FUNC31_OUT_INV_SEL_S 8 6125 /** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [9]; default: 0; 6126 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 6127 * enable signal.0:use peripheral output enable signal. 6128 */ 6129 #define GPIO_FUNC31_OEN_SEL (BIT(9)) 6130 #define GPIO_FUNC31_OEN_SEL_M (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S) 6131 #define GPIO_FUNC31_OEN_SEL_V 0x00000001U 6132 #define GPIO_FUNC31_OEN_SEL_S 9 6133 /** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 6134 * set this bit to invert output enable signal.1:invert.0:not invert. 6135 */ 6136 #define GPIO_FUNC31_OEN_INV_SEL (BIT(10)) 6137 #define GPIO_FUNC31_OEN_INV_SEL_M (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S) 6138 #define GPIO_FUNC31_OEN_INV_SEL_V 0x00000001U 6139 #define GPIO_FUNC31_OEN_INV_SEL_S 10 6140 6141 /** GPIO_FUNC32_OUT_SEL_CFG_REG register 6142 * GPIO output function select register 6143 */ 6144 #define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4) 6145 /** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 6146 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 6147 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 6148 * GPIO_OUT_REG[n]. 6149 */ 6150 #define GPIO_FUNC32_OUT_SEL 0x000000FFU 6151 #define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) 6152 #define GPIO_FUNC32_OUT_SEL_V 0x000000FFU 6153 #define GPIO_FUNC32_OUT_SEL_S 0 6154 /** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 6155 * set this bit to invert output signal.1:invert.0:not invert. 6156 */ 6157 #define GPIO_FUNC32_OUT_INV_SEL (BIT(8)) 6158 #define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) 6159 #define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001U 6160 #define GPIO_FUNC32_OUT_INV_SEL_S 8 6161 /** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [9]; default: 0; 6162 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 6163 * enable signal.0:use peripheral output enable signal. 6164 */ 6165 #define GPIO_FUNC32_OEN_SEL (BIT(9)) 6166 #define GPIO_FUNC32_OEN_SEL_M (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S) 6167 #define GPIO_FUNC32_OEN_SEL_V 0x00000001U 6168 #define GPIO_FUNC32_OEN_SEL_S 9 6169 /** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 6170 * set this bit to invert output enable signal.1:invert.0:not invert. 6171 */ 6172 #define GPIO_FUNC32_OEN_INV_SEL (BIT(10)) 6173 #define GPIO_FUNC32_OEN_INV_SEL_M (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S) 6174 #define GPIO_FUNC32_OEN_INV_SEL_V 0x00000001U 6175 #define GPIO_FUNC32_OEN_INV_SEL_S 10 6176 6177 /** GPIO_FUNC33_OUT_SEL_CFG_REG register 6178 * GPIO output function select register 6179 */ 6180 #define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8) 6181 /** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 6182 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 6183 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 6184 * GPIO_OUT_REG[n]. 6185 */ 6186 #define GPIO_FUNC33_OUT_SEL 0x000000FFU 6187 #define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) 6188 #define GPIO_FUNC33_OUT_SEL_V 0x000000FFU 6189 #define GPIO_FUNC33_OUT_SEL_S 0 6190 /** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 6191 * set this bit to invert output signal.1:invert.0:not invert. 6192 */ 6193 #define GPIO_FUNC33_OUT_INV_SEL (BIT(8)) 6194 #define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) 6195 #define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001U 6196 #define GPIO_FUNC33_OUT_INV_SEL_S 8 6197 /** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [9]; default: 0; 6198 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 6199 * enable signal.0:use peripheral output enable signal. 6200 */ 6201 #define GPIO_FUNC33_OEN_SEL (BIT(9)) 6202 #define GPIO_FUNC33_OEN_SEL_M (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S) 6203 #define GPIO_FUNC33_OEN_SEL_V 0x00000001U 6204 #define GPIO_FUNC33_OEN_SEL_S 9 6205 /** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 6206 * set this bit to invert output enable signal.1:invert.0:not invert. 6207 */ 6208 #define GPIO_FUNC33_OEN_INV_SEL (BIT(10)) 6209 #define GPIO_FUNC33_OEN_INV_SEL_M (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S) 6210 #define GPIO_FUNC33_OEN_INV_SEL_V 0x00000001U 6211 #define GPIO_FUNC33_OEN_INV_SEL_S 10 6212 6213 /** GPIO_FUNC34_OUT_SEL_CFG_REG register 6214 * GPIO output function select register 6215 */ 6216 #define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc) 6217 /** GPIO_FUNC34_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; 6218 * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: 6219 * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals 6220 * GPIO_OUT_REG[n]. 6221 */ 6222 #define GPIO_FUNC34_OUT_SEL 0x000000FFU 6223 #define GPIO_FUNC34_OUT_SEL_M (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S) 6224 #define GPIO_FUNC34_OUT_SEL_V 0x000000FFU 6225 #define GPIO_FUNC34_OUT_SEL_S 0 6226 /** GPIO_FUNC34_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; 6227 * set this bit to invert output signal.1:invert.0:not invert. 6228 */ 6229 #define GPIO_FUNC34_OUT_INV_SEL (BIT(8)) 6230 #define GPIO_FUNC34_OUT_INV_SEL_M (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S) 6231 #define GPIO_FUNC34_OUT_INV_SEL_V 0x00000001U 6232 #define GPIO_FUNC34_OUT_INV_SEL_S 8 6233 /** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [9]; default: 0; 6234 * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output 6235 * enable signal.0:use peripheral output enable signal. 6236 */ 6237 #define GPIO_FUNC34_OEN_SEL (BIT(9)) 6238 #define GPIO_FUNC34_OEN_SEL_M (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S) 6239 #define GPIO_FUNC34_OEN_SEL_V 0x00000001U 6240 #define GPIO_FUNC34_OEN_SEL_S 9 6241 /** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; 6242 * set this bit to invert output enable signal.1:invert.0:not invert. 6243 */ 6244 #define GPIO_FUNC34_OEN_INV_SEL (BIT(10)) 6245 #define GPIO_FUNC34_OEN_INV_SEL_M (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S) 6246 #define GPIO_FUNC34_OEN_INV_SEL_V 0x00000001U 6247 #define GPIO_FUNC34_OEN_INV_SEL_S 10 6248 6249 /** GPIO_CLOCK_GATE_REG register 6250 * GPIO clock gate register 6251 */ 6252 #define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) 6253 /** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; 6254 * set this bit to enable GPIO clock gate 6255 */ 6256 #define GPIO_CLK_EN (BIT(0)) 6257 #define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) 6258 #define GPIO_CLK_EN_V 0x00000001U 6259 #define GPIO_CLK_EN_S 0 6260 6261 /** GPIO_DATE_REG register 6262 * GPIO version register 6263 */ 6264 #define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) 6265 /** GPIO_DATE : R/W; bitpos: [27:0]; default: 35655968; 6266 * version register 6267 */ 6268 #define GPIO_DATE 0x0FFFFFFFU 6269 #define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) 6270 #define GPIO_DATE_V 0x0FFFFFFFU 6271 #define GPIO_DATE_S 0 6272 6273 #ifdef __cplusplus 6274 } 6275 #endif 6276
