1 /* 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include "soc/soc.h" 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /*CLINT MINT*/ 14 #define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0) 15 /* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */ 16 /*description: .*/ 17 #define CLINT_CPU_MINT_SIP 0xFFFFFFFF 18 #define CLINT_CPU_MINT_SIP_M ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S)) 19 #define CLINT_CPU_MINT_SIP_V 0xFFFFFFFF 20 #define CLINT_CPU_MINT_SIP_S 0 21 22 #define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4) 23 /* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ 24 /*description: .*/ 25 #define CLINT_MINT_SAMPLING_MODE 0x00000003 26 #define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S)) 27 #define CLINT_MINT_SAMPLING_MODE_V 0x3 28 #define CLINT_MINT_SAMPLING_MODE_S 4 29 /* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ 30 /*description: */ 31 #define CLINT_MINT_COUNTER_OVERFLOW (BIT(3)) 32 #define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3)) 33 #define CLINT_MINT_COUNTER_OVERFLOW_V 0x1 34 #define CLINT_MINT_COUNTER_OVERFLOW_S 3 35 /* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ 36 /*description: */ 37 #define CLINT_MINT_TIMERINT_PENDING (BIT(2)) 38 #define CLINT_MINT_TIMERINT_PENDING_M (BIT(2)) 39 #define CLINT_MINT_TIMERINT_PENDING_V 0x1 40 #define CLINT_MINT_TIMERINT_PENDING_S 2 41 /* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 42 /*description: */ 43 #define CLINT_MINT_TIMERINT_EN (BIT(1)) 44 #define CLINT_MINT_TIMERINT_EN_M (BIT(1)) 45 #define CLINT_MINT_TIMERINT_EN_V 0x1 46 #define CLINT_MINT_TIMERINT_EN_S 1 47 /* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 48 /*description: */ 49 #define CLINT_MINT_COUNTER_EN (BIT(0)) 50 #define CLINT_MINT_COUNTER_EN_M (BIT(0)) 51 #define CLINT_MINT_COUNTER_EN_V 0x1 52 #define CLINT_MINT_COUNTER_EN_S 0 53 54 #define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0x8) 55 /* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 56 /*description: .*/ 57 #define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF 58 #define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S)) 59 #define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF 60 #define CLINT_CPU_MINT_MTIME_L_S 0 61 62 #define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xC) 63 /* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 64 /*description: .*/ 65 #define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF 66 #define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S)) 67 #define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF 68 #define CLINT_CPU_MINT_MTIME_H_S 0 69 70 #define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x10) 71 /* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 72 /*description: .*/ 73 #define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF 74 #define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S)) 75 #define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF 76 #define CLINT_CPU_MINT_MTIMECMP_L_S 0 77 78 #define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x14) 79 /* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 80 /*description: .*/ 81 #define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF 82 #define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S)) 83 #define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF 84 #define CLINT_CPU_MINT_MTIMECMP_H_S 0 85 86 /*CLINT UINT*/ 87 #define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0) 88 /* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */ 89 /*description: .*/ 90 #define CLINT_CPU_UINT_SIP 0xFFFFFFFF 91 #define CLINT_CPU_UINT_SIP_M ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S)) 92 #define CLINT_CPU_UINT_SIP_V 0xFFFFFFFF 93 #define CLINT_CPU_UINT_SIP_S 0 94 95 #define CLINT_UINT_TIMECTL_REG (DR_REG_CLINT_U_BASE + 0x4) 96 /* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ 97 /*description: .*/ 98 #define CLINT_UINT_SAMPLING_MODE 0x00000003 99 #define CLINT_UINT_SAMPLING_MODE_M ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S)) 100 #define CLINT_UINT_SAMPLING_MODE_V 0x3 101 #define CLINT_UINT_SAMPLING_MODE_S 4 102 /* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ 103 /*description: */ 104 #define CLINT_UINT_COUNTER_OVERFLOW (BIT(3)) 105 #define CLINT_UINT_COUNTER_OVERFLOW_M (BIT(3)) 106 #define CLINT_UINT_COUNTER_OVERFLOW_V 0x1 107 #define CLINT_UINT_COUNTER_OVERFLOW_S 3 108 /* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ 109 /*description: */ 110 #define CLINT_UINT_TIMERINT_PENDING (BIT(2)) 111 #define CLINT_UINT_TIMERINT_PENDING_M (BIT(2)) 112 #define CLINT_UINT_TIMERINT_PENDING_V 0x1 113 #define CLINT_UINT_TIMERINT_PENDING_S 2 114 /* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 115 /*description: */ 116 #define CLINT_UINT_TIMERINT_EN (BIT(1)) 117 #define CLINT_UINT_TIMERINT_EN_M (BIT(1)) 118 #define CLINT_UINT_TIMERINT_EN_V 0x1 119 #define CLINT_UINT_TIMERINT_EN_S 1 120 /* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 121 /*description: */ 122 #define CLINT_UINT_COUNTER_EN (BIT(0)) 123 #define CLINT_UINT_COUNTER_EN_M (BIT(0)) 124 #define CLINT_UINT_COUNTER_EN_V 0x1 125 #define CLINT_UINT_COUNTER_EN_S 0 126 127 #define CLINT_UINT_UTIME_L_REG (DR_REG_CLINT_U_BASE + 0x8) 128 /* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 129 /*description: .*/ 130 #define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF 131 #define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S)) 132 #define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF 133 #define CLINT_CPU_UINT_UTIME_L_S 0 134 135 #define CLINT_UINT_UTIME_H_REG (DR_REG_CLINT_U_BASE + 0xC) 136 /* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 137 /*description: .*/ 138 #define CLINT_CPU_UINT_UTIME_H 0xFFFFFFFF 139 #define CLINT_CPU_UINT_UTIME_H_M ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S)) 140 #define CLINT_CPU_UINT_UTIME_H_V 0xFFFFFFFF 141 #define CLINT_CPU_UINT_UTIME_H_S 0 142 143 #define CLINT_UINT_UTIMECMP_L_REG (DR_REG_CLINT_U_BASE + 0x10) 144 /* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 145 /*description: .*/ 146 #define CLINT_CPU_UINT_UTIMECMP_L 0xFFFFFFFF 147 #define CLINT_CPU_UINT_UTIMECMP_L_M ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S)) 148 #define CLINT_CPU_UINT_UTIMECMP_L_V 0xFFFFFFFF 149 #define CLINT_CPU_UINT_UTIMECMP_L_S 0 150 151 #define CLINT_UINT_UTIMECMP_H_REG (DR_REG_CLINT_U_BASE + 0x14) 152 /* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 153 /*description: .*/ 154 #define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF 155 #define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S)) 156 #define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF 157 #define CLINT_CPU_UINT_UTIMECMP_H_S 0 158 #ifdef __cplusplus 159 } 160 #endif 161
