1 /**
2  * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdint.h>
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 /** Group: Configure Register */
14 /** Type of saradc_ctrl register
15  *  digital saradc configure register
16  */
17 typedef union {
18     struct {
19         /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
20          *  select software enable saradc sample
21          */
22         uint32_t saradc_saradc_start_force:1;
23         /** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
24          *  software enable saradc sample
25          */
26         uint32_t saradc_saradc_start:1;
27         uint32_t reserved_2:4;
28         /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
29          *  SAR clock gated
30          */
31         uint32_t saradc_saradc_sar_clk_gated:1;
32         /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
33          *  SAR clock divider
34          */
35         uint32_t saradc_saradc_sar_clk_div:8;
36         /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
37          *  0 ~ 15 means length 1 ~ 16
38          */
39         uint32_t saradc_saradc_sar_patt_len:3;
40         uint32_t reserved_18:5;
41         /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
42          *  clear the pointer of pattern table for DIG ADC1 CTRL
43          */
44         uint32_t saradc_saradc_sar_patt_p_clear:1;
45         uint32_t reserved_24:3;
46         /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
47          *  force option to xpd sar blocks
48          */
49         uint32_t saradc_saradc_xpd_sar_force:2;
50         /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
51          *  enable saradc2 power detect driven func.
52          */
53         uint32_t saradc_saradc2_pwdet_drv:1;
54         /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
55          *  wait arbit signal stable after sar_done
56          */
57         uint32_t saradc_saradc_wait_arb_cycle:2;
58     };
59     uint32_t val;
60 } apb_saradc_ctrl_reg_t;
61 
62 /** Type of saradc_ctrl2 register
63  *  digital saradc configure register
64  */
65 typedef union {
66     struct {
67         /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
68          *  enable max meas num
69          */
70         uint32_t saradc_saradc_meas_num_limit:1;
71         /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
72          *  max conversion number
73          */
74         uint32_t saradc_saradc_max_meas_num:8;
75         /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
76          *  1: data to DIG ADC1 CTRL is inverted, otherwise not
77          */
78         uint32_t saradc_saradc_sar1_inv:1;
79         /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
80          *  1: data to DIG ADC2 CTRL is inverted, otherwise not
81          */
82         uint32_t saradc_saradc_sar2_inv:1;
83         uint32_t reserved_11:1;
84         /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
85          *  to set saradc timer target
86          */
87         uint32_t saradc_saradc_timer_target:12;
88         /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
89          *  to enable saradc timer trigger
90          */
91         uint32_t saradc_saradc_timer_en:1;
92         uint32_t reserved_25:7;
93     };
94     uint32_t val;
95 } apb_saradc_ctrl2_reg_t;
96 
97 /** Type of saradc_filter_ctrl1 register
98  *  digital saradc configure register
99  */
100 typedef union {
101     struct {
102         uint32_t reserved_0:26;
103         /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
104          *  Factor of saradc filter1
105          */
106         uint32_t saradc_apb_saradc_filter_factor1:3;
107         /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
108          *  Factor of saradc filter0
109          */
110         uint32_t saradc_apb_saradc_filter_factor0:3;
111     };
112     uint32_t val;
113 } apb_saradc_filter_ctrl1_reg_t;
114 
115 /** Type of saradc_fsm_wait register
116  *  digital saradc configure register
117  */
118 typedef union {
119     struct {
120         /** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8;
121          *  saradc_xpd_wait
122          */
123         uint32_t saradc_saradc_xpd_wait:8;
124         /** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8;
125          *  saradc_rstb_wait
126          */
127         uint32_t saradc_saradc_rstb_wait:8;
128         /** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255;
129          *  saradc_standby_wait
130          */
131         uint32_t saradc_saradc_standby_wait:8;
132         uint32_t reserved_24:8;
133     };
134     uint32_t val;
135 } apb_saradc_fsm_wait_reg_t;
136 
137 /** Type of saradc_sar1_status register
138  *  digital saradc configure register
139  */
140 typedef union {
141     struct {
142         /** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912;
143          *  saradc1 status about data and channel
144          */
145         uint32_t saradc_saradc_sar1_status:32;
146     };
147     uint32_t val;
148 } apb_saradc_sar1_status_reg_t;
149 
150 /** Type of saradc_sar2_status register
151  *  digital saradc configure register
152  */
153 typedef union {
154     struct {
155         /** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912;
156          *  saradc2 status about data and channel
157          */
158         uint32_t saradc_saradc_sar2_status:32;
159     };
160     uint32_t val;
161 } apb_saradc_sar2_status_reg_t;
162 
163 /** Type of saradc_sar_patt_tab1 register
164  *  digital saradc configure register
165  */
166 typedef union {
167     struct {
168         /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
169          *  item 0 ~ 3 for pattern table 1 (each item one byte)
170          */
171         uint32_t saradc_saradc_sar_patt_tab1:24;
172         uint32_t reserved_24:8;
173     };
174     uint32_t val;
175 } apb_saradc_sar_patt_tab1_reg_t;
176 
177 /** Type of saradc_sar_patt_tab2 register
178  *  digital saradc configure register
179  */
180 typedef union {
181     struct {
182         /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
183          *  Item 4 ~ 7 for pattern table 1 (each item one byte)
184          */
185         uint32_t saradc_saradc_sar_patt_tab2:24;
186         uint32_t reserved_24:8;
187     };
188     uint32_t val;
189 } apb_saradc_sar_patt_tab2_reg_t;
190 
191 /** Type of saradc_onetime_sample register
192  *  digital saradc configure register
193  */
194 typedef union {
195     struct {
196         uint32_t reserved_0:23;
197         /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
198          *  configure onetime atten
199          */
200         uint32_t saradc_saradc_onetime_atten:2;
201         /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
202          *  configure onetime channel
203          */
204         uint32_t saradc_saradc_onetime_channel:4;
205         /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
206          *  trigger adc onetime sample
207          */
208         uint32_t saradc_saradc_onetime_start:1;
209         /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
210          *  enable adc2 onetime sample
211          */
212         uint32_t saradc_saradc2_onetime_sample:1;
213         /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
214          *  enable adc1 onetime sample
215          */
216         uint32_t saradc_saradc1_onetime_sample:1;
217     };
218     uint32_t val;
219 } apb_saradc_onetime_sample_reg_t;
220 
221 /** Type of saradc_arb_ctrl register
222  *  digital saradc configure register
223  */
224 typedef union {
225     struct {
226         uint32_t reserved_0:2;
227         /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
228          *  adc2 arbiter force to enableapb controller
229          */
230         uint32_t saradc_adc_arb_apb_force:1;
231         /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
232          *  adc2 arbiter force to enable rtc controller
233          */
234         uint32_t saradc_adc_arb_rtc_force:1;
235         /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
236          *  adc2 arbiter force to enable wifi controller
237          */
238         uint32_t saradc_adc_arb_wifi_force:1;
239         /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
240          *  adc2 arbiter force grant
241          */
242         uint32_t saradc_adc_arb_grant_force:1;
243         /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
244          *  Set adc2 arbiterapb priority
245          */
246         uint32_t saradc_adc_arb_apb_priority:2;
247         /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
248          *  Set adc2 arbiter rtc priority
249          */
250         uint32_t saradc_adc_arb_rtc_priority:2;
251         /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
252          *  Set adc2 arbiter wifi priority
253          */
254         uint32_t saradc_adc_arb_wifi_priority:2;
255         /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
256          *  adc2 arbiter uses fixed priority
257          */
258         uint32_t saradc_adc_arb_fix_priority:1;
259         uint32_t reserved_13:19;
260     };
261     uint32_t val;
262 } apb_saradc_arb_ctrl_reg_t;
263 
264 /** Type of saradc_filter_ctrl0 register
265  *  digital saradc configure register
266  */
267 typedef union {
268     struct {
269         uint32_t reserved_0:18;
270         /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
271          *  configure filter1 to adc channel
272          */
273         uint32_t saradc_apb_saradc_filter_channel1:4;
274         /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
275          *  configure filter0 to adc channel
276          */
277         uint32_t saradc_apb_saradc_filter_channel0:4;
278         uint32_t reserved_26:5;
279         /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
280          *  enable apb_adc1_filter
281          */
282         uint32_t saradc_apb_saradc_filter_reset:1;
283     };
284     uint32_t val;
285 } apb_saradc_filter_ctrl0_reg_t;
286 
287 /** Type of saradc_sar1data_status register
288  *  digital saradc configure register
289  */
290 typedef union {
291     struct {
292         /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
293          *  saradc1 data
294          */
295         uint32_t saradc_apb_saradc1_data:17;
296         uint32_t reserved_17:15;
297     };
298     uint32_t val;
299 } apb_saradc_sar1data_status_reg_t;
300 
301 /** Type of saradc_sar2data_status register
302  *  digital saradc configure register
303  */
304 typedef union {
305     struct {
306         /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
307          *  saradc2 data
308          */
309         uint32_t saradc_apb_saradc2_data:17;
310         uint32_t reserved_17:15;
311     };
312     uint32_t val;
313 } apb_saradc_sar2data_status_reg_t;
314 
315 /** Type of saradc_thres0_ctrl register
316  *  digital saradc configure register
317  */
318 typedef union {
319     struct {
320         /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
321          *  configure thres0 to adc channel
322          */
323         uint32_t saradc_apb_saradc_thres0_channel:4;
324         uint32_t reserved_4:1;
325         /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
326          *  saradc thres0 monitor thres
327          */
328         uint32_t saradc_apb_saradc_thres0_high:13;
329         /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
330          *  saradc thres0 monitor thres
331          */
332         uint32_t saradc_apb_saradc_thres0_low:13;
333         uint32_t reserved_31:1;
334     };
335     uint32_t val;
336 } apb_saradc_thres0_ctrl_reg_t;
337 
338 /** Type of saradc_thres1_ctrl register
339  *  digital saradc configure register
340  */
341 typedef union {
342     struct {
343         /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
344          *  configure thres1 to adc channel
345          */
346         uint32_t saradc_apb_saradc_thres1_channel:4;
347         uint32_t reserved_4:1;
348         /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
349          *  saradc thres1 monitor thres
350          */
351         uint32_t saradc_apb_saradc_thres1_high:13;
352         /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
353          *  saradc thres1 monitor thres
354          */
355         uint32_t saradc_apb_saradc_thres1_low:13;
356         uint32_t reserved_31:1;
357     };
358     uint32_t val;
359 } apb_saradc_thres1_ctrl_reg_t;
360 
361 /** Type of saradc_thres_ctrl register
362  *  digital saradc configure register
363  */
364 typedef union {
365     struct {
366         uint32_t reserved_0:27;
367         /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
368          *  enable thres to all channel
369          */
370         uint32_t saradc_apb_saradc_thres_all_en:1;
371         uint32_t reserved_28:2;
372         /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
373          *  enable thres1
374          */
375         uint32_t saradc_apb_saradc_thres1_en:1;
376         /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
377          *  enable thres0
378          */
379         uint32_t saradc_apb_saradc_thres0_en:1;
380     };
381     uint32_t val;
382 } apb_saradc_thres_ctrl_reg_t;
383 
384 /** Type of saradc_int_ena register
385  *  digital saradc int register
386  */
387 typedef union {
388     struct {
389         uint32_t reserved_0:25;
390         /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
391          *  tsens low  interrupt enable
392          */
393         uint32_t saradc_apb_saradc_tsens_int_ena:1;
394         /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
395          *  saradc thres1 low  interrupt enable
396          */
397         uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
398         /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
399          *  saradc thres0 low interrupt enable
400          */
401         uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
402         /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
403          *  saradc thres1 high interrupt enable
404          */
405         uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
406         /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
407          *  saradc thres0 high interrupt enable
408          */
409         uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
410         /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
411          *  saradc2 done interrupt enable
412          */
413         uint32_t saradc_apb_saradc2_done_int_ena:1;
414         /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
415          *  saradc1 done interrupt enable
416          */
417         uint32_t saradc_apb_saradc1_done_int_ena:1;
418     };
419     uint32_t val;
420 } apb_saradc_int_ena_reg_t;
421 
422 /** Type of saradc_int_raw register
423  *  digital saradc int register
424  */
425 typedef union {
426     struct {
427         uint32_t reserved_0:25;
428         /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
429          *  saradc tsens  interrupt raw
430          */
431         uint32_t saradc_apb_saradc_tsens_int_raw:1;
432         /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
433          *  saradc thres1 low  interrupt raw
434          */
435         uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
436         /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
437          *  saradc thres0 low interrupt raw
438          */
439         uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
440         /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
441          *  saradc thres1 high interrupt raw
442          */
443         uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
444         /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
445          *  saradc thres0 high interrupt raw
446          */
447         uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
448         /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
449          *  saradc2 done interrupt raw
450          */
451         uint32_t saradc_apb_saradc2_done_int_raw:1;
452         /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
453          *  saradc1 done interrupt raw
454          */
455         uint32_t saradc_apb_saradc1_done_int_raw:1;
456     };
457     uint32_t val;
458 } apb_saradc_int_raw_reg_t;
459 
460 /** Type of saradc_int_st register
461  *  digital saradc int register
462  */
463 typedef union {
464     struct {
465         uint32_t reserved_0:25;
466         /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
467          *  saradc tsens  interrupt state
468          */
469         uint32_t saradc_apb_saradc_tsens_int_st:1;
470         /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
471          *  saradc thres1 low  interrupt state
472          */
473         uint32_t saradc_apb_saradc_thres1_low_int_st:1;
474         /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
475          *  saradc thres0 low interrupt state
476          */
477         uint32_t saradc_apb_saradc_thres0_low_int_st:1;
478         /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
479          *  saradc thres1 high interrupt state
480          */
481         uint32_t saradc_apb_saradc_thres1_high_int_st:1;
482         /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
483          *  saradc thres0 high interrupt state
484          */
485         uint32_t saradc_apb_saradc_thres0_high_int_st:1;
486         /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
487          *  saradc2 done interrupt state
488          */
489         uint32_t saradc_apb_saradc2_done_int_st:1;
490         /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
491          *  saradc1 done interrupt state
492          */
493         uint32_t saradc_apb_saradc1_done_int_st:1;
494     };
495     uint32_t val;
496 } apb_saradc_int_st_reg_t;
497 
498 /** Type of saradc_int_clr register
499  *  digital saradc int register
500  */
501 typedef union {
502     struct {
503         uint32_t reserved_0:25;
504         /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
505          *  saradc tsens  interrupt clear
506          */
507         uint32_t saradc_apb_saradc_tsens_int_clr:1;
508         /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
509          *  saradc thres1 low  interrupt clear
510          */
511         uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
512         /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
513          *  saradc thres0 low interrupt clear
514          */
515         uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
516         /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
517          *  saradc thres1 high interrupt clear
518          */
519         uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
520         /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
521          *  saradc thres0 high interrupt clear
522          */
523         uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
524         /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
525          *  saradc2 done interrupt clear
526          */
527         uint32_t saradc_apb_saradc2_done_int_clr:1;
528         /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
529          *  saradc1 done interrupt clear
530          */
531         uint32_t saradc_apb_saradc1_done_int_clr:1;
532     };
533     uint32_t val;
534 } apb_saradc_int_clr_reg_t;
535 
536 /** Type of saradc_dma_conf register
537  *  digital saradc configure register
538  */
539 typedef union {
540     struct {
541         /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
542          *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
543          */
544         uint32_t saradc_apb_adc_eof_num:16;
545         uint32_t reserved_16:14;
546         /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
547          *  reset_apb_adc_state
548          */
549         uint32_t saradc_apb_adc_reset_fsm:1;
550         /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
551          *  enable apb_adc use spi_dma
552          */
553         uint32_t saradc_apb_adc_trans:1;
554     };
555     uint32_t val;
556 } apb_saradc_dma_conf_reg_t;
557 
558 /** Type of saradc_clkm_conf register
559  *  digital saradc configure register
560  */
561 typedef union {
562     struct {
563         /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
564          *  Integral I2S clock divider value
565          */
566         uint32_t saradc_clkm_div_num:8;
567         /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
568          *  Fractional clock divider numerator value
569          */
570         uint32_t saradc_clkm_div_b:6;
571         /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
572          *  Fractional clock divider denominator value
573          */
574         uint32_t saradc_clkm_div_a:6;
575         /** saradc_clk_en : R/W; bitpos: [20]; default: 0;
576          *  reg clk en
577          */
578         uint32_t saradc_clk_en:1;
579         /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
580          *  Set this bit to enable clk_apll
581          */
582         uint32_t saradc_clk_sel:2;
583         uint32_t reserved_23:9;
584     };
585     uint32_t val;
586 } apb_saradc_clkm_conf_reg_t;
587 
588 /** Type of saradc_apb_tsens_ctrl register
589  *  digital tsens configure register
590  */
591 typedef union {
592     struct {
593         /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
594          *  temperature sensor data out
595          */
596         uint32_t saradc_tsens_out:8;
597         uint32_t reserved_8:5;
598         /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
599          *  invert temperature sensor data
600          */
601         uint32_t saradc_tsens_in_inv:1;
602         /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
603          *  temperature sensor clock divider
604          */
605         uint32_t saradc_tsens_clk_div:8;
606         /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
607          *  temperature sensor power up
608          */
609         uint32_t saradc_tsens_pu:1;
610         uint32_t reserved_23:9;
611     };
612     uint32_t val;
613 } apb_saradc_apb_tsens_ctrl_reg_t;
614 
615 /** Type of saradc_tsens_ctrl2 register
616  *  digital tsens configure register
617  */
618 typedef union {
619     struct {
620         /** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2;
621          *  the time that power up tsens need wait
622          */
623         uint32_t saradc_tsens_xpd_wait:12;
624         /** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0;
625          *  force power up tsens
626          */
627         uint32_t saradc_tsens_xpd_force:2;
628         /** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1;
629          *  inv tsens clk
630          */
631         uint32_t saradc_tsens_clk_inv:1;
632         /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
633          *  tsens clk select
634          */
635         uint32_t saradc_tsens_clk_sel:1;
636         uint32_t reserved_16:16;
637     };
638     uint32_t val;
639 } apb_saradc_tsens_ctrl2_reg_t;
640 
641 /** Type of saradc_cali register
642  *  digital saradc configure register
643  */
644 typedef union {
645     struct {
646         /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
647          *  saradc cali factor
648          */
649         uint32_t saradc_apb_saradc_cali_cfg:17;
650         uint32_t reserved_17:15;
651     };
652     uint32_t val;
653 } apb_saradc_cali_reg_t;
654 
655 /** Type of tsens_wake register
656  *  digital tsens configure register
657  */
658 typedef union {
659     struct {
660         /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
661          *  reg_wakeup_th_low
662          */
663         uint32_t saradc_wakeup_th_low:8;
664         /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
665          *  reg_wakeup_th_high
666          */
667         uint32_t saradc_wakeup_th_high:8;
668         /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
669          *  reg_wakeup_over_upper_th
670          */
671         uint32_t saradc_wakeup_over_upper_th:1;
672         /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
673          *  reg_wakeup_mode
674          */
675         uint32_t saradc_wakeup_mode:1;
676         /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
677          *  reg_wakeup_en
678          */
679         uint32_t saradc_wakeup_en:1;
680         uint32_t reserved_19:13;
681     };
682     uint32_t val;
683 } apb_tsens_wake_reg_t;
684 
685 /** Type of tsens_sample register
686  *  digital tsens configure register
687  */
688 typedef union {
689     struct {
690         /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
691          *  HW sample rate
692          */
693         uint32_t saradc_tsens_sample_rate:16;
694         /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
695          *  HW sample en
696          */
697         uint32_t saradc_tsens_sample_en:1;
698         uint32_t reserved_17:15;
699     };
700     uint32_t val;
701 } apb_tsens_sample_reg_t;
702 
703 /** Type of saradc_ctrl_date register
704  *  version
705  */
706 typedef union {
707     struct {
708         /** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
709          *  version
710          */
711         uint32_t saradc_date:32;
712     };
713     uint32_t val;
714 } apb_saradc_ctrl_date_reg_t;
715 
716 
717 typedef struct apb_dev_t {
718     volatile apb_saradc_ctrl_reg_t saradc_ctrl;
719     volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
720     volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
721     volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait;
722     volatile apb_saradc_sar1_status_reg_t saradc_sar1_status;
723     volatile apb_saradc_sar2_status_reg_t saradc_sar2_status;
724     volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
725     volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
726     volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
727     volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
728     volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
729     volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
730     volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
731     volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
732     volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
733     volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
734     volatile apb_saradc_int_ena_reg_t saradc_int_ena;
735     volatile apb_saradc_int_raw_reg_t saradc_int_raw;
736     volatile apb_saradc_int_st_reg_t saradc_int_st;
737     volatile apb_saradc_int_clr_reg_t saradc_int_clr;
738     volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
739     volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
740     volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
741     volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
742     volatile apb_saradc_cali_reg_t saradc_cali;
743     volatile apb_tsens_wake_reg_t tsens_wake;
744     volatile apb_tsens_sample_reg_t tsens_sample;
745     uint32_t reserved_06c[228];
746     volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
747 } apb_dev_t;
748 
749 extern apb_dev_t APB_SARADC;
750 
751 #ifndef __cplusplus
752 _Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
753 #endif
754 
755 #ifdef __cplusplus
756 }
757 #endif
758