1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #include "soc/interrupts.h"
16 
17 const char *const esp_isr_names[] = {
18     [0] = "WIFI_MAC",
19     [1] = "WIFI_MAC_NMI",
20     [2] = "WIFI_PWR",
21     [3] = "WIFI_BB",
22     [4] = "BT_MAC",
23     [5] = "BT_BB",
24     [6] = "BT_BB_NMI",
25     [7] = "RWBT",
26     [8] = "RWBLE",
27     [9] = "RWBT_NMI",
28     [10] = "RWBLE_NMI",
29     [11] = "I2C_MASTER",
30     [12] = "SLC0",
31     [13] = "SLC1",
32     [14] = "APB_CTRL",
33     [15] = "UHCI0",
34     [16] = "GPIO",
35     [17] = "GPIO_NMI",
36     [18] = "SPI1",
37     [19] = "SPI2",
38     [20] = "I2S1",
39     [21] = "UART0",
40     [22] = "UART1",
41     [23] = "LEDC",
42     [24] = "EFUSE",
43     [25] = "TWAI",
44     [26] = "USB",
45     [27] = "RTC_CORE",
46     [28] = "RMT",
47     [29] = "I2C_EXT0",
48     [30] = "TIMER1",
49     [31] = "TIMER2",
50     [32] = "TG0_T0_LEVEL",
51     [33] = "TG0_WDT_LEVEL",
52     [34] = "TG1_T0_LEVEL",
53     [35] = "TG1_WDT_LEVEL",
54     [36] = "CACHE_IA",
55     [37] = "SYSTIMER_TARGET0_EDGE",
56     [38] = "SYSTIMER_TARGET1_EDGE",
57     [39] = "SYSTIMER_TARGET2_EDGE",
58     [40] = "SPI_MEM_REJECT_CACHE",
59     [41] = "ICACHE_PRELOAD0",
60     [42] = "ICACHE_SYNC0",
61     [43] = "APB_ADC",
62     [44] = "DMA_CH0",
63     [45] = "DMA_CH1",
64     [46] = "DMA_CH2",
65     [47] = "RSA",
66     [48] = "AES",
67     [49] = "SHA",
68     [50] = "FROM_CPU_INTR0",
69     [51] = "FROM_CPU_INTR1",
70     [52] = "FROM_CPU_INTR2",
71     [53] = "FROM_CPU_INTR3",
72     [54] = "ASSIST_DEBUG",
73     [55] = "DMA_APBPERI_PMS",
74     [56] = "CORE0_IRAM0_PMS",
75     [57] = "CORE0_DRAM0_PMS",
76     [58] = "CORE0_PIF_PMS",
77     [59] = "CORE0_PIF_PMS_SIZE",
78     [60] = "BAK_PMS_VIOLATE",
79     [61] = "CACHE_CORE0_ACS",
80 };
81