1 /** 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_SYSCON_REG_H_ 7 #define _SOC_SYSCON_REG_H_ 8 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #include "soc.h" 14 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) 15 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ 16 /*description: */ 17 #define SYSCON_RST_TICK_CNT (BIT(12)) 18 #define SYSCON_RST_TICK_CNT_M (BIT(12)) 19 #define SYSCON_RST_TICK_CNT_V 0x1 20 #define SYSCON_RST_TICK_CNT_S 12 21 /* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 22 /*description: */ 23 #define SYSCON_CLK_EN (BIT(11)) 24 #define SYSCON_CLK_EN_M (BIT(11)) 25 #define SYSCON_CLK_EN_V 0x1 26 #define SYSCON_CLK_EN_S 11 27 /* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 28 /*description: */ 29 #define SYSCON_CLK_320M_EN (BIT(10)) 30 #define SYSCON_CLK_320M_EN_M (BIT(10)) 31 #define SYSCON_CLK_320M_EN_V 0x1 32 #define SYSCON_CLK_320M_EN_S 10 33 /* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 34 /*description: */ 35 #define SYSCON_PRE_DIV_CNT 0x000003FF 36 #define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) 37 #define SYSCON_PRE_DIV_CNT_V 0x3FF 38 #define SYSCON_PRE_DIV_CNT_S 0 39 40 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) 41 /* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ 42 /*description: */ 43 #define SYSCON_TICK_ENABLE (BIT(16)) 44 #define SYSCON_TICK_ENABLE_M (BIT(16)) 45 #define SYSCON_TICK_ENABLE_V 0x1 46 #define SYSCON_TICK_ENABLE_S 16 47 /* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ 48 /*description: */ 49 #define SYSCON_CK8M_TICK_NUM 0x000000FF 50 #define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) 51 #define SYSCON_CK8M_TICK_NUM_V 0xFF 52 #define SYSCON_CK8M_TICK_NUM_S 8 53 /* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ 54 /*description: */ 55 #define SYSCON_XTAL_TICK_NUM 0x000000FF 56 #define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) 57 #define SYSCON_XTAL_TICK_NUM_V 0xFF 58 #define SYSCON_XTAL_TICK_NUM_S 0 59 60 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) 61 /* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 62 /*description: */ 63 #define SYSCON_CLK_XTAL_OEN (BIT(10)) 64 #define SYSCON_CLK_XTAL_OEN_M (BIT(10)) 65 #define SYSCON_CLK_XTAL_OEN_V 0x1 66 #define SYSCON_CLK_XTAL_OEN_S 10 67 /* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 68 /*description: */ 69 #define SYSCON_CLK40X_BB_OEN (BIT(9)) 70 #define SYSCON_CLK40X_BB_OEN_M (BIT(9)) 71 #define SYSCON_CLK40X_BB_OEN_V 0x1 72 #define SYSCON_CLK40X_BB_OEN_S 9 73 /* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ 74 /*description: */ 75 #define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) 76 #define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) 77 #define SYSCON_CLK_DAC_CPU_OEN_V 0x1 78 #define SYSCON_CLK_DAC_CPU_OEN_S 8 79 /* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 80 /*description: */ 81 #define SYSCON_CLK_ADC_INF_OEN (BIT(7)) 82 #define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) 83 #define SYSCON_CLK_ADC_INF_OEN_V 0x1 84 #define SYSCON_CLK_ADC_INF_OEN_S 7 85 /* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 86 /*description: */ 87 #define SYSCON_CLK_320M_OEN (BIT(6)) 88 #define SYSCON_CLK_320M_OEN_M (BIT(6)) 89 #define SYSCON_CLK_320M_OEN_V 0x1 90 #define SYSCON_CLK_320M_OEN_S 6 91 /* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 92 /*description: */ 93 #define SYSCON_CLK160_OEN (BIT(5)) 94 #define SYSCON_CLK160_OEN_M (BIT(5)) 95 #define SYSCON_CLK160_OEN_V 0x1 96 #define SYSCON_CLK160_OEN_S 5 97 /* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 98 /*description: */ 99 #define SYSCON_CLK80_OEN (BIT(4)) 100 #define SYSCON_CLK80_OEN_M (BIT(4)) 101 #define SYSCON_CLK80_OEN_V 0x1 102 #define SYSCON_CLK80_OEN_S 4 103 /* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 104 /*description: */ 105 #define SYSCON_CLK_BB_OEN (BIT(3)) 106 #define SYSCON_CLK_BB_OEN_M (BIT(3)) 107 #define SYSCON_CLK_BB_OEN_V 0x1 108 #define SYSCON_CLK_BB_OEN_S 3 109 /* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 110 /*description: */ 111 #define SYSCON_CLK44_OEN (BIT(2)) 112 #define SYSCON_CLK44_OEN_M (BIT(2)) 113 #define SYSCON_CLK44_OEN_V 0x1 114 #define SYSCON_CLK44_OEN_S 2 115 /* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 116 /*description: */ 117 #define SYSCON_CLK22_OEN (BIT(1)) 118 #define SYSCON_CLK22_OEN_M (BIT(1)) 119 #define SYSCON_CLK22_OEN_V 0x1 120 #define SYSCON_CLK22_OEN_S 1 121 /* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 122 /*description: */ 123 #define SYSCON_CLK20_OEN (BIT(0)) 124 #define SYSCON_CLK20_OEN_M (BIT(0)) 125 #define SYSCON_CLK20_OEN_V 0x1 126 #define SYSCON_CLK20_OEN_S 0 127 128 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) 129 /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 130 /*description: */ 131 #define SYSCON_WIFI_BB_CFG 0xFFFFFFFF 132 #define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) 133 #define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF 134 #define SYSCON_WIFI_BB_CFG_S 0 135 136 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010) 137 /* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 138 /*description: */ 139 #define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF 140 #define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) 141 #define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF 142 #define SYSCON_WIFI_BB_CFG_2_S 0 143 144 #define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014) 145 /* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 146 /*description: */ 147 #define SYSCON_WIFI_CLK_EN 0xFFFFFFFF 148 #define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) 149 #define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF 150 #define SYSCON_WIFI_CLK_EN_S 0 151 152 #define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018) 153 /* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 154 /*description: */ 155 #define SYSCON_WIFI_RST 0xFFFFFFFF 156 #define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) 157 #define SYSCON_WIFI_RST_V 0xFFFFFFFF 158 #define SYSCON_WIFI_RST_S 0 159 160 #define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG 161 /* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 162 /*description: */ 163 #define SYSTEM_WIFI_CLK_EN 0x00FB9FCF 164 #define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S)) 165 #define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF 166 #define SYSTEM_WIFI_CLK_EN_S 0 167 168 /* Mask for all Wifi clock bits, 6 */ 169 #define SYSTEM_WIFI_CLK_WIFI_EN 0x0 170 #define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) 171 #define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 172 #define SYSTEM_WIFI_CLK_WIFI_EN_S 0 173 /* Mask for all Bluetooth clock bits, 11, 16, 17 */ 174 #define SYSTEM_WIFI_CLK_BT_EN 0x0 175 #define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) 176 #define SYSTEM_WIFI_CLK_BT_EN_V 0x0 177 #define SYSTEM_WIFI_CLK_BT_EN_S 0 178 /* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ 179 #define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F 180 181 /* Digital team to check */ 182 //bluetooth baseband bit11 183 #define SYSTEM_BT_BASEBAND_EN BIT(11) 184 //bluetooth LC bit16 and bit17 185 #define SYSTEM_BT_LC_EN (BIT(16)|BIT(17)) 186 187 /* Remaining single bit clock masks */ 188 #define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4) 189 #define SYSTEM_WIFI_CLK_I2C_CLK_EN BIT(5) 190 #define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) 191 #define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) 192 #define SYSTEM_WIFI_CLK_RNG_EN BIT(15) 193 194 #define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG 195 #define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG 196 197 /* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 198 /*description: */ 199 #define SYSTEM_WIFIBB_RST BIT(0) 200 #define SYSTEM_FE_RST BIT(1) 201 #define SYSTEM_WIFIMAC_RST BIT(2) 202 #define SYSTEM_BTBB_RST BIT(3) /* Bluetooth Baseband */ 203 #define SYSTEM_BTMAC_RST BIT(4) /* deprecated */ 204 #define SYSTEM_SDIO_RST BIT(5) 205 #define SYSTEM_EMAC_RST BIT(7) 206 #define SYSTEM_MACPWR_RST BIT(8) 207 #define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */ 208 #define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */ 209 #define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */ 210 #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ 211 #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ 212 213 #define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \ 214 SYSTEM_FE_RST | \ 215 SYSTEM_WIFIMAC_RST | \ 216 SYSTEM_BTBB_RST | \ 217 SYSTEM_BTMAC_RST | \ 218 SYSTEM_RW_BTMAC_RST | \ 219 SYSTEM_RW_BTMAC_REG_RST | \ 220 SYSTEM_BTBB_REG_RST) 221 222 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) 223 /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 224 /*description: */ 225 #define SYSCON_PERI_IO_SWAP 0x000000FF 226 #define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) 227 #define SYSCON_PERI_IO_SWAP_V 0xFF 228 #define SYSCON_PERI_IO_SWAP_S 0 229 230 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020) 231 /* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 232 /*description: */ 233 #define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) 234 #define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) 235 #define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 236 #define SYSCON_EXT_MEM_PMS_LOCK_S 0 237 238 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028) 239 /* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 240 /*description: */ 241 #define SYSCON_FLASH_ACE0_ATTR 0x00000003 242 #define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) 243 #define SYSCON_FLASH_ACE0_ATTR_V 0x3 244 #define SYSCON_FLASH_ACE0_ATTR_S 0 245 246 #define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C) 247 /* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 248 /*description: */ 249 #define SYSCON_FLASH_ACE1_ATTR 0x00000003 250 #define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) 251 #define SYSCON_FLASH_ACE1_ATTR_V 0x3 252 #define SYSCON_FLASH_ACE1_ATTR_S 0 253 254 #define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030) 255 /* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 256 /*description: */ 257 #define SYSCON_FLASH_ACE2_ATTR 0x00000003 258 #define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) 259 #define SYSCON_FLASH_ACE2_ATTR_V 0x3 260 #define SYSCON_FLASH_ACE2_ATTR_S 0 261 262 #define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034) 263 /* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 264 /*description: */ 265 #define SYSCON_FLASH_ACE3_ATTR 0x00000003 266 #define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) 267 #define SYSCON_FLASH_ACE3_ATTR_V 0x3 268 #define SYSCON_FLASH_ACE3_ATTR_S 0 269 270 #define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038) 271 /* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 272 /*description: */ 273 #define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF 274 #define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) 275 #define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF 276 #define SYSCON_FLASH_ACE0_ADDR_S_S 0 277 278 #define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C) 279 /* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */ 280 /*description: */ 281 #define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF 282 #define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) 283 #define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF 284 #define SYSCON_FLASH_ACE1_ADDR_S_S 0 285 286 #define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040) 287 /* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */ 288 /*description: */ 289 #define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF 290 #define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) 291 #define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF 292 #define SYSCON_FLASH_ACE2_ADDR_S_S 0 293 294 #define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044) 295 /* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */ 296 /*description: */ 297 #define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF 298 #define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) 299 #define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF 300 #define SYSCON_FLASH_ACE3_ADDR_S_S 0 301 302 #define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048) 303 /* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 304 /*description: */ 305 #define SYSCON_FLASH_ACE0_SIZE 0x00001FFF 306 #define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) 307 #define SYSCON_FLASH_ACE0_SIZE_V 0x1FFF 308 #define SYSCON_FLASH_ACE0_SIZE_S 0 309 310 #define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C) 311 /* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 312 /*description: */ 313 #define SYSCON_FLASH_ACE1_SIZE 0x00001FFF 314 #define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) 315 #define SYSCON_FLASH_ACE1_SIZE_V 0x1FFF 316 #define SYSCON_FLASH_ACE1_SIZE_S 0 317 318 #define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050) 319 /* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 320 /*description: */ 321 #define SYSCON_FLASH_ACE2_SIZE 0x00001FFF 322 #define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) 323 #define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF 324 #define SYSCON_FLASH_ACE2_SIZE_S 0 325 326 #define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054) 327 /* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 328 /*description: */ 329 #define SYSCON_FLASH_ACE3_SIZE 0x00001FFF 330 #define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) 331 #define SYSCON_FLASH_ACE3_SIZE_V 0x1FFF 332 #define SYSCON_FLASH_ACE3_SIZE_S 0 333 334 #define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088) 335 /* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ 336 /*description: */ 337 #define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F 338 #define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) 339 #define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F 340 #define SYSCON_SPI_MEM_REJECT_CDE_S 2 341 /* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 342 /*description: */ 343 #define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) 344 #define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) 345 #define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 346 #define SYSCON_SPI_MEM_REJECT_CLR_S 1 347 /* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ 348 /*description: */ 349 #define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) 350 #define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) 351 #define SYSCON_SPI_MEM_REJECT_INT_V 0x1 352 #define SYSCON_SPI_MEM_REJECT_INT_S 0 353 354 #define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C) 355 /* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 356 /*description: */ 357 #define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF 358 #define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) 359 #define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF 360 #define SYSCON_SPI_MEM_REJECT_ADDR_S 0 361 362 #define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090) 363 /* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 364 /*description: */ 365 #define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) 366 #define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) 367 #define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 368 #define SYSCON_SDIO_WIN_ACCESS_EN_S 0 369 370 #define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094) 371 /* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 372 /*description: */ 373 #define SYSCON_REDCY_ANDOR (BIT(31)) 374 #define SYSCON_REDCY_ANDOR_M (BIT(31)) 375 #define SYSCON_REDCY_ANDOR_V 0x1 376 #define SYSCON_REDCY_ANDOR_S 31 377 /* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 378 /*description: */ 379 #define SYSCON_REDCY_SIG0 0x7FFFFFFF 380 #define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) 381 #define SYSCON_REDCY_SIG0_V 0x7FFFFFFF 382 #define SYSCON_REDCY_SIG0_S 0 383 384 #define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098) 385 /* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 386 /*description: */ 387 #define SYSCON_REDCY_NANDOR (BIT(31)) 388 #define SYSCON_REDCY_NANDOR_M (BIT(31)) 389 #define SYSCON_REDCY_NANDOR_V 0x1 390 #define SYSCON_REDCY_NANDOR_S 31 391 /* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 392 /*description: */ 393 #define SYSCON_REDCY_SIG1 0x7FFFFFFF 394 #define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) 395 #define SYSCON_REDCY_SIG1_V 0x7FFFFFFF 396 #define SYSCON_REDCY_SIG1_S 0 397 398 #define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C) 399 /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 400 /*description: */ 401 #define SYSCON_DC_MEM_FORCE_PD (BIT(5)) 402 #define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) 403 #define SYSCON_DC_MEM_FORCE_PD_V 0x1 404 #define SYSCON_DC_MEM_FORCE_PD_S 5 405 /* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 406 /*description: */ 407 #define SYSCON_DC_MEM_FORCE_PU (BIT(4)) 408 #define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) 409 #define SYSCON_DC_MEM_FORCE_PU_V 0x1 410 #define SYSCON_DC_MEM_FORCE_PU_S 4 411 /* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 412 /*description: */ 413 #define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) 414 #define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) 415 #define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 416 #define SYSCON_PBUS_MEM_FORCE_PD_S 3 417 /* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 418 /*description: */ 419 #define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) 420 #define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) 421 #define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 422 #define SYSCON_PBUS_MEM_FORCE_PU_S 2 423 /* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 424 /*description: */ 425 #define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) 426 #define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) 427 #define SYSCON_AGC_MEM_FORCE_PD_V 0x1 428 #define SYSCON_AGC_MEM_FORCE_PD_S 1 429 /* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 430 /*description: */ 431 #define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) 432 #define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) 433 #define SYSCON_AGC_MEM_FORCE_PU_V 0x1 434 #define SYSCON_AGC_MEM_FORCE_PU_S 0 435 436 #define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0) 437 /* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 438 /*description: */ 439 #define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) 440 #define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) 441 #define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 442 #define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 443 /* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 444 /*description: */ 445 #define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF 446 #define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S)) 447 #define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF 448 #define SYSCON_RETENTION_LINK_ADDR_S 0 449 450 #define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A4) 451 /* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ 452 /*description: */ 453 #define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F 454 #define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) 455 #define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF 456 #define SYSCON_SRAM_CLKGATE_FORCE_ON_S 2 457 /* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ 458 /*description: */ 459 #define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000003 460 #define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) 461 #define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x3 462 #define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 463 464 #define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0A8) 465 /* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */ 466 /*description: */ 467 #define SYSCON_SRAM_POWER_DOWN 0x0000000F 468 #define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) 469 #define SYSCON_SRAM_POWER_DOWN_V 0xF 470 #define SYSCON_SRAM_POWER_DOWN_S 2 471 /* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 472 /*description: */ 473 #define SYSCON_ROM_POWER_DOWN 0x00000003 474 #define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) 475 #define SYSCON_ROM_POWER_DOWN_V 0x3 476 #define SYSCON_ROM_POWER_DOWN_S 0 477 478 #define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0AC) 479 /* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ 480 /*description: */ 481 #define SYSCON_SRAM_POWER_UP 0x0000000F 482 #define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) 483 #define SYSCON_SRAM_POWER_UP_V 0xF 484 #define SYSCON_SRAM_POWER_UP_S 2 485 /* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ 486 /*description: */ 487 #define SYSCON_ROM_POWER_UP 0x00000003 488 #define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) 489 #define SYSCON_ROM_POWER_UP_V 0x3 490 #define SYSCON_ROM_POWER_UP_S 0 491 492 #define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0x0B0) 493 /* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 494 /*description: */ 495 #define SYSCON_RND_DATA 0xFFFFFFFF 496 #define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S)) 497 #define SYSCON_RND_DATA_V 0xFFFFFFFF 498 #define SYSCON_RND_DATA_S 0 499 500 #define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0x0B4) 501 /* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 502 /*description: */ 503 #define SYSCON_PERI_BACKUP_ENA (BIT(31)) 504 #define SYSCON_PERI_BACKUP_ENA_M (BIT(31)) 505 #define SYSCON_PERI_BACKUP_ENA_V 0x1 506 #define SYSCON_PERI_BACKUP_ENA_S 31 507 /* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ 508 /*description: */ 509 #define SYSCON_PERI_BACKUP_TO_MEM (BIT(30)) 510 #define SYSCON_PERI_BACKUP_TO_MEM_M (BIT(30)) 511 #define SYSCON_PERI_BACKUP_TO_MEM_V 0x1 512 #define SYSCON_PERI_BACKUP_TO_MEM_S 30 513 /* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */ 514 /*description: */ 515 #define SYSCON_PERI_BACKUP_START (BIT(29)) 516 #define SYSCON_PERI_BACKUP_START_M (BIT(29)) 517 #define SYSCON_PERI_BACKUP_START_V 0x1 518 #define SYSCON_PERI_BACKUP_START_S 29 519 /* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ 520 /*description: */ 521 #define SYSCON_PERI_BACKUP_SIZE 0x000003FF 522 #define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S)) 523 #define SYSCON_PERI_BACKUP_SIZE_V 0x3FF 524 #define SYSCON_PERI_BACKUP_SIZE_S 19 525 /* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ 526 /*description: */ 527 #define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FF 528 #define SYSCON_PERI_BACKUP_TOUT_THRES_M ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S)) 529 #define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x3FF 530 #define SYSCON_PERI_BACKUP_TOUT_THRES_S 9 531 /* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ 532 /*description: */ 533 #define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001F 534 #define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S)) 535 #define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F 536 #define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4 537 /* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ 538 /*description: */ 539 #define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003 540 #define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S)) 541 #define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3 542 #define SYSCON_PERI_BACKUP_FLOW_ERR_S 1 543 544 #define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B8) 545 /* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 546 /*description: */ 547 #define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF 548 #define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S)) 549 #define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF 550 #define SYSCON_BACKUP_APB_START_ADDR_S 0 551 552 #define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC) 553 /* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 554 /*description: */ 555 #define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF 556 #define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S)) 557 #define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF 558 #define SYSCON_BACKUP_MEM_START_ADDR_S 0 559 560 #define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0C0) 561 /* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ 562 /*description: */ 563 #define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1)) 564 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) 565 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1 566 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1 567 /* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */ 568 /*description: */ 569 #define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0)) 570 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) 571 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1 572 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0 573 574 #define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0C4) 575 /* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ 576 /*description: */ 577 #define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1)) 578 #define SYSCON_PERI_BACKUP_ERR_INT_ST_M (BIT(1)) 579 #define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x1 580 #define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1 581 /* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ 582 /*description: */ 583 #define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0)) 584 #define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0)) 585 #define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1 586 #define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0 587 588 #define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0C8) 589 /* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ 590 /*description: */ 591 #define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1)) 592 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) 593 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x1 594 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1 595 /* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ 596 /*description: */ 597 #define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0)) 598 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) 599 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1 600 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0 601 602 #define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0D0) 603 /* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ 604 /*description: */ 605 #define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1)) 606 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) 607 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1 608 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1 609 /* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */ 610 /*description: */ 611 #define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0)) 612 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) 613 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1 614 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0 615 616 #define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) 617 /* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */ 618 /*description: Version control*/ 619 #define SYSCON_DATE 0xFFFFFFFF 620 #define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) 621 #define SYSCON_DATE_V 0xFFFFFFFF 622 #define SYSCON_DATE_S 0 623 624 #ifdef __cplusplus 625 } 626 #endif 627 628 629 630 #endif /*_SOC_SYSCON_REG_H_ */ 631
