1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_RTC_I2C_REG_H_ 15 #define _SOC_RTC_I2C_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) 23 /* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ 24 /*description: time period that scl = 0*/ 25 #define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF 26 #define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) 27 #define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF 28 #define RTC_I2C_SCL_LOW_PERIOD_S 0 29 30 #define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004) 31 /* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 32 /*description: rtc i2c reg clk gating*/ 33 #define RTC_I2C_CLK_EN (BIT(31)) 34 #define RTC_I2C_CLK_EN_M (BIT(31)) 35 #define RTC_I2C_CLK_EN_V 0x1 36 #define RTC_I2C_CLK_EN_S 31 37 /* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ 38 /*description: rtc i2c sw reset*/ 39 #define RTC_I2C_RESET (BIT(30)) 40 #define RTC_I2C_RESET_M (BIT(30)) 41 #define RTC_I2C_RESET_V 0x1 42 #define RTC_I2C_RESET_S 30 43 /* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ 44 /*description: */ 45 #define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) 46 #define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) 47 #define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 48 #define RTC_I2C_CTRL_CLK_GATE_EN_S 29 49 /* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 50 /*description: receive lsb first*/ 51 #define RTC_I2C_RX_LSB_FIRST (BIT(5)) 52 #define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) 53 #define RTC_I2C_RX_LSB_FIRST_V 0x1 54 #define RTC_I2C_RX_LSB_FIRST_S 5 55 /* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 56 /*description: transit lsb first*/ 57 #define RTC_I2C_TX_LSB_FIRST (BIT(4)) 58 #define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) 59 #define RTC_I2C_TX_LSB_FIRST_V 0x1 60 #define RTC_I2C_TX_LSB_FIRST_S 4 61 /* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */ 62 /*description: force start*/ 63 #define RTC_I2C_TRANS_START (BIT(3)) 64 #define RTC_I2C_TRANS_START_M (BIT(3)) 65 #define RTC_I2C_TRANS_START_V 0x1 66 #define RTC_I2C_TRANS_START_S 3 67 /* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 68 /*description: 1=master 0=slave*/ 69 #define RTC_I2C_MS_MODE (BIT(2)) 70 #define RTC_I2C_MS_MODE_M (BIT(2)) 71 #define RTC_I2C_MS_MODE_V 0x1 72 #define RTC_I2C_MS_MODE_S 2 73 /* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 74 /*description: 1=push pull 0=open drain*/ 75 #define RTC_I2C_SCL_FORCE_OUT (BIT(1)) 76 #define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) 77 #define RTC_I2C_SCL_FORCE_OUT_V 0x1 78 #define RTC_I2C_SCL_FORCE_OUT_S 1 79 /* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 80 /*description: 1=push pull 0=open drain*/ 81 #define RTC_I2C_SDA_FORCE_OUT (BIT(0)) 82 #define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) 83 #define RTC_I2C_SDA_FORCE_OUT_V 0x1 84 #define RTC_I2C_SDA_FORCE_OUT_S 0 85 86 #define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008) 87 /* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ 88 /*description: scl last status*/ 89 #define RTC_I2C_SCL_STATE_LAST 0x00000007 90 #define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S)) 91 #define RTC_I2C_SCL_STATE_LAST_V 0x7 92 #define RTC_I2C_SCL_STATE_LAST_S 28 93 /* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ 94 /*description: i2c last main status*/ 95 #define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 96 #define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S)) 97 #define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 98 #define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 99 /* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ 100 /*description: shifter content*/ 101 #define RTC_I2C_SHIFT 0x000000FF 102 #define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S)) 103 #define RTC_I2C_SHIFT_V 0xFF 104 #define RTC_I2C_SHIFT_S 16 105 /* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */ 106 /*description: which operation is working*/ 107 #define RTC_I2C_OP_CNT 0x00000003 108 #define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S)) 109 #define RTC_I2C_OP_CNT_V 0x3 110 #define RTC_I2C_OP_CNT_S 6 111 /* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */ 112 /*description: One byte transit done*/ 113 #define RTC_I2C_BYTE_TRANS (BIT(5)) 114 #define RTC_I2C_BYTE_TRANS_M (BIT(5)) 115 #define RTC_I2C_BYTE_TRANS_V 0x1 116 #define RTC_I2C_BYTE_TRANS_S 5 117 /* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */ 118 /*description: slave reg sub address*/ 119 #define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) 120 #define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) 121 #define RTC_I2C_SLAVE_ADDRESSED_V 0x1 122 #define RTC_I2C_SLAVE_ADDRESSED_S 4 123 /* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */ 124 /*description: bus is busy*/ 125 #define RTC_I2C_BUS_BUSY (BIT(3)) 126 #define RTC_I2C_BUS_BUSY_M (BIT(3)) 127 #define RTC_I2C_BUS_BUSY_V 0x1 128 #define RTC_I2C_BUS_BUSY_S 3 129 /* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */ 130 /*description: arbitration is lost*/ 131 #define RTC_I2C_ARB_LOST (BIT(2)) 132 #define RTC_I2C_ARB_LOST_M (BIT(2)) 133 #define RTC_I2C_ARB_LOST_V 0x1 134 #define RTC_I2C_ARB_LOST_S 2 135 /* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ 136 /*description: slave read or write*/ 137 #define RTC_I2C_SLAVE_RW (BIT(1)) 138 #define RTC_I2C_SLAVE_RW_M (BIT(1)) 139 #define RTC_I2C_SLAVE_RW_V 0x1 140 #define RTC_I2C_SLAVE_RW_S 1 141 /* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ 142 /*description: ack response*/ 143 #define RTC_I2C_ACK_REC (BIT(0)) 144 #define RTC_I2C_ACK_REC_M (BIT(0)) 145 #define RTC_I2C_ACK_REC_V 0x1 146 #define RTC_I2C_ACK_REC_S 0 147 148 #define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c) 149 /* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */ 150 /*description: time out threshold*/ 151 #define RTC_I2C_TIMEOUT 0x000FFFFF 152 #define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) 153 #define RTC_I2C_TIMEOUT_V 0xFFFFF 154 #define RTC_I2C_TIMEOUT_S 0 155 156 #define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010) 157 /* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 158 /*description: i2c 10bit mode enable*/ 159 #define RTC_I2C_ADDR_10BIT_EN (BIT(31)) 160 #define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) 161 #define RTC_I2C_ADDR_10BIT_EN_V 0x1 162 #define RTC_I2C_ADDR_10BIT_EN_S 31 163 /* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ 164 /*description: slave address*/ 165 #define RTC_I2C_SLAVE_ADDR 0x00007FFF 166 #define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) 167 #define RTC_I2C_SLAVE_ADDR_V 0x7FFF 168 #define RTC_I2C_SLAVE_ADDR_S 0 169 170 #define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014) 171 /* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ 172 /*description: time period that scl = 1*/ 173 #define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF 174 #define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) 175 #define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF 176 #define RTC_I2C_SCL_HIGH_PERIOD_S 0 177 178 #define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018) 179 /* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */ 180 /*description: time period for SDA to toggle after SCL goes low*/ 181 #define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF 182 #define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S)) 183 #define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF 184 #define RTC_I2C_SDA_DUTY_NUM_S 0 185 186 #define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c) 187 /* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ 188 /*description: time period for SCL to toggle after I2C start is triggered*/ 189 #define RTC_I2C_SCL_START_PERIOD 0x000FFFFF 190 #define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) 191 #define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF 192 #define RTC_I2C_SCL_START_PERIOD_S 0 193 194 #define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020) 195 /* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ 196 /*description: time period for SCL to stop after I2C end is triggered*/ 197 #define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF 198 #define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) 199 #define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF 200 #define RTC_I2C_SCL_STOP_PERIOD_S 0 201 202 #define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024) 203 /* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 204 /*description: clear detect start interrupt*/ 205 #define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) 206 #define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) 207 #define RTC_I2C_DETECT_START_INT_CLR_V 0x1 208 #define RTC_I2C_DETECT_START_INT_CLR_S 8 209 /* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 210 /*description: clear transit load data complete interrupt*/ 211 #define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) 212 #define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) 213 #define RTC_I2C_TX_DATA_INT_CLR_V 0x1 214 #define RTC_I2C_TX_DATA_INT_CLR_S 7 215 /* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 216 /*description: clear receive data interrupt*/ 217 #define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) 218 #define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) 219 #define RTC_I2C_RX_DATA_INT_CLR_V 0x1 220 #define RTC_I2C_RX_DATA_INT_CLR_S 6 221 /* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 222 /*description: clear ack error interrupt*/ 223 #define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) 224 #define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) 225 #define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 226 #define RTC_I2C_ACK_ERR_INT_CLR_S 5 227 /* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 228 /*description: clear time out interrupt*/ 229 #define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) 230 #define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) 231 #define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 232 #define RTC_I2C_TIMEOUT_INT_CLR_S 4 233 /* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 234 /*description: clear transit complete interrupt*/ 235 #define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) 236 #define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) 237 #define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 238 #define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 239 /* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 240 /*description: clear master transit complete interrupt*/ 241 #define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) 242 #define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) 243 #define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 244 #define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 245 /* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 246 /*description: clear arbitration lost interrupt*/ 247 #define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) 248 #define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) 249 #define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 250 #define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 251 /* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 252 /*description: clear slave transit complete interrupt*/ 253 #define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) 254 #define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) 255 #define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 256 #define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 257 258 #define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028) 259 /* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 260 /*description: detect start interrupt raw*/ 261 #define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) 262 #define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) 263 #define RTC_I2C_DETECT_START_INT_RAW_V 0x1 264 #define RTC_I2C_DETECT_START_INT_RAW_S 8 265 /* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 266 /*description: transit data interrupt raw*/ 267 #define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) 268 #define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) 269 #define RTC_I2C_TX_DATA_INT_RAW_V 0x1 270 #define RTC_I2C_TX_DATA_INT_RAW_S 7 271 /* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 272 /*description: receive data interrupt raw*/ 273 #define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) 274 #define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) 275 #define RTC_I2C_RX_DATA_INT_RAW_V 0x1 276 #define RTC_I2C_RX_DATA_INT_RAW_S 6 277 /* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 278 /*description: ack error interrupt raw*/ 279 #define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) 280 #define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) 281 #define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 282 #define RTC_I2C_ACK_ERR_INT_RAW_S 5 283 /* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 284 /*description: time out interrupt raw*/ 285 #define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) 286 #define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) 287 #define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 288 #define RTC_I2C_TIMEOUT_INT_RAW_S 4 289 /* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 290 /*description: transit complete interrupt raw*/ 291 #define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) 292 #define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) 293 #define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 294 #define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 295 /* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 296 /*description: master transit complete interrupt raw*/ 297 #define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) 298 #define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) 299 #define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 300 #define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 301 /* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 302 /*description: arbitration lost interrupt raw*/ 303 #define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) 304 #define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) 305 #define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 306 #define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 307 /* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 308 /*description: slave transit complete interrupt raw*/ 309 #define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) 310 #define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) 311 #define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 312 #define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 313 314 #define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c) 315 /* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 316 /*description: detect start interrupt state*/ 317 #define RTC_I2C_DETECT_START_INT_ST (BIT(8)) 318 #define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) 319 #define RTC_I2C_DETECT_START_INT_ST_V 0x1 320 #define RTC_I2C_DETECT_START_INT_ST_S 8 321 /* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 322 /*description: transit data interrupt state*/ 323 #define RTC_I2C_TX_DATA_INT_ST (BIT(7)) 324 #define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) 325 #define RTC_I2C_TX_DATA_INT_ST_V 0x1 326 #define RTC_I2C_TX_DATA_INT_ST_S 7 327 /* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 328 /*description: receive data interrupt state*/ 329 #define RTC_I2C_RX_DATA_INT_ST (BIT(6)) 330 #define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) 331 #define RTC_I2C_RX_DATA_INT_ST_V 0x1 332 #define RTC_I2C_RX_DATA_INT_ST_S 6 333 /* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 334 /*description: ack error interrupt state*/ 335 #define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) 336 #define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) 337 #define RTC_I2C_ACK_ERR_INT_ST_V 0x1 338 #define RTC_I2C_ACK_ERR_INT_ST_S 5 339 /* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 340 /*description: time out interrupt state*/ 341 #define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) 342 #define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) 343 #define RTC_I2C_TIMEOUT_INT_ST_V 0x1 344 #define RTC_I2C_TIMEOUT_INT_ST_S 4 345 /* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 346 /*description: transit complete interrupt state*/ 347 #define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) 348 #define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) 349 #define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 350 #define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 351 /* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 352 /*description: master transit complete interrupt state*/ 353 #define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) 354 #define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) 355 #define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 356 #define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 357 /* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 358 /*description: arbitration lost interrupt state*/ 359 #define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) 360 #define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) 361 #define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 362 #define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 363 /* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 364 /*description: slave transit complete interrupt state*/ 365 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) 366 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) 367 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 368 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 369 370 #define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030) 371 /* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 372 /*description: enable detect start interrupt*/ 373 #define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) 374 #define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) 375 #define RTC_I2C_DETECT_START_INT_ENA_V 0x1 376 #define RTC_I2C_DETECT_START_INT_ENA_S 8 377 /* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 378 /*description: enable transit data interrupt*/ 379 #define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) 380 #define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) 381 #define RTC_I2C_TX_DATA_INT_ENA_V 0x1 382 #define RTC_I2C_TX_DATA_INT_ENA_S 7 383 /* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 384 /*description: enable receive data interrupt*/ 385 #define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) 386 #define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) 387 #define RTC_I2C_RX_DATA_INT_ENA_V 0x1 388 #define RTC_I2C_RX_DATA_INT_ENA_S 6 389 /* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 390 /*description: enable eack error interrupt*/ 391 #define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) 392 #define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) 393 #define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 394 #define RTC_I2C_ACK_ERR_INT_ENA_S 5 395 /* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 396 /*description: enable time out interrupt*/ 397 #define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) 398 #define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) 399 #define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 400 #define RTC_I2C_TIMEOUT_INT_ENA_S 4 401 /* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 402 /*description: enable transit complete interrupt*/ 403 #define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) 404 #define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) 405 #define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 406 #define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 407 /* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 408 /*description: enable master transit complete interrupt*/ 409 #define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) 410 #define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) 411 #define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 412 #define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 413 /* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 414 /*description: enable arbitration lost interrupt*/ 415 #define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) 416 #define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) 417 #define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 418 #define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 419 /* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 420 /*description: enable slave transit complete interrupt*/ 421 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) 422 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) 423 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 424 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 425 426 #define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034) 427 /* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 428 /*description: i2c done*/ 429 #define RTC_I2C_DONE (BIT(31)) 430 #define RTC_I2C_DONE_M (BIT(31)) 431 #define RTC_I2C_DONE_V 0x1 432 #define RTC_I2C_DONE_S 31 433 /* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ 434 /*description: data sent by slave*/ 435 #define RTC_I2C_SLAVE_TX_DATA 0x000000FF 436 #define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S)) 437 #define RTC_I2C_SLAVE_TX_DATA_V 0xFF 438 #define RTC_I2C_SLAVE_TX_DATA_S 8 439 /* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */ 440 /*description: data received*/ 441 #define RTC_I2C_RDATA 0x000000FF 442 #define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S)) 443 #define RTC_I2C_RDATA_V 0xFF 444 #define RTC_I2C_RDATA_S 0 445 446 #define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038) 447 /* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 448 /*description: command0_done*/ 449 #define RTC_I2C_COMMAND0_DONE (BIT(31)) 450 #define RTC_I2C_COMMAND0_DONE_M (BIT(31)) 451 #define RTC_I2C_COMMAND0_DONE_V 0x1 452 #define RTC_I2C_COMMAND0_DONE_S 31 453 /* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ 454 /*description: command0*/ 455 #define RTC_I2C_COMMAND0 0x00003FFF 456 #define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S)) 457 #define RTC_I2C_COMMAND0_V 0x3FFF 458 #define RTC_I2C_COMMAND0_S 0 459 460 #define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c) 461 /* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 462 /*description: command1_done*/ 463 #define RTC_I2C_COMMAND1_DONE (BIT(31)) 464 #define RTC_I2C_COMMAND1_DONE_M (BIT(31)) 465 #define RTC_I2C_COMMAND1_DONE_V 0x1 466 #define RTC_I2C_COMMAND1_DONE_S 31 467 /* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ 468 /*description: command1*/ 469 #define RTC_I2C_COMMAND1 0x00003FFF 470 #define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S)) 471 #define RTC_I2C_COMMAND1_V 0x3FFF 472 #define RTC_I2C_COMMAND1_S 0 473 474 #define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040) 475 /* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 476 /*description: command2_done*/ 477 #define RTC_I2C_COMMAND2_DONE (BIT(31)) 478 #define RTC_I2C_COMMAND2_DONE_M (BIT(31)) 479 #define RTC_I2C_COMMAND2_DONE_V 0x1 480 #define RTC_I2C_COMMAND2_DONE_S 31 481 /* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */ 482 /*description: command2*/ 483 #define RTC_I2C_COMMAND2 0x00003FFF 484 #define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S)) 485 #define RTC_I2C_COMMAND2_V 0x3FFF 486 #define RTC_I2C_COMMAND2_S 0 487 488 #define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044) 489 /* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 490 /*description: command3_done*/ 491 #define RTC_I2C_COMMAND3_DONE (BIT(31)) 492 #define RTC_I2C_COMMAND3_DONE_M (BIT(31)) 493 #define RTC_I2C_COMMAND3_DONE_V 0x1 494 #define RTC_I2C_COMMAND3_DONE_S 31 495 /* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ 496 /*description: command3*/ 497 #define RTC_I2C_COMMAND3 0x00003FFF 498 #define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S)) 499 #define RTC_I2C_COMMAND3_V 0x3FFF 500 #define RTC_I2C_COMMAND3_S 0 501 502 #define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048) 503 /* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 504 /*description: command4_done*/ 505 #define RTC_I2C_COMMAND4_DONE (BIT(31)) 506 #define RTC_I2C_COMMAND4_DONE_M (BIT(31)) 507 #define RTC_I2C_COMMAND4_DONE_V 0x1 508 #define RTC_I2C_COMMAND4_DONE_S 31 509 /* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ 510 /*description: command4*/ 511 #define RTC_I2C_COMMAND4 0x00003FFF 512 #define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S)) 513 #define RTC_I2C_COMMAND4_V 0x3FFF 514 #define RTC_I2C_COMMAND4_S 0 515 516 #define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c) 517 /* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 518 /*description: command5_done*/ 519 #define RTC_I2C_COMMAND5_DONE (BIT(31)) 520 #define RTC_I2C_COMMAND5_DONE_M (BIT(31)) 521 #define RTC_I2C_COMMAND5_DONE_V 0x1 522 #define RTC_I2C_COMMAND5_DONE_S 31 523 /* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ 524 /*description: command5*/ 525 #define RTC_I2C_COMMAND5 0x00003FFF 526 #define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S)) 527 #define RTC_I2C_COMMAND5_V 0x3FFF 528 #define RTC_I2C_COMMAND5_S 0 529 530 #define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050) 531 /* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 532 /*description: command6_done*/ 533 #define RTC_I2C_COMMAND6_DONE (BIT(31)) 534 #define RTC_I2C_COMMAND6_DONE_M (BIT(31)) 535 #define RTC_I2C_COMMAND6_DONE_V 0x1 536 #define RTC_I2C_COMMAND6_DONE_S 31 537 /* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ 538 /*description: command6*/ 539 #define RTC_I2C_COMMAND6 0x00003FFF 540 #define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S)) 541 #define RTC_I2C_COMMAND6_V 0x3FFF 542 #define RTC_I2C_COMMAND6_S 0 543 544 #define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054) 545 /* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 546 /*description: command7_done*/ 547 #define RTC_I2C_COMMAND7_DONE (BIT(31)) 548 #define RTC_I2C_COMMAND7_DONE_M (BIT(31)) 549 #define RTC_I2C_COMMAND7_DONE_V 0x1 550 #define RTC_I2C_COMMAND7_DONE_S 31 551 /* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */ 552 /*description: command7*/ 553 #define RTC_I2C_COMMAND7 0x00003FFF 554 #define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S)) 555 #define RTC_I2C_COMMAND7_V 0x3FFF 556 #define RTC_I2C_COMMAND7_S 0 557 558 #define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058) 559 /* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 560 /*description: command8_done*/ 561 #define RTC_I2C_COMMAND8_DONE (BIT(31)) 562 #define RTC_I2C_COMMAND8_DONE_M (BIT(31)) 563 #define RTC_I2C_COMMAND8_DONE_V 0x1 564 #define RTC_I2C_COMMAND8_DONE_S 31 565 /* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ 566 /*description: command8*/ 567 #define RTC_I2C_COMMAND8 0x00003FFF 568 #define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S)) 569 #define RTC_I2C_COMMAND8_V 0x3FFF 570 #define RTC_I2C_COMMAND8_S 0 571 572 #define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c) 573 /* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 574 /*description: command9_done*/ 575 #define RTC_I2C_COMMAND9_DONE (BIT(31)) 576 #define RTC_I2C_COMMAND9_DONE_M (BIT(31)) 577 #define RTC_I2C_COMMAND9_DONE_V 0x1 578 #define RTC_I2C_COMMAND9_DONE_S 31 579 /* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ 580 /*description: command9*/ 581 #define RTC_I2C_COMMAND9 0x00003FFF 582 #define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S)) 583 #define RTC_I2C_COMMAND9_V 0x3FFF 584 #define RTC_I2C_COMMAND9_S 0 585 586 #define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060) 587 /* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 588 /*description: command10_done*/ 589 #define RTC_I2C_COMMAND10_DONE (BIT(31)) 590 #define RTC_I2C_COMMAND10_DONE_M (BIT(31)) 591 #define RTC_I2C_COMMAND10_DONE_V 0x1 592 #define RTC_I2C_COMMAND10_DONE_S 31 593 /* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ 594 /*description: command10*/ 595 #define RTC_I2C_COMMAND10 0x00003FFF 596 #define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S)) 597 #define RTC_I2C_COMMAND10_V 0x3FFF 598 #define RTC_I2C_COMMAND10_S 0 599 600 #define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064) 601 /* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 602 /*description: command11_done*/ 603 #define RTC_I2C_COMMAND11_DONE (BIT(31)) 604 #define RTC_I2C_COMMAND11_DONE_M (BIT(31)) 605 #define RTC_I2C_COMMAND11_DONE_V 0x1 606 #define RTC_I2C_COMMAND11_DONE_S 31 607 /* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ 608 /*description: command11*/ 609 #define RTC_I2C_COMMAND11 0x00003FFF 610 #define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S)) 611 #define RTC_I2C_COMMAND11_V 0x3FFF 612 #define RTC_I2C_COMMAND11_S 0 613 614 #define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068) 615 /* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 616 /*description: command12_done*/ 617 #define RTC_I2C_COMMAND12_DONE (BIT(31)) 618 #define RTC_I2C_COMMAND12_DONE_M (BIT(31)) 619 #define RTC_I2C_COMMAND12_DONE_V 0x1 620 #define RTC_I2C_COMMAND12_DONE_S 31 621 /* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ 622 /*description: command12*/ 623 #define RTC_I2C_COMMAND12 0x00003FFF 624 #define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S)) 625 #define RTC_I2C_COMMAND12_V 0x3FFF 626 #define RTC_I2C_COMMAND12_S 0 627 628 #define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c) 629 /* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 630 /*description: command13_done*/ 631 #define RTC_I2C_COMMAND13_DONE (BIT(31)) 632 #define RTC_I2C_COMMAND13_DONE_M (BIT(31)) 633 #define RTC_I2C_COMMAND13_DONE_V 0x1 634 #define RTC_I2C_COMMAND13_DONE_S 31 635 /* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ 636 /*description: command13*/ 637 #define RTC_I2C_COMMAND13 0x00003FFF 638 #define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S)) 639 #define RTC_I2C_COMMAND13_V 0x3FFF 640 #define RTC_I2C_COMMAND13_S 0 641 642 #define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070) 643 /* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 644 /*description: command14_done*/ 645 #define RTC_I2C_COMMAND14_DONE (BIT(31)) 646 #define RTC_I2C_COMMAND14_DONE_M (BIT(31)) 647 #define RTC_I2C_COMMAND14_DONE_V 0x1 648 #define RTC_I2C_COMMAND14_DONE_S 31 649 /* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 650 /*description: command14*/ 651 #define RTC_I2C_COMMAND14 0x00003FFF 652 #define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S)) 653 #define RTC_I2C_COMMAND14_V 0x3FFF 654 #define RTC_I2C_COMMAND14_S 0 655 656 #define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074) 657 /* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 658 /*description: command15_done*/ 659 #define RTC_I2C_COMMAND15_DONE (BIT(31)) 660 #define RTC_I2C_COMMAND15_DONE_M (BIT(31)) 661 #define RTC_I2C_COMMAND15_DONE_V 0x1 662 #define RTC_I2C_COMMAND15_DONE_S 31 663 /* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 664 /*description: command15*/ 665 #define RTC_I2C_COMMAND15 0x00003FFF 666 #define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S)) 667 #define RTC_I2C_COMMAND15_V 0x3FFF 668 #define RTC_I2C_COMMAND15_S 0 669 670 #define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC) 671 /* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ 672 /*description: */ 673 #define RTC_I2C_DATE 0x0FFFFFFF 674 #define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S)) 675 #define RTC_I2C_DATE_V 0xFFFFFFF 676 #define RTC_I2C_DATE_S 0 677 678 #ifdef __cplusplus 679 } 680 #endif 681 682 683 684 #endif /*_SOC_RTC_I2C_REG_H_ */ 685
