1 /*
2  * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #pragma once
8 
9 //+-----------------------------------------------Terminology---------------------------------------------+
10 //|                                                                                                       |
11 //| CPU Reset:    Reset CPU core only, once reset done, CPU will execute from reset vector                |
12 //|                                                                                                       |
13 //| Core Reset:   Reset the whole digital system except RTC sub-system                                    |
14 //|                                                                                                       |
15 //| System Reset: Reset the whole digital system, including RTC sub-system                                |
16 //|                                                                                                       |
17 //| Chip Reset:   Reset the whole chip, including the analog part                                         |
18 //|                                                                                                       |
19 //+-------------------------------------------------------------------------------------------------------+
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 /**
26  * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
27  * @note refer to TRM: <Reset and Clock> chapter
28  */
29 typedef enum {
30     RESET_REASON_CHIP_POWER_ON   = 0x01, // Power on reset
31     RESET_REASON_CORE_SW         = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
32     RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
33     RESET_REASON_CORE_MWDT0      = 0x07, // Main watch dog 0 resets digital core
34     RESET_REASON_CORE_RTC_WDT    = 0x09, // RTC watch dog resets digital core
35     RESET_REASON_CPU0_MWDT0      = 0x0B, // Main watch dog 0 resets CPU 0
36     RESET_REASON_CPU0_SW         = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
37     RESET_REASON_CPU0_RTC_WDT    = 0x0D, // RTC watch dog resets CPU 0
38     RESET_REASON_SYS_BROWN_OUT   = 0x0F, // VDD voltage is not stable and resets the digital core
39     RESET_REASON_SYS_RTC_WDT     = 0x10, // RTC watch dog resets digital core and rtc module
40     RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
41     RESET_REASON_SYS_CLK_GLITCH  = 0x13, // Glitch on clock resets the digital core and rtc module
42     RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core
43     RESET_REASON_CPU0_JTAG       = 0x18, // JTAG resets the CPU 0
44 } soc_reset_reason_t;
45 
46 
47 #ifdef __cplusplus
48 }
49 #endif
50