1 /** 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** GDMA_INT_RAW_CH0_REG register 15 * GDMA_INT_RAW_CH0_REG. 16 */ 17 #define GDMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) 18 /** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; 19 * The raw interrupt bit turns to high level when the last data pointed by one inlink 20 * descriptor has been received for Rx channel 0. 21 */ 22 #define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) 23 #define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) 24 #define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U 25 #define GDMA_IN_DONE_CH0_INT_RAW_S 0 26 /** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; 27 * The raw interrupt bit turns to high level when the last data pointed by one inlink 28 * descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit 29 * turns to high level when the last data pointed by one inlink descriptor has been 30 * received and no data error is detected for Rx channel 0. 31 */ 32 #define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) 33 #define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) 34 #define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U 35 #define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 36 /** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; 37 * The raw interrupt bit turns to high level when data error is detected only in the 38 * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw 39 * interrupt is reserved. 40 */ 41 #define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) 42 #define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) 43 #define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U 44 #define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 45 /** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; 46 * The raw interrupt bit turns to high level when the last data pointed by one outlink 47 * descriptor has been transmitted to peripherals for Tx channel 0. 48 */ 49 #define GDMA_OUT_DONE_CH0_INT_RAW (BIT(3)) 50 #define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) 51 #define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U 52 #define GDMA_OUT_DONE_CH0_INT_RAW_S 3 53 /** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; 54 * The raw interrupt bit turns to high level when the last data pointed by one outlink 55 * descriptor has been read from memory for Tx channel 0. 56 */ 57 #define GDMA_OUT_EOF_CH0_INT_RAW (BIT(4)) 58 #define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) 59 #define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U 60 #define GDMA_OUT_EOF_CH0_INT_RAW_S 4 61 /** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; 62 * The raw interrupt bit turns to high level when detecting inlink descriptor error, 63 * including owner error, the second and third word error of inlink descriptor for Rx 64 * channel 0. 65 */ 66 #define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) 67 #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) 68 #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U 69 #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 70 /** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; 71 * The raw interrupt bit turns to high level when detecting outlink descriptor error, 72 * including owner error, the second and third word error of outlink descriptor for Tx 73 * channel 0. 74 */ 75 #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) 76 #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) 77 #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U 78 #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 79 /** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; 80 * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full 81 * and receiving data is not completed, but there is no more inlink for Rx channel 0. 82 */ 83 #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) 84 #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) 85 #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U 86 #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 87 /** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; 88 * The raw interrupt bit turns to high level when data corresponding a outlink 89 * (includes one link descriptor or few link descriptors) is transmitted out for Tx 90 * channel 0. 91 */ 92 #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) 93 #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) 94 #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U 95 #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 96 /** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; 97 * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is 98 * overflow. 99 */ 100 #define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(9)) 101 #define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) 102 #define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U 103 #define GDMA_INFIFO_OVF_CH0_INT_RAW_S 9 104 /** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; 105 * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is 106 * underflow. 107 */ 108 #define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(10)) 109 #define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) 110 #define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U 111 #define GDMA_INFIFO_UDF_CH0_INT_RAW_S 10 112 /** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; 113 * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is 114 * overflow. 115 */ 116 #define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11)) 117 #define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) 118 #define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U 119 #define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 11 120 /** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; 121 * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is 122 * underflow. 123 */ 124 #define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12)) 125 #define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) 126 #define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U 127 #define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 12 128 129 /** GDMA_INT_ST_CH0_REG register 130 * GDMA_INT_ST_CH0_REG. 131 */ 132 #define GDMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) 133 /** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; 134 * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 135 */ 136 #define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) 137 #define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) 138 #define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U 139 #define GDMA_IN_DONE_CH0_INT_ST_S 0 140 /** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; 141 * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 142 */ 143 #define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) 144 #define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) 145 #define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U 146 #define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 147 /** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; 148 * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 149 */ 150 #define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) 151 #define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) 152 #define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U 153 #define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 154 /** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [3]; default: 0; 155 * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 156 */ 157 #define GDMA_OUT_DONE_CH0_INT_ST (BIT(3)) 158 #define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) 159 #define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U 160 #define GDMA_OUT_DONE_CH0_INT_ST_S 3 161 /** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [4]; default: 0; 162 * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 163 */ 164 #define GDMA_OUT_EOF_CH0_INT_ST (BIT(4)) 165 #define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) 166 #define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U 167 #define GDMA_OUT_EOF_CH0_INT_ST_S 4 168 /** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [5]; default: 0; 169 * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 170 */ 171 #define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) 172 #define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) 173 #define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U 174 #define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 5 175 /** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; 176 * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 177 */ 178 #define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) 179 #define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) 180 #define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U 181 #define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 182 /** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [7]; default: 0; 183 * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 184 */ 185 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) 186 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) 187 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U 188 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 189 /** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [8]; default: 0; 190 * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 191 */ 192 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) 193 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) 194 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U 195 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 196 /** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0; 197 * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 198 */ 199 #define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(9)) 200 #define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) 201 #define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U 202 #define GDMA_INFIFO_OVF_CH0_INT_ST_S 9 203 /** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0; 204 * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 205 */ 206 #define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(10)) 207 #define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) 208 #define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U 209 #define GDMA_INFIFO_UDF_CH0_INT_ST_S 10 210 /** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; 211 * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 212 */ 213 #define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(11)) 214 #define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) 215 #define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U 216 #define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 11 217 /** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; 218 * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 219 */ 220 #define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(12)) 221 #define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) 222 #define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U 223 #define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 12 224 225 /** GDMA_INT_ENA_CH0_REG register 226 * GDMA_INT_ENA_CH0_REG. 227 */ 228 #define GDMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) 229 /** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; 230 * The interrupt enable bit for the IN_DONE_CH_INT interrupt. 231 */ 232 #define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) 233 #define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) 234 #define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U 235 #define GDMA_IN_DONE_CH0_INT_ENA_S 0 236 /** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; 237 * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 238 */ 239 #define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) 240 #define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) 241 #define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U 242 #define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 243 /** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; 244 * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 245 */ 246 #define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) 247 #define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) 248 #define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U 249 #define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 250 /** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; 251 * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 252 */ 253 #define GDMA_OUT_DONE_CH0_INT_ENA (BIT(3)) 254 #define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) 255 #define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U 256 #define GDMA_OUT_DONE_CH0_INT_ENA_S 3 257 /** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; 258 * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 259 */ 260 #define GDMA_OUT_EOF_CH0_INT_ENA (BIT(4)) 261 #define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) 262 #define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U 263 #define GDMA_OUT_EOF_CH0_INT_ENA_S 4 264 /** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; 265 * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 266 */ 267 #define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) 268 #define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) 269 #define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U 270 #define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 271 /** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; 272 * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 273 */ 274 #define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) 275 #define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) 276 #define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U 277 #define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 278 /** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; 279 * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 280 */ 281 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) 282 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) 283 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U 284 #define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 285 /** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; 286 * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 287 */ 288 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) 289 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) 290 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U 291 #define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 292 /** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; 293 * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 294 */ 295 #define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(9)) 296 #define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) 297 #define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U 298 #define GDMA_INFIFO_OVF_CH0_INT_ENA_S 9 299 /** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; 300 * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 301 */ 302 #define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(10)) 303 #define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) 304 #define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U 305 #define GDMA_INFIFO_UDF_CH0_INT_ENA_S 10 306 /** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; 307 * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 308 */ 309 #define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(11)) 310 #define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) 311 #define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U 312 #define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 11 313 /** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; 314 * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 315 */ 316 #define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(12)) 317 #define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) 318 #define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U 319 #define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 12 320 321 /** GDMA_INT_CLR_CH0_REG register 322 * GDMA_INT_CLR_CH0_REG. 323 */ 324 #define GDMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) 325 /** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; 326 * Set this bit to clear the IN_DONE_CH_INT interrupt. 327 */ 328 #define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) 329 #define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) 330 #define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U 331 #define GDMA_IN_DONE_CH0_INT_CLR_S 0 332 /** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; 333 * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 334 */ 335 #define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) 336 #define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) 337 #define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U 338 #define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 339 /** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; 340 * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 341 */ 342 #define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) 343 #define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) 344 #define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U 345 #define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 346 /** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [3]; default: 0; 347 * Set this bit to clear the OUT_DONE_CH_INT interrupt. 348 */ 349 #define GDMA_OUT_DONE_CH0_INT_CLR (BIT(3)) 350 #define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) 351 #define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U 352 #define GDMA_OUT_DONE_CH0_INT_CLR_S 3 353 /** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; 354 * Set this bit to clear the OUT_EOF_CH_INT interrupt. 355 */ 356 #define GDMA_OUT_EOF_CH0_INT_CLR (BIT(4)) 357 #define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) 358 #define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U 359 #define GDMA_OUT_EOF_CH0_INT_CLR_S 4 360 /** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [5]; default: 0; 361 * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 362 */ 363 #define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) 364 #define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) 365 #define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U 366 #define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 367 /** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; 368 * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 369 */ 370 #define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) 371 #define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) 372 #define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U 373 #define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 374 /** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [7]; default: 0; 375 * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 376 */ 377 #define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) 378 #define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) 379 #define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U 380 #define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 381 /** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [8]; default: 0; 382 * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 383 */ 384 #define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) 385 #define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) 386 #define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U 387 #define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 388 /** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0; 389 * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 390 */ 391 #define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(9)) 392 #define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) 393 #define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U 394 #define GDMA_INFIFO_OVF_CH0_INT_CLR_S 9 395 /** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0; 396 * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 397 */ 398 #define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(10)) 399 #define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) 400 #define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U 401 #define GDMA_INFIFO_UDF_CH0_INT_CLR_S 10 402 /** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; 403 * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 404 */ 405 #define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(11)) 406 #define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) 407 #define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U 408 #define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 11 409 /** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; 410 * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 411 */ 412 #define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(12)) 413 #define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) 414 #define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U 415 #define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 12 416 417 /** GDMA_AHB_TEST_REG register 418 * GDMA_AHB_TEST_REG. 419 */ 420 #define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x40) 421 /** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; 422 * reserved 423 */ 424 #define GDMA_AHB_TESTMODE 0x00000007U 425 #define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) 426 #define GDMA_AHB_TESTMODE_V 0x00000007U 427 #define GDMA_AHB_TESTMODE_S 0 428 /** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; 429 * reserved 430 */ 431 #define GDMA_AHB_TESTADDR 0x00000003U 432 #define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) 433 #define GDMA_AHB_TESTADDR_V 0x00000003U 434 #define GDMA_AHB_TESTADDR_S 4 435 436 /** GDMA_MISC_CONF_REG register 437 * GDMA_MISC_CONF_REG. 438 */ 439 #define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x44) 440 /** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; 441 * Set this bit, then clear this bit to reset the internal ahb FSM. 442 */ 443 #define GDMA_AHBM_RST_INTER (BIT(0)) 444 #define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) 445 #define GDMA_AHBM_RST_INTER_V 0x00000001U 446 #define GDMA_AHBM_RST_INTER_S 0 447 /** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; 448 * Set this bit to disable priority arbitration function. 449 */ 450 #define GDMA_ARB_PRI_DIS (BIT(2)) 451 #define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) 452 #define GDMA_ARB_PRI_DIS_V 0x00000001U 453 #define GDMA_ARB_PRI_DIS_S 2 454 /** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; 455 * reg_clk_en 456 */ 457 #define GDMA_CLK_EN (BIT(3)) 458 #define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) 459 #define GDMA_CLK_EN_V 0x00000001U 460 #define GDMA_CLK_EN_S 3 461 462 /** GDMA_DATE_REG register 463 * GDMA_DATE_REG. 464 */ 465 #define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x48) 466 /** GDMA_DATE : R/W; bitpos: [31:0]; default: 34624128; 467 * register version. 468 */ 469 #define GDMA_DATE 0xFFFFFFFFU 470 #define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) 471 #define GDMA_DATE_V 0xFFFFFFFFU 472 #define GDMA_DATE_S 0 473 474 /** GDMA_IN_CONF0_CH0_REG register 475 * GDMA_IN_CONF0_CH0_REG. 476 */ 477 #define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) 478 /** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; 479 * This bit is used to reset GDMA channel 0 Rx FSM and Rx FIFO pointer. 480 */ 481 #define GDMA_IN_RST_CH0 (BIT(0)) 482 #define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) 483 #define GDMA_IN_RST_CH0_V 0x00000001U 484 #define GDMA_IN_RST_CH0_S 0 485 /** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; 486 * reserved 487 */ 488 #define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) 489 #define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) 490 #define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U 491 #define GDMA_IN_LOOP_TEST_CH0_S 1 492 /** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; 493 * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link 494 * descriptor when accessing internal SRAM. 495 */ 496 #define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) 497 #define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) 498 #define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U 499 #define GDMA_INDSCR_BURST_EN_CH0_S 2 500 /** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; 501 * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data 502 * when accessing internal SRAM. 503 */ 504 #define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) 505 #define GDMA_IN_DATA_BURST_EN_CH0_M (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S) 506 #define GDMA_IN_DATA_BURST_EN_CH0_V 0x00000001U 507 #define GDMA_IN_DATA_BURST_EN_CH0_S 3 508 /** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; 509 * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. 510 */ 511 #define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) 512 #define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) 513 #define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U 514 #define GDMA_MEM_TRANS_EN_CH0_S 4 515 516 /** GDMA_IN_CONF1_CH0_REG register 517 * GDMA_IN_CONF1_CH0_REG. 518 */ 519 #define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) 520 /** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; 521 * Set this bit to enable checking the owner attribute of the link descriptor. 522 */ 523 #define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) 524 #define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) 525 #define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U 526 #define GDMA_IN_CHECK_OWNER_CH0_S 12 527 528 /** GDMA_INFIFO_STATUS_CH0_REG register 529 * GDMA_INFIFO_STATUS_CH0_REG. 530 */ 531 #define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) 532 /** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; 533 * L1 Rx FIFO full signal for Rx channel 0. 534 */ 535 #define GDMA_INFIFO_FULL_CH0 (BIT(0)) 536 #define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) 537 #define GDMA_INFIFO_FULL_CH0_V 0x00000001U 538 #define GDMA_INFIFO_FULL_CH0_S 0 539 /** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; 540 * L1 Rx FIFO empty signal for Rx channel 0. 541 */ 542 #define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) 543 #define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) 544 #define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U 545 #define GDMA_INFIFO_EMPTY_CH0_S 1 546 /** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; 547 * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 548 */ 549 #define GDMA_INFIFO_CNT_CH0 0x0000003FU 550 #define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) 551 #define GDMA_INFIFO_CNT_CH0_V 0x0000003FU 552 #define GDMA_INFIFO_CNT_CH0_S 2 553 /** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; 554 * reserved 555 */ 556 #define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) 557 #define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) 558 #define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U 559 #define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 560 /** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; 561 * reserved 562 */ 563 #define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) 564 #define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) 565 #define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U 566 #define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 567 /** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; 568 * reserved 569 */ 570 #define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) 571 #define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) 572 #define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U 573 #define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 574 /** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; 575 * reserved 576 */ 577 #define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) 578 #define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) 579 #define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U 580 #define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 581 /** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; 582 * reserved 583 */ 584 #define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) 585 #define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) 586 #define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U 587 #define GDMA_IN_BUF_HUNGRY_CH0_S 27 588 589 /** GDMA_IN_POP_CH0_REG register 590 * GDMA_IN_POP_CH0_REG. 591 */ 592 #define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) 593 /** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; 594 * This register stores the data popping from GDMA FIFO. 595 */ 596 #define GDMA_INFIFO_RDATA_CH0 0x00000FFFU 597 #define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) 598 #define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU 599 #define GDMA_INFIFO_RDATA_CH0_S 0 600 /** GDMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [12]; default: 0; 601 * Set this bit to pop data from GDMA FIFO. 602 */ 603 #define GDMA_INFIFO_POP_CH0 (BIT(12)) 604 #define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) 605 #define GDMA_INFIFO_POP_CH0_V 0x00000001U 606 #define GDMA_INFIFO_POP_CH0_S 12 607 608 /** GDMA_IN_LINK_CH0_REG register 609 * GDMA_IN_LINK_CH0_REG. 610 */ 611 #define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) 612 /** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; 613 * This register stores the 20 least significant bits of the first inlink descriptor's 614 * address. 615 */ 616 #define GDMA_INLINK_ADDR_CH0 0x000FFFFFU 617 #define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) 618 #define GDMA_INLINK_ADDR_CH0_V 0x000FFFFFU 619 #define GDMA_INLINK_ADDR_CH0_S 0 620 /** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; 621 * Set this bit to return to current inlink descriptor's address, when there are some 622 * errors in current receiving data. 623 */ 624 #define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) 625 #define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) 626 #define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U 627 #define GDMA_INLINK_AUTO_RET_CH0_S 20 628 /** GDMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; 629 * Set this bit to stop dealing with the inlink descriptors. 630 */ 631 #define GDMA_INLINK_STOP_CH0 (BIT(21)) 632 #define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) 633 #define GDMA_INLINK_STOP_CH0_V 0x00000001U 634 #define GDMA_INLINK_STOP_CH0_S 21 635 /** GDMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; 636 * Set this bit to start dealing with the inlink descriptors. 637 */ 638 #define GDMA_INLINK_START_CH0 (BIT(22)) 639 #define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) 640 #define GDMA_INLINK_START_CH0_V 0x00000001U 641 #define GDMA_INLINK_START_CH0_S 22 642 /** GDMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; 643 * Set this bit to mount a new inlink descriptor. 644 */ 645 #define GDMA_INLINK_RESTART_CH0 (BIT(23)) 646 #define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) 647 #define GDMA_INLINK_RESTART_CH0_V 0x00000001U 648 #define GDMA_INLINK_RESTART_CH0_S 23 649 /** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; 650 * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is 651 * working. 652 */ 653 #define GDMA_INLINK_PARK_CH0 (BIT(24)) 654 #define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) 655 #define GDMA_INLINK_PARK_CH0_V 0x00000001U 656 #define GDMA_INLINK_PARK_CH0_S 24 657 658 /** GDMA_IN_STATE_CH0_REG register 659 * GDMA_IN_STATE_CH0_REG. 660 */ 661 #define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) 662 /** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; 663 * This register stores the current inlink descriptor's address. 664 */ 665 #define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU 666 #define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) 667 #define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU 668 #define GDMA_INLINK_DSCR_ADDR_CH0_S 0 669 /** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; 670 * reserved 671 */ 672 #define GDMA_IN_DSCR_STATE_CH0 0x00000003U 673 #define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) 674 #define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U 675 #define GDMA_IN_DSCR_STATE_CH0_S 18 676 /** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; 677 * reserved 678 */ 679 #define GDMA_IN_STATE_CH0 0x00000007U 680 #define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) 681 #define GDMA_IN_STATE_CH0_V 0x00000007U 682 #define GDMA_IN_STATE_CH0_S 20 683 684 /** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register 685 * GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG. 686 */ 687 #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) 688 /** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; 689 * This register stores the address of the inlink descriptor when the EOF bit in this 690 * descriptor is 1. 691 */ 692 #define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU 693 #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) 694 #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU 695 #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 696 697 /** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register 698 * GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG. 699 */ 700 #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) 701 /** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; 702 * This register stores the address of the inlink descriptor when there are some 703 * errors in current receiving data. Only used when peripheral is UHCI0. 704 */ 705 #define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU 706 #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) 707 #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU 708 #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 709 710 /** GDMA_IN_DSCR_CH0_REG register 711 * GDMA_IN_DSCR_CH0_REG. 712 */ 713 #define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) 714 /** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; 715 * The address of the current inlink descriptor x. 716 */ 717 #define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU 718 #define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) 719 #define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU 720 #define GDMA_INLINK_DSCR_CH0_S 0 721 722 /** GDMA_IN_DSCR_BF0_CH0_REG register 723 * GDMA_IN_DSCR_BF0_CH0_REG. 724 */ 725 #define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) 726 /** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; 727 * The address of the last inlink descriptor x-1. 728 */ 729 #define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU 730 #define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) 731 #define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU 732 #define GDMA_INLINK_DSCR_BF0_CH0_S 0 733 734 /** GDMA_IN_DSCR_BF1_CH0_REG register 735 * GDMA_IN_DSCR_BF1_CH0_REG. 736 */ 737 #define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) 738 /** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; 739 * The address of the second-to-last inlink descriptor x-2. 740 */ 741 #define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU 742 #define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) 743 #define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU 744 #define GDMA_INLINK_DSCR_BF1_CH0_S 0 745 746 /** GDMA_IN_PRI_CH0_REG register 747 * GDMA_IN_PRI_CH0_REG. 748 */ 749 #define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) 750 /** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; 751 * The priority of Rx channel 0. The larger of the value, the higher of the priority. 752 */ 753 #define GDMA_RX_PRI_CH0 0x0000000FU 754 #define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) 755 #define GDMA_RX_PRI_CH0_V 0x0000000FU 756 #define GDMA_RX_PRI_CH0_S 0 757 758 /** GDMA_IN_PERI_SEL_CH0_REG register 759 * GDMA_IN_PERI_SEL_CH0_REG. 760 */ 761 #define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) 762 /** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; 763 * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 764 * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 765 */ 766 #define GDMA_PERI_IN_SEL_CH0 0x0000003FU 767 #define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) 768 #define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU 769 #define GDMA_PERI_IN_SEL_CH0_S 0 770 771 /** GDMA_OUT_CONF0_CH0_REG register 772 * GDMA_OUT_CONF0_CH0_REG. 773 */ 774 #define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) 775 /** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; 776 * This bit is used to reset GDMA channel 0 Tx FSM and Tx FIFO pointer. 777 */ 778 #define GDMA_OUT_RST_CH0 (BIT(0)) 779 #define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) 780 #define GDMA_OUT_RST_CH0_V 0x00000001U 781 #define GDMA_OUT_RST_CH0_S 0 782 /** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; 783 * reserved 784 */ 785 #define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) 786 #define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) 787 #define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U 788 #define GDMA_OUT_LOOP_TEST_CH0_S 1 789 /** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; 790 * Set this bit to enable automatic outlink-writeback when all the data in tx buffer 791 * has been transmitted. 792 */ 793 #define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) 794 #define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) 795 #define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U 796 #define GDMA_OUT_AUTO_WRBACK_CH0_S 2 797 /** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; 798 * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is 799 * generated when data need to transmit has been popped from FIFO in GDMA 800 */ 801 #define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) 802 #define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) 803 #define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U 804 #define GDMA_OUT_EOF_MODE_CH0_S 3 805 /** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; 806 * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link 807 * descriptor when accessing internal SRAM. 808 */ 809 #define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) 810 #define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) 811 #define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U 812 #define GDMA_OUTDSCR_BURST_EN_CH0_S 4 813 /** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; 814 * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data 815 * when accessing internal SRAM. 816 */ 817 #define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) 818 #define GDMA_OUT_DATA_BURST_EN_CH0_M (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S) 819 #define GDMA_OUT_DATA_BURST_EN_CH0_V 0x00000001U 820 #define GDMA_OUT_DATA_BURST_EN_CH0_S 5 821 822 /** GDMA_OUT_CONF1_CH0_REG register 823 * GDMA_OUT_CONF1_CH0_REG. 824 */ 825 #define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) 826 /** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; 827 * Set this bit to enable checking the owner attribute of the link descriptor. 828 */ 829 #define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) 830 #define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) 831 #define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U 832 #define GDMA_OUT_CHECK_OWNER_CH0_S 12 833 834 /** GDMA_OUTFIFO_STATUS_CH0_REG register 835 * GDMA_OUTFIFO_STATUS_CH0_REG. 836 */ 837 #define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) 838 /** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; 839 * L1 Tx FIFO full signal for Tx channel 0. 840 */ 841 #define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) 842 #define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) 843 #define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U 844 #define GDMA_OUTFIFO_FULL_CH0_S 0 845 /** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; 846 * L1 Tx FIFO empty signal for Tx channel 0. 847 */ 848 #define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) 849 #define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) 850 #define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U 851 #define GDMA_OUTFIFO_EMPTY_CH0_S 1 852 /** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; 853 * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 854 */ 855 #define GDMA_OUTFIFO_CNT_CH0 0x0000003FU 856 #define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) 857 #define GDMA_OUTFIFO_CNT_CH0_V 0x0000003FU 858 #define GDMA_OUTFIFO_CNT_CH0_S 2 859 /** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; 860 * reserved 861 */ 862 #define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) 863 #define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) 864 #define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U 865 #define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 866 /** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; 867 * reserved 868 */ 869 #define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) 870 #define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) 871 #define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U 872 #define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 873 /** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; 874 * reserved 875 */ 876 #define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) 877 #define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) 878 #define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U 879 #define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 880 /** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; 881 * reserved 882 */ 883 #define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) 884 #define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) 885 #define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U 886 #define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 887 888 /** GDMA_OUT_PUSH_CH0_REG register 889 * GDMA_OUT_PUSH_CH0_REG. 890 */ 891 #define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) 892 /** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; 893 * This register stores the data that need to be pushed into GDMA FIFO. 894 */ 895 #define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU 896 #define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) 897 #define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU 898 #define GDMA_OUTFIFO_WDATA_CH0_S 0 899 /** GDMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [9]; default: 0; 900 * Set this bit to push data into GDMA FIFO. 901 */ 902 #define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) 903 #define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) 904 #define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U 905 #define GDMA_OUTFIFO_PUSH_CH0_S 9 906 907 /** GDMA_OUT_LINK_CH0_REG register 908 * GDMA_OUT_LINK_CH0_REG. 909 */ 910 #define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) 911 /** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; 912 * This register stores the 20 least significant bits of the first outlink 913 * descriptor's address. 914 */ 915 #define GDMA_OUTLINK_ADDR_CH0 0x000FFFFFU 916 #define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) 917 #define GDMA_OUTLINK_ADDR_CH0_V 0x000FFFFFU 918 #define GDMA_OUTLINK_ADDR_CH0_S 0 919 /** GDMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0; 920 * Set this bit to stop dealing with the outlink descriptors. 921 */ 922 #define GDMA_OUTLINK_STOP_CH0 (BIT(20)) 923 #define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) 924 #define GDMA_OUTLINK_STOP_CH0_V 0x00000001U 925 #define GDMA_OUTLINK_STOP_CH0_S 20 926 /** GDMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0; 927 * Set this bit to start dealing with the outlink descriptors. 928 */ 929 #define GDMA_OUTLINK_START_CH0 (BIT(21)) 930 #define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) 931 #define GDMA_OUTLINK_START_CH0_V 0x00000001U 932 #define GDMA_OUTLINK_START_CH0_S 21 933 /** GDMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0; 934 * Set this bit to restart a new outlink from the last address. 935 */ 936 #define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) 937 #define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) 938 #define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U 939 #define GDMA_OUTLINK_RESTART_CH0_S 22 940 /** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; 941 * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM 942 * is working. 943 */ 944 #define GDMA_OUTLINK_PARK_CH0 (BIT(23)) 945 #define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) 946 #define GDMA_OUTLINK_PARK_CH0_V 0x00000001U 947 #define GDMA_OUTLINK_PARK_CH0_S 23 948 949 /** GDMA_OUT_STATE_CH0_REG register 950 * GDMA_OUT_STATE_CH0_REG. 951 */ 952 #define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) 953 /** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; 954 * This register stores the current outlink descriptor's address. 955 */ 956 #define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU 957 #define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) 958 #define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU 959 #define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 960 /** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; 961 * reserved 962 */ 963 #define GDMA_OUT_DSCR_STATE_CH0 0x00000003U 964 #define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) 965 #define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U 966 #define GDMA_OUT_DSCR_STATE_CH0_S 18 967 /** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; 968 * reserved 969 */ 970 #define GDMA_OUT_STATE_CH0 0x00000007U 971 #define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) 972 #define GDMA_OUT_STATE_CH0_V 0x00000007U 973 #define GDMA_OUT_STATE_CH0_S 20 974 975 /** GDMA_OUT_EOF_DES_ADDR_CH0_REG register 976 * GDMA_OUT_EOF_DES_ADDR_CH0_REG. 977 */ 978 #define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) 979 /** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; 980 * This register stores the address of the outlink descriptor when the EOF bit in this 981 * descriptor is 1. 982 */ 983 #define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU 984 #define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) 985 #define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU 986 #define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 987 988 /** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register 989 * GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. 990 */ 991 #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) 992 /** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; 993 * This register stores the address of the outlink descriptor before the last outlink 994 * descriptor. 995 */ 996 #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU 997 #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) 998 #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU 999 #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 1000 1001 /** GDMA_OUT_DSCR_CH0_REG register 1002 * GDMA_OUT_DSCR_CH0_REG. 1003 */ 1004 #define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) 1005 /** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; 1006 * The address of the current outlink descriptor y. 1007 */ 1008 #define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU 1009 #define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) 1010 #define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU 1011 #define GDMA_OUTLINK_DSCR_CH0_S 0 1012 1013 /** GDMA_OUT_DSCR_BF0_CH0_REG register 1014 * GDMA_OUT_DSCR_BF0_CH0_REG. 1015 */ 1016 #define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) 1017 /** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; 1018 * The address of the last outlink descriptor y-1. 1019 */ 1020 #define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU 1021 #define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) 1022 #define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU 1023 #define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 1024 1025 /** GDMA_OUT_DSCR_BF1_CH0_REG register 1026 * GDMA_OUT_DSCR_BF1_CH0_REG. 1027 */ 1028 #define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) 1029 /** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; 1030 * The address of the second-to-last inlink descriptor x-2. 1031 */ 1032 #define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU 1033 #define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) 1034 #define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU 1035 #define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 1036 1037 /** GDMA_OUT_PRI_CH0_REG register 1038 * GDMA_OUT_PRI_CH0_REG. 1039 */ 1040 #define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) 1041 /** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; 1042 * The priority of Tx channel 0. The larger of the value, the higher of the priority. 1043 */ 1044 #define GDMA_TX_PRI_CH0 0x0000000FU 1045 #define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) 1046 #define GDMA_TX_PRI_CH0_V 0x0000000FU 1047 #define GDMA_TX_PRI_CH0_S 0 1048 1049 /** GDMA_OUT_PERI_SEL_CH0_REG register 1050 * GDMA_OUT_PERI_SEL_CH0_REG. 1051 */ 1052 #define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) 1053 /** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; 1054 * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 1055 * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 1056 */ 1057 #define GDMA_PERI_OUT_SEL_CH0 0x0000003FU 1058 #define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) 1059 #define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU 1060 #define GDMA_PERI_OUT_SEL_CH0_S 0 1061 1062 #ifdef __cplusplus 1063 } 1064 #endif 1065
