1 /* 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <stdint.h> 8 #include <stdlib.h> 9 #include "esp_attr.h" 10 #include "sdkconfig.h" 11 #include "soc/soc.h" 12 #include "heap_memory_layout.h" 13 #include "esp_heap_caps.h" 14 15 /** 16 * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. 17 * Each type of memory map consists of one or more regions in the address space. 18 * Each type contains an array of prioritized capabilities. 19 * Types with later entries are only taken if earlier ones can't fulfill the memory request. 20 * 21 * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. 22 * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. 23 * - Most other malloc caps only fit in one region anyway. 24 * 25 */ 26 /* Index of memory in `soc_memory_types[]` */ 27 enum { 28 SOC_MEMORY_TYPE_DRAM = 0, 29 SOC_MEMORY_TYPE_STACK_DRAM = 1, 30 SOC_MEMORY_TYPE_DIRAM = 2, 31 SOC_MEMORY_TYPE_STACK_DIRAM = 3, 32 SOC_MEMORY_TYPE_RTCRAM = 4, 33 SOC_MEMORY_TYPE_NUM, 34 }; 35 36 const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { 37 // Type 0: DRAM 38 [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, 39 // Type 1: DRAM used for startup stacks 40 [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, 41 // Type 2: DRAM which has an alias on the I-port 42 [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, 43 // Type 3: DIRAM used for startup stacks 44 [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, 45 // Type 4: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM 46 [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, 47 }; 48 49 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 50 #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM 51 #define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM 52 #else 53 #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM 54 #define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM 55 #endif 56 57 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); 58 59 /** 60 * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. 61 * 62 * @note Because of requirements in the coalescing code which merges adjacent regions, 63 * this list should always be sorted from low to high by start address. 64 * 65 */ 66 67 /** 68 * Register the shared buffer area of the last memory block into the heap during heap initialization 69 */ 70 #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) 71 72 const soc_memory_region_t soc_memory_regions[] = { 73 { 0x40800000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level 0 74 { 0x40810000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40810000}, //D/IRAM level 1 75 { 0x40820000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level 2 76 { 0x40830000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40830000}, //D/IRAM level 3 77 { 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level 4 78 { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, APP_USABLE_DRAM_END}, //D/IRAM level 4 79 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 80 { 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory 81 #endif 82 }; 83 84 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); 85 86 87 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; 88 extern int _rtc_reserved_start, _rtc_reserved_end; 89 90 /** 91 * Reserved memory regions. 92 * These are removed from the soc_memory_regions array when heaps are created. 93 * 94 */ 95 96 // Static data region. DRAM used by data+bss and possibly rodata 97 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); 98 99 // Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips 100 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code); 101 102 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 103 // TODO: IDF-6019 check reserved lp mem region 104 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); 105 #endif 106 107 SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); 108
