1 /* 2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <stdint.h> 8 #include <stdlib.h> 9 #include "esp_attr.h" 10 #include "sdkconfig.h" 11 #include "soc/soc.h" 12 #include "heap_memory_layout.h" 13 #include "esp_heap_caps.h" 14 15 /** 16 * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. 17 * Each type of memory map consists of one or more regions in the address space. 18 * Each type contains an array of prioritized capabilities. 19 * Types with later entries are only taken if earlier ones can't fulfill the memory request. 20 * 21 * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. 22 * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. 23 * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. 24 * - Most other malloc caps only fit in one region anyway. 25 * 26 */ 27 28 /* Index of memory in `soc_memory_types[]` */ 29 enum { 30 SOC_MEMORY_TYPE_DRAM = 0, 31 SOC_MEMORY_TYPE_STACK_DRAM = 1, 32 SOC_MEMORY_TYPE_DIRAM = 2, 33 SOC_MEMORY_TYPE_STACK_DIRAM = 3, 34 SOC_MEMORY_TYPE_RTCRAM = 4, 35 SOC_MEMORY_TYPE_NUM, 36 }; 37 38 const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { 39 // Type 0: DRAM 40 [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, 41 // Type 1: DRAM used for startup stacks 42 [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, 43 // Type 2: DRAM which has an alias on the I-port 44 [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, 45 // Type 3: DIRAM used for startup stacks 46 [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, 47 // Type 4: RTCRAM 48 [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, 49 }; 50 51 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 52 #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM 53 #define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM 54 #else 55 #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM 56 #define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM 57 #endif 58 59 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); 60 61 /** 62 * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. 63 * 64 * @note Because of requirements in the coalescing code which merges adjacent regions, 65 * this list should always be sorted from low to high by start address. 66 * 67 */ 68 69 /** 70 * Register the shared buffer area of the last memory block into the heap during heap initialization 71 */ 72 #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) 73 74 const soc_memory_region_t soc_memory_regions[] = { 75 { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory 76 { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory 77 { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory 78 { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) 79 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 80 { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory 81 #endif 82 }; 83 84 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); 85 86 87 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; 88 extern int _rtc_reserved_start, _rtc_reserved_end; 89 90 /** 91 * Reserved memory regions. 92 * These are removed from the soc_memory_regions array when heaps are created. 93 * 94 */ 95 96 // Static data region. DRAM used by data+bss and possibly rodata 97 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); 98 99 // Target has a big D/IRAM region, the part used by code is reserved 100 // The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address 101 #define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) 102 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); 103 104 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 105 /* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW 106 region on C3, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections. 107 */ 108 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); 109 #endif 110 111 SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); 112
