1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef BOOTLOADER_BUILD 7 8 #include <stdint.h> 9 #include <stdlib.h> 10 #include "esp_attr.h" 11 #include "sdkconfig.h" 12 #include "soc/soc.h" 13 #include "soc/soc_memory_layout.h" 14 #include "esp_heap_caps.h" 15 16 /** 17 * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. 18 * Each type of memory map consists of one or more regions in the address space. 19 * Each type contains an array of prioritized capabilities. 20 * Types with later entries are only taken if earlier ones can't fulfill the memory request. 21 * 22 * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. 23 * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. 24 * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. 25 * - Most other malloc caps only fit in one region anyway. 26 * 27 */ 28 29 /* Index of memory in `soc_memory_types[]` */ 30 enum { 31 SOC_MEMORY_TYPE_STACK_DRAM = 0, 32 SOC_MEMORY_TYPE_DIRAM = 1, 33 SOC_MEMORY_TYPE_NUM, 34 }; 35 36 const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { 37 // Type 0: DRAM used for startup stacks 38 [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, 39 // Type 1: DRAM which has an alias on the I-port 40 [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, 41 }; 42 43 #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM 44 45 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); 46 47 /** 48 * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. 49 * 50 * @note Because of requirements in the coalescing code which merges adjacent regions, 51 * this list should always be sorted from low to high by start address. 52 * 53 */ 54 55 /** 56 * Register the shared buffer area of the last memory block into the heap during heap initialization 57 */ 58 #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) 59 60 const soc_memory_region_t soc_memory_regions[] = { 61 { 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1 62 { 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //D/IRAM level2 63 { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level3 64 { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)} //D/IRAM level3 (ROM reserved area) 65 }; 66 67 68 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); 69 70 71 extern int _data_start, _heap_start, _iram_start, _iram_end; 72 73 /** 74 * Reserved memory regions. 75 * These are removed from the soc_memory_regions array when heaps are created. 76 * 77 */ 78 79 // Static data region. DRAM used by data+bss and possibly rodata 80 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); 81 82 // Target has a big D/IRAM region, the part used by code is reserved 83 // The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address 84 #define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) 85 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); 86 87 #endif // BOOTLOADER_BUILD 88
