1// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7//     http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15#include <string.h>
16#include <stdlib.h>
17#include "hal/spi_flash_hal.h"
18#include "hal/assert.h"
19#include "soc/soc_caps.h"
20#include "sdkconfig.h"
21
22#define ADDRESS_MASK_24BIT 0xFFFFFF
23#define COMPUTE_DUMMY_CYCLELEN(host, base)    ((base) + ((spi_flash_hal_context_t*)host)->extra_dummy)
24
25static inline spi_dev_t *get_spi_dev(spi_flash_host_inst_t *host)
26{
27    return ((spi_flash_hal_context_t*)host)->spi;
28}
29
30static inline int get_host_id(spi_flash_host_inst_t* host)
31{
32    spi_dev_t *dev = get_spi_dev(host);
33    return spi_flash_ll_hw_get_id(dev);
34}
35
36void spi_flash_hal_poll_cmd_done(spi_flash_host_inst_t *host)
37{
38    while (!spi_flash_ll_cmd_is_done(get_spi_dev(host))) {
39        //nop
40    }
41}
42
43esp_err_t spi_flash_hal_device_config(spi_flash_host_inst_t *host)
44{
45    spi_flash_hal_context_t* ctx = (spi_flash_hal_context_t*)host;
46    spi_dev_t *dev = get_spi_dev(host);
47
48    spi_flash_ll_reset(dev);
49    spi_flash_ll_set_cs_pin(dev, ctx->cs_num);
50    spi_flash_ll_set_clock(dev, &ctx->clock_conf);
51    int cs_hold = ctx->cs_hold;
52    spi_flash_ll_set_hold(dev, cs_hold);
53    spi_flash_ll_set_cs_setup(dev, ctx->cs_setup);
54
55#ifndef GPSPI_BUILD
56#if SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
57    if ((ctx->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) != 0) {
58        spi_flash_hal_setup_auto_suspend_mode(host);
59    } else {
60        spi_flash_hal_disable_auto_suspend_mode(host);
61    }
62    if ((ctx->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME) != 0) {
63        spi_flash_hal_setup_auto_resume_mode(host);
64    } else {
65        spi_flash_hal_disable_auto_resume_mode(host);
66    }
67#endif //SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
68#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
69    // Always keep the extra dummy on SPI1 is 0, add extra dummy to user dummy
70    spimem_flash_ll_set_extra_dummy((spi_mem_dev_t*)dev, 0);
71#endif
72#else
73    gpspi_flash_ll_set_hold_pol(dev, 1);
74#endif //GPSPI_BUILD
75
76    return ESP_OK;
77}
78
79esp_err_t spi_flash_hal_configure_host_io_mode(
80    spi_flash_host_inst_t *host,
81    uint32_t command,
82    uint32_t addr_bitlen,
83    int dummy_cyclelen_base,
84    esp_flash_io_mode_t io_mode)
85{
86    spi_dev_t *dev = get_spi_dev(host);
87    int host_id = spi_flash_ll_hw_get_id(dev);
88
89    uint32_t extra_bits = io_mode & 0xFFFF0000;
90    io_mode = io_mode & 0xFFFF;
91
92    /*
93     * Some flash chips, when working under some IO modes (DIO, QIO and OIO in the future), treat
94     * the first 8 bits of the dummy bits as the bits. When the bits meet some pattern, the chip
95     * will go into a "continuous (XIP)" mode, where the command field will be skipped in the next
96     * transaction. We have to output all ones in these cycles because we don't need this feature.
97     */
98    bool conf_required = ((extra_bits & SPI_FLASH_CONFIG_CONF_BITS) != 0);
99
100    if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) && io_mode > SPI_FLASH_FASTRD) {
101        return ESP_ERR_NOT_SUPPORTED;
102    }
103
104#if SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
105    // The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits.
106    spi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
107#else
108    /**
109     * - On current chips, addr phase can support 32 bits at most.
110     * - Flash chip requires continuous mode bits
111     *
112     * We send continuous mode bits via the dummy output feature, so as to support
113     * 32-bit address.
114     *
115     * On chips without dummy output feature (ESP32, ESP32C6), we fallback to use
116     * addr phase to send the continuous mode bits:
117     * - On ESP32 (QIO), qio_dummy: 6 - 4 / 4 = 5, addr_bitlen: 24 + 4 = 28. (This
118     *   setting exists for long time, we keep this on ESP32)
119     * - On ESP32C6 (QIO), qio_dummy: 6 - 8 / 4 = 4, addr_bitlen: 24 + 8 = 32
120     * - On future chips without dummy output feature, we follow the ESP32C6 (QIO)
121     *   way.
122     * - Above two ways, the timings are same.
123     * - DIO is similar.
124     */
125    if (conf_required) {
126        int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
127        dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
128        addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
129        spi_flash_ll_set_extra_address(dev, 0);
130    }
131#endif
132
133    if (command >= 0x100) {
134        spi_flash_ll_set_command(dev, command, 16);
135    } else {
136        spi_flash_ll_set_command(dev, command, 8);
137    }
138    spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
139    // Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
140    spi_flash_ll_set_dummy(dev, COMPUTE_DUMMY_CYCLELEN(host, dummy_cyclelen_base));
141    //disable all data phases, enable them later if needed
142    spi_flash_ll_set_miso_bitlen(dev, 0);
143    spi_flash_ll_set_mosi_bitlen(dev, 0);
144    spi_flash_ll_set_read_mode(dev, io_mode);
145    return ESP_OK;
146}
147
148esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_trans_t *trans)
149{
150    spi_dev_t *dev = get_spi_dev(host);
151    esp_flash_io_mode_t io_mode = ((spi_flash_hal_context_t*)host)->base_io_mode;
152    uint16_t command;
153    uint8_t dummy_bitlen;
154
155    command = trans->command;
156    dummy_bitlen = trans->dummy_bitlen;
157    if ((trans->flags & SPI_FLASH_TRANS_FLAG_IGNORE_BASEIO) != 0) {
158        io_mode = trans->io_mode;
159    }
160
161    host->driver->configure_host_io_mode(host, command, trans->address_bitlen, dummy_bitlen, io_mode);
162
163    spi_flash_ll_set_usr_address(dev, trans->address, trans->address_bitlen);
164    //No extra dummy cycles for compensation if no input data
165    if (trans->miso_len == 0) {
166        spi_flash_ll_set_dummy(dev, dummy_bitlen);
167    }
168
169    spi_flash_ll_set_mosi_bitlen(dev, trans->mosi_len * 8);
170    spi_flash_ll_set_buffer_data(dev, trans->mosi_data, trans->mosi_len);
171
172    spi_flash_ll_set_miso_bitlen(dev, trans->miso_len * 8);
173    spi_flash_ll_user_start(dev);
174    host->driver->poll_cmd_done(host);
175    if (trans->miso_len > 0) {
176        spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len);
177    }
178    return ESP_OK;
179}
180
181esp_err_t spi_flash_hal_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len)
182{
183    spi_dev_t *dev = get_spi_dev(host);
184    int bitlen = spi_flash_ll_get_addr_bitlen(dev);
185    //Only 24-bit and 32-bit address are supported. The extra length are for M7-M0, which should be
186    //filled with ones by the function below
187    spi_flash_ll_set_usr_address(dev, address, bitlen & (~7));
188    spi_flash_ll_set_miso_bitlen(dev, read_len * 8);
189    spi_flash_ll_user_start(dev);
190    host->driver->poll_cmd_done(host);
191    if (read_len > 0) {
192        spi_flash_ll_get_buffer_data(dev, buffer, read_len);
193    }
194    return ESP_OK;
195}
196