1 /*
2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include <sys/param.h>
9 #include "soc/soc_caps.h"
10 #include "hal/assert.h"
11 #include "hal/efuse_hal.h"
12 #include "hal/efuse_ll.h"
13 #include "esp32s3/rom/efuse.h"
14 #include "esp_attr.h"
15
16 #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
17
18
19 //The wafer_major and MSB of wafer_minor fields was allocated to other purposes when block version is v1.1.
20 //Luckily only chip v0.0 have this kind of block version and efuse usage.
21 //This workaround fixes the issue.
is_eco0(uint32_t minor_raw)22 static inline bool is_eco0(uint32_t minor_raw)
23 {
24 return ((minor_raw & 0x7) == 0 &&
25 efuse_ll_get_blk_version_major() == 1 && efuse_ll_get_blk_version_minor() == 1);
26 }
27
efuse_hal_get_major_chip_version(void)28 IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
29 {
30 uint32_t minor_raw = efuse_ll_get_chip_wafer_version_minor();
31
32 if (is_eco0(minor_raw)) {
33 return 0;
34 }
35 return efuse_ll_get_chip_wafer_version_major();
36 }
37
efuse_hal_get_minor_chip_version(void)38 IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
39 {
40 uint32_t minor_raw = efuse_ll_get_chip_wafer_version_minor();
41
42 if (is_eco0(minor_raw)) {
43 return 0;
44 }
45 return minor_raw;
46 }
47
48 /******************* eFuse control functions *************************/
49
efuse_hal_set_timing(uint32_t apb_freq_hz)50 void efuse_hal_set_timing(uint32_t apb_freq_hz)
51 {
52 (void) apb_freq_hz;
53 efuse_ll_set_dac_num(0xFF);
54 efuse_ll_set_dac_clk_div(0x28);
55 efuse_ll_set_pwr_on_num(0x3000);
56 efuse_ll_set_pwr_off_num(0x190);
57 }
58
efuse_hal_read(void)59 void efuse_hal_read(void)
60 {
61 efuse_hal_set_timing(0);
62
63 efuse_ll_set_conf_read_op_code();
64 efuse_ll_set_read_cmd();
65
66 while (efuse_ll_get_read_cmd() != 0) { }
67 /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
68 while (efuse_ll_get_read_cmd() != 0) { }
69 }
70
efuse_hal_clear_program_registers(void)71 void efuse_hal_clear_program_registers(void)
72 {
73 ets_efuse_clear_program_registers();
74 }
75
efuse_hal_program(uint32_t block)76 void efuse_hal_program(uint32_t block)
77 {
78 efuse_hal_set_timing(0);
79
80 efuse_ll_set_conf_write_op_code();
81 efuse_ll_set_pgm_cmd(block);
82
83 while (efuse_ll_get_pgm_cmd() != 0) { }
84
85 efuse_hal_clear_program_registers();
86 efuse_hal_read();
87 }
88
efuse_hal_rs_calculate(const void * data,void * rs_values)89 void efuse_hal_rs_calculate(const void *data, void *rs_values)
90 {
91 ets_efuse_rs_calculate(data, rs_values);
92 }
93
94 /******************* eFuse control functions *************************/
95
efuse_hal_is_coding_error_in_block(unsigned block)96 bool efuse_hal_is_coding_error_in_block(unsigned block)
97 {
98 if (block == 0) {
99 for (unsigned i = 0; i < 5; i++) {
100 if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
101 return true;
102 }
103 }
104 } else if (block <= 10) {
105 // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
106 // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
107 block--;
108 uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
109 return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
110 }
111 return false;
112 }
113
