1 /*
2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include <sys/param.h>
9 #include "soc/soc_caps.h"
10 #include "hal/assert.h"
11 #include "hal/efuse_hal.h"
12 #include "hal/efuse_ll.h"
13 #include "esp32s2/rom/efuse.h"
14 #include "esp_attr.h"
15
16 #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
17
efuse_hal_get_major_chip_version(void)18 IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
19 {
20 return efuse_ll_get_chip_wafer_version_major();
21 }
22
efuse_hal_get_minor_chip_version(void)23 IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
24 {
25 return efuse_ll_get_chip_wafer_version_minor();
26 }
27
28 /******************* eFuse control functions *************************/
29
efuse_hal_set_timing(uint32_t apb_freq_hz)30 void efuse_hal_set_timing(uint32_t apb_freq_hz)
31 {
32 uint32_t tsup_a;
33 uint32_t tpgm;
34 uint32_t thp_a;
35 uint32_t tpgm_inact;
36 uint32_t clk_div;
37 uint32_t power_on;
38 uint32_t power_off;
39 uint32_t tsur_a;
40 uint32_t trd;
41 uint32_t thr_a;
42 if (apb_freq_hz == 80000000) {
43 tsup_a = 0x2;
44 tpgm = 0x320;
45 thp_a = 0x2;
46 tpgm_inact = 0x4;
47 clk_div = 0xA0;
48 power_on = 0xA200;
49 power_off = 0x100;
50 tsur_a = 0x2;
51 trd = 0x4;
52 thr_a = 0x2;
53 } else if (apb_freq_hz == 40000000) {
54 tsup_a = 0x1;
55 tpgm = 0x190;
56 thp_a = 0x1;
57 tpgm_inact = 0x2;
58 clk_div = 0x50;
59 power_on = 0x5100;
60 power_off = 0x80;
61 tsur_a = 0x1;
62 trd = 0x2;
63 thr_a = 0x1;
64 } else { // 20000000 or 5000000 or 10000000
65 tsup_a = 0x1;
66 tpgm = 0xC8;
67 thp_a = 0x1;
68 tpgm_inact = 0x1;
69 clk_div = 0x28;
70 power_on = 0x2880;
71 power_off = 0x40;
72 tsur_a = 0x1;
73 trd = 0x1;
74 thr_a = 0x1;
75 }
76 REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_TSUP_A, tsup_a);
77 REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm);
78 REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a);
79 REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact);
80 REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, clk_div);
81 REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_PWR_ON_NUM, power_on);
82 REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, power_off);
83 REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TSUR_A, tsur_a);
84 REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TRD, trd);
85 REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_THR_A, thr_a);
86 }
87
efuse_hal_read(void)88 void efuse_hal_read(void)
89 {
90 ets_efuse_read();
91 }
92
efuse_hal_clear_program_registers(void)93 void efuse_hal_clear_program_registers(void)
94 {
95 ets_efuse_clear_program_registers();
96 }
97
efuse_hal_program(uint32_t block)98 void efuse_hal_program(uint32_t block)
99 {
100 ets_efuse_program(block);
101 }
102
efuse_hal_rs_calculate(const void * data,void * rs_values)103 void efuse_hal_rs_calculate(const void *data, void *rs_values)
104 {
105 ets_efuse_rs_calculate(data, rs_values);
106 }
107
108 /******************* eFuse control functions *************************/
109
efuse_hal_is_coding_error_in_block(unsigned block)110 bool efuse_hal_is_coding_error_in_block(unsigned block)
111 {
112 if (block == 0) {
113 for (unsigned i = 0; i < 5; i++) {
114 if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
115 return true;
116 }
117 }
118 } else if (block <= 10) {
119 // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
120 // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
121 block--;
122 uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
123 return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
124 }
125 return false;
126 }
127
