1 /*
2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include <sys/param.h>
9 #include "soc/soc_caps.h"
10 #include "hal/assert.h"
11 #include "hal/efuse_hal.h"
12 #include "hal/efuse_ll.h"
13
14 #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
15 #define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
16
efuse_hal_get_major_chip_version(void)17 uint32_t efuse_hal_get_major_chip_version(void)
18 {
19 #ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
20 return CONFIG_ESP_REV_MIN_FULL / 100;
21 #else
22 return efuse_ll_get_chip_wafer_version_major();
23 #endif
24 }
25
efuse_hal_get_minor_chip_version(void)26 uint32_t efuse_hal_get_minor_chip_version(void)
27 {
28 #ifdef CONFIG_ESP_REV_NEW_CHIP_TEST
29 return CONFIG_ESP_REV_MIN_FULL % 100;
30 #else
31 return efuse_ll_get_chip_wafer_version_minor();
32 #endif
33 }
34
35 /******************* eFuse control functions *************************/
36
efuse_hal_set_timing(uint32_t apb_freq_hz)37 void efuse_hal_set_timing(uint32_t apb_freq_hz)
38 {
39 (void) apb_freq_hz;
40 efuse_ll_set_dac_num(0xFF);
41 efuse_ll_set_dac_clk_div(0x28);
42 efuse_ll_set_pwr_on_num(0x3000);
43 efuse_ll_set_pwr_off_num(0x190);
44 }
45
efuse_hal_read(void)46 void efuse_hal_read(void)
47 {
48 efuse_hal_set_timing(0);
49
50 efuse_ll_set_conf_read_op_code();
51 efuse_ll_set_read_cmd();
52
53 while (efuse_ll_get_read_cmd() != 0) { }
54 /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
55 while (efuse_ll_get_read_cmd() != 0) { }
56 }
57
efuse_hal_clear_program_registers(void)58 void efuse_hal_clear_program_registers(void)
59 {
60 ets_efuse_clear_program_registers();
61 }
62
efuse_hal_program(uint32_t block)63 void efuse_hal_program(uint32_t block)
64 {
65 efuse_hal_set_timing(0);
66
67 efuse_ll_set_conf_write_op_code();
68 efuse_ll_set_pgm_cmd(block);
69
70 while (efuse_ll_get_pgm_cmd() != 0) { }
71
72 efuse_hal_clear_program_registers();
73 efuse_hal_read();
74 }
75
efuse_hal_rs_calculate(const void * data,void * rs_values)76 void efuse_hal_rs_calculate(const void *data, void *rs_values)
77 {
78 ets_efuse_rs_calculate(data, rs_values);
79 }
80
81 /******************* eFuse control functions *************************/
82
efuse_hal_is_coding_error_in_block(unsigned block)83 bool efuse_hal_is_coding_error_in_block(unsigned block)
84 {
85 if (block == 0) {
86 for (unsigned i = 0; i < 5; i++) {
87 if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
88 return true;
89 }
90 }
91 } else if (block <= 10) {
92 // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
93 // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
94 block--;
95 uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
96 return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
97 }
98 return false;
99 }
100
