1 /*
2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include <sys/param.h>
9 #include "soc/soc_caps.h"
10 #include "hal/assert.h"
11 #include "hal/efuse_hal.h"
12 #include "hal/efuse_ll.h"
13 #include "hal/clk_tree_ll.h"
14 #include "esp_attr.h"
15
16 #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
17
efuse_hal_get_major_chip_version(void)18 IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
19 {
20 return efuse_ll_get_chip_wafer_version_major();
21 }
22
efuse_hal_get_minor_chip_version(void)23 IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
24 {
25 return efuse_ll_get_chip_wafer_version_minor();
26 }
27
28 /******************* eFuse control functions *************************/
29
efuse_hal_set_timing(uint32_t apb_freq_hz)30 void efuse_hal_set_timing(uint32_t apb_freq_hz)
31 {
32 (void) apb_freq_hz;
33 efuse_ll_set_dac_num(0xFF);
34 efuse_ll_set_dac_clk_div(0x28);
35 efuse_ll_set_pwr_on_num(0x3000);
36 efuse_ll_set_pwr_off_num(0x190);
37 int xtal = clk_ll_xtal_load_freq_mhz();
38 HAL_ASSERT(xtal == 40 || xtal == 26);
39 // for the XTAL = 40 MHz we use the default value = 200.
40 // XTAL = 26 MHz the value = 130.
41 efuse_ll_set_tpgm_inactive(xtal * 5);
42 }
43
efuse_hal_read(void)44 void efuse_hal_read(void)
45 {
46 efuse_hal_set_timing(0);
47
48 efuse_ll_set_conf_read_op_code();
49 efuse_ll_set_read_cmd();
50
51 while (efuse_ll_get_read_cmd() != 0) { }
52 /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
53 while (efuse_ll_get_read_cmd() != 0) { }
54 }
55
efuse_hal_clear_program_registers(void)56 void efuse_hal_clear_program_registers(void)
57 {
58 ets_efuse_clear_program_registers();
59 }
60
efuse_hal_program(uint32_t block)61 void efuse_hal_program(uint32_t block)
62 {
63 efuse_hal_set_timing(0);
64
65 efuse_ll_set_conf_write_op_code();
66 efuse_ll_set_pgm_cmd(block);
67
68 while (efuse_ll_get_pgm_cmd() != 0) { }
69
70 efuse_hal_clear_program_registers();
71 efuse_hal_read();
72 }
73
efuse_hal_rs_calculate(const void * data,void * rs_values)74 void efuse_hal_rs_calculate(const void *data, void *rs_values)
75 {
76 ets_efuse_rs_calculate(data, rs_values);
77 }
78
79 /******************* eFuse control functions *************************/
80
efuse_hal_is_coding_error_in_block(unsigned block)81 bool efuse_hal_is_coding_error_in_block(unsigned block)
82 {
83 if (block == 0) {
84 return REG_READ(EFUSE_RD_REPEAT_ERR_REG) != 0;
85 } else if (block <= 3) {
86 // EFUSE_RD_RS_ERR_REG: (hi) ----, ----, ----, ----, ----, BLOCK3, BLOCK2, BLOCK1 (low)
87 uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR_REG);
88 return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block - 1) != 0;
89 }
90 return false;
91 }
92
