1 /*
2 * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <sys/param.h>
8 #include "sdkconfig.h"
9 #include "soc/soc_caps.h"
10 #include "hal/adc_oneshot_hal.h"
11 #include "hal/adc_hal_common.h"
12 #include "hal/adc_ll.h"
13 #include "hal/assert.h"
14 #include "hal/log.h"
15
16 #if SOC_DAC_SUPPORTED
17 #include "hal/dac_ll.h"
18 #endif
19
20 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
21 /**
22 * For chips without RTC controller, Digital controller is used to trigger an ADC single read.
23 */
24 #include "esp_rom_sys.h"
25 #endif
26
27
28 #if CONFIG_ADC_DISABLE_DAC_OUTPUT
29 // To disable DAC, workarounds, see this function body to know more
30 static void s_disable_dac(adc_oneshot_hal_ctx_t *hal, adc_channel_t channel);
31 #endif
32
33
adc_oneshot_hal_init(adc_oneshot_hal_ctx_t * hal,const adc_oneshot_hal_cfg_t * config)34 void adc_oneshot_hal_init(adc_oneshot_hal_ctx_t *hal, const adc_oneshot_hal_cfg_t *config)
35 {
36 hal->unit = config->unit;
37 hal->work_mode = config->work_mode;
38 hal->clk_src = config->clk_src;
39 hal->clk_src_freq_hz = config->clk_src_freq_hz;
40 }
41
adc_oneshot_hal_channel_config(adc_oneshot_hal_ctx_t * hal,const adc_oneshot_hal_chan_cfg_t * config,adc_channel_t chan)42 void adc_oneshot_hal_channel_config(adc_oneshot_hal_ctx_t *hal, const adc_oneshot_hal_chan_cfg_t *config, adc_channel_t chan)
43 {
44 hal->chan_configs[chan].atten = config->atten;
45 hal->chan_configs[chan].bitwidth = config->bitwidth;
46 }
47
adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t * hal,adc_channel_t chan)48 void adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t *hal, adc_channel_t chan)
49 {
50 adc_unit_t unit = hal->unit;
51
52 #ifdef CONFIG_IDF_TARGET_ESP32
53 adc_ll_hall_disable(); //Disable other peripherals.
54 adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
55 #endif
56
57 #if CONFIG_ADC_DISABLE_DAC_OUTPUT
58 s_disable_dac(hal, chan);
59 #endif
60
61 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
62 adc_ll_digi_clk_sel(hal->clk_src);
63 adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT);
64 adc_ll_digi_set_clk_div(ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT);
65 #else
66 adc_ll_set_sar_clk_div(unit, ADC_LL_SAR_CLK_DIV_DEFAULT(unit));
67 if (unit == ADC_UNIT_2) {
68 adc_ll_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
69 }
70 #endif
71
72 adc_oneshot_ll_output_invert(unit, ADC_LL_DATA_INVERT_DEFAULT(unit));
73 adc_oneshot_ll_set_atten(unit, chan, hal->chan_configs[chan].atten);
74 adc_oneshot_ll_set_output_bits(unit, hal->chan_configs[chan].bitwidth);
75 adc_oneshot_ll_set_channel(unit, chan);
76 adc_hal_set_controller(unit, hal->work_mode);
77
78 #if SOC_ADC_ARBITER_SUPPORTED
79 adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
80 adc_hal_arbiter_config(&config);
81 #endif //#if SOC_ADC_ARBITER_SUPPORTED
82 }
83
adc_hal_onetime_start(adc_unit_t unit,uint32_t clk_src_freq_hz,uint32_t * read_delay_us)84 static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz, uint32_t *read_delay_us)
85 {
86 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
87 (void)unit;
88 /**
89 * There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the
90 * ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller
91 * clock cycle.
92 */
93 uint32_t adc_ctrl_clk = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1);
94 //Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough.
95
96 uint32_t sample_delay_us = ((1000 * 1000) / adc_ctrl_clk + 1) * 3;
97 HAL_EARLY_LOGD("adc_hal", "clk_src_freq_hz: %"PRIu32", adc_ctrl_clk: %"PRIu32", sample_delay_us: %"PRIu32"", clk_src_freq_hz, adc_ctrl_clk, sample_delay_us);
98
99 //This coefficient (8) is got from test, and verified from DT. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
100 if (adc_ctrl_clk >= APB_CLK_FREQ/8) {
101 sample_delay_us = 0;
102 }
103
104 HAL_EARLY_LOGD("adc_hal", "delay for `onetime_start` signal captured: %"PRIu32"", sample_delay_us);
105 adc_oneshot_ll_start(false);
106 esp_rom_delay_us(sample_delay_us);
107 adc_oneshot_ll_start(true);
108
109 #if ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL
110 /**
111 * There is a hardware limitation.
112 * After ADC get DONE signal, it still need a delay to synchronize ADC raw data or it may get zero.
113 * A rough estimate for this step should be at least ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL ADC sar clock cycle.
114 */
115 uint32_t sar_clk = adc_ctrl_clk / ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT;
116 *read_delay_us = ((1000 * 1000) / sar_clk + 1) * ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL;
117 HAL_EARLY_LOGD("adc_hal", "clk_src_freq_hz: %"PRIu32", sar_clk: %"PRIu32", read_delay_us: %"PRIu32"", clk_src_freq_hz, sar_clk, read_delay_us);
118 #endif //ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL
119
120 #else
121 adc_oneshot_ll_start(unit);
122 #endif // SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
123 }
124
adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t * hal,int * out_raw)125 bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw)
126 {
127 bool valid = true;
128 uint32_t event = 0;
129 uint32_t read_delay_us = 0;
130 if (hal->unit == ADC_UNIT_1) {
131 event = ADC_LL_EVENT_ADC1_ONESHOT_DONE;
132 } else {
133 event = ADC_LL_EVENT_ADC2_ONESHOT_DONE;
134 }
135
136 adc_oneshot_ll_clear_event(event);
137 adc_oneshot_ll_disable_all_unit();
138 adc_oneshot_ll_enable(hal->unit);
139
140 adc_hal_onetime_start(hal->unit, hal->clk_src_freq_hz, &read_delay_us);
141 while (!adc_oneshot_ll_get_event(event)) {
142 ;
143 }
144 esp_rom_delay_us(read_delay_us);
145 *out_raw = adc_oneshot_ll_get_raw_result(hal->unit);
146 #if (SOC_ADC_PERIPH_NUM == 2)
147 if (hal->unit == ADC_UNIT_2) {
148 valid = adc_oneshot_ll_raw_check_valid(ADC_UNIT_2, *out_raw);
149 if (!valid) {
150 *out_raw = -1;
151 }
152 }
153 #endif
154
155 adc_oneshot_ll_disable_all_unit();
156 return valid;
157 }
158
159
160 /*---------------------------------------------------------------
161 Workarounds
162 ---------------------------------------------------------------*/
163 #if CONFIG_ADC_DISABLE_DAC_OUTPUT
s_disable_dac(adc_oneshot_hal_ctx_t * hal,adc_channel_t channel)164 static void s_disable_dac(adc_oneshot_hal_ctx_t *hal, adc_channel_t channel)
165 {
166 /**
167 * Workaround: Disable the synchronization operation function of ADC1 and DAC.
168 * If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage.
169 */
170 if (hal->unit == ADC_UNIT_1) {
171 dac_ll_rtc_sync_by_adc(false);
172 }
173
174 #if CONFIG_IDF_TARGET_ESP32
175 if (hal->unit == ADC_UNIT_2) {
176 if (channel == ADC_CHANNEL_8) {
177 dac_ll_power_down(DAC_CHAN_0); // the same as DAC channel 0
178 }
179 if (channel == ADC_CHANNEL_9) {
180 dac_ll_power_down(DAC_CHAN_1);
181 }
182 }
183 #elif CONFIG_IDF_TARGET_ESP32S2
184 if (hal->unit == ADC_UNIT_2) {
185 if (channel == ADC_CHANNEL_6) {
186 dac_ll_power_down(DAC_CHAN_0); // the same as DAC channel 0
187 }
188 if (channel == ADC_CHANNEL_7) {
189 dac_ll_power_down(DAC_CHAN_1);
190 }
191 }
192 #else
193 //Nothing needed (DAC is only supported on ESP32 and ESP32S2), add this if future chips needs
194 #endif
195 }
196 #endif
197
