1 /*
2 * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <sys/param.h>
8 #include "sdkconfig.h"
9 #include "soc/soc_caps.h"
10 #include "hal/adc_hal_common.h"
11 #include "hal/adc_ll.h"
12 #include "hal/assert.h"
13
14 /*---------------------------------------------------------------
15 Controller Setting
16 ---------------------------------------------------------------*/
get_controller(adc_unit_t unit,adc_hal_work_mode_t work_mode)17 static adc_ll_controller_t get_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
18 {
19 if (unit == ADC_UNIT_1) {
20 switch (work_mode) {
21 #if SOC_ULP_HAS_ADC
22 case ADC_HAL_ULP_FSM_MODE:
23 return ADC_LL_CTRL_ULP;
24 #endif
25 case ADC_HAL_SINGLE_READ_MODE:
26 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
27 return ADC_LL_CTRL_DIG;
28 #elif SOC_ADC_RTC_CTRL_SUPPORTED
29 return ADC_LL_CTRL_RTC;
30 #endif
31 case ADC_HAL_CONTINUOUS_READ_MODE:
32 return ADC_LL_CTRL_DIG;
33 default:
34 abort();
35 return ADC_LL_CTRL_DIG; //avoid -Wreturn-type
36 }
37 } else {
38 switch (work_mode) {
39 #if SOC_ULP_HAS_ADC
40 case ADC_HAL_ULP_FSM_MODE:
41 return ADC_LL_CTRL_ULP;
42 #endif
43 #if !SOC_ADC_ARBITER_SUPPORTED //No ADC2 arbiter on ESP32
44 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
45 default:
46 return ADC_LL_CTRL_DIG;
47 #else
48 case ADC_HAL_SINGLE_READ_MODE:
49 return ADC_LL_CTRL_RTC;
50 case ADC_HAL_CONTINUOUS_READ_MODE:
51 return ADC_LL_CTRL_DIG;
52 case ADC_HAL_PWDET_MODE:
53 return ADC_LL_CTRL_PWDET;
54 default:
55 abort();
56 #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
57 #else
58 default:
59 return ADC_LL_CTRL_ARB;
60 #endif
61 }
62 }
63 }
64
adc_hal_set_controller(adc_unit_t unit,adc_hal_work_mode_t work_mode)65 void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
66 {
67 adc_ll_controller_t ctrlr = get_controller(unit, work_mode);
68 adc_ll_set_controller(unit, ctrlr);
69 }
70
71
72 /*---------------------------------------------------------------
73 Arbiter
74 ---------------------------------------------------------------*/
75 #if SOC_ADC_ARBITER_SUPPORTED
adc_hal_arbiter_config(adc_arbiter_t * config)76 void adc_hal_arbiter_config(adc_arbiter_t *config)
77 {
78 adc_ll_set_arbiter_work_mode(config->mode);
79 adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
80 }
81 #endif // #if SOC_ADC_ARBITER_SUPPORTED
82
83
84 /*---------------------------------------------------------------
85 ADC calibration setting
86 ---------------------------------------------------------------*/
87 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
88 //For chips without RTC controller, Digital controller is used to trigger an ADC single read.
89 #include "esp_rom_sys.h"
90
adc_hal_calibration_init(adc_unit_t adc_n)91 void adc_hal_calibration_init(adc_unit_t adc_n)
92 {
93 adc_ll_calibration_init(adc_n);
94 }
95
96 static uint32_t s_previous_init_code[SOC_ADC_PERIPH_NUM] = {
97 [0 ... (SOC_ADC_PERIPH_NUM - 1)] = -1,
98 };
99
adc_hal_set_calibration_param(adc_unit_t adc_n,uint32_t param)100 void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param)
101 {
102 if (param != s_previous_init_code[adc_n]) {
103 adc_ll_set_calibration_param(adc_n, param);
104 s_previous_init_code[adc_n] = param;
105 }
106 }
107
108 #if SOC_ADC_SELF_HW_CALI_SUPPORTED
cal_setup(adc_unit_t adc_n,adc_atten_t atten)109 static void cal_setup(adc_unit_t adc_n, adc_atten_t atten)
110 {
111 adc_hal_set_controller(adc_n, ADC_HAL_SINGLE_READ_MODE);
112 adc_oneshot_ll_disable_all_unit();
113 // Enableinternal connect GND (for calibration).
114 adc_oneshot_ll_disable_channel(adc_n);
115 /**
116 * Note:
117 * When controlled by RTC controller, when all channels are disabled, HW auto selects channel0 atten param.
118 * When controlled by DIG controller, unit and channel are not related to attenuation
119 */
120 adc_oneshot_ll_set_atten(adc_n, 0, atten);
121 adc_oneshot_ll_enable(adc_n);
122 }
123
read_cal_channel(adc_unit_t adc_n)124 static uint32_t read_cal_channel(adc_unit_t adc_n)
125 {
126 uint32_t event = (adc_n == ADC_UNIT_1) ? ADC_LL_EVENT_ADC1_ONESHOT_DONE : ADC_LL_EVENT_ADC2_ONESHOT_DONE;
127 adc_oneshot_ll_clear_event(event);
128
129 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
130 adc_oneshot_ll_start(false);
131 esp_rom_delay_us(5);
132 adc_oneshot_ll_start(true);
133 #else
134 adc_oneshot_ll_start(adc_n);
135 #endif
136
137 while(!adc_oneshot_ll_get_event(event));
138
139 uint32_t read_val = -1;
140 read_val = adc_oneshot_ll_get_raw_result(adc_n);
141 if (adc_oneshot_ll_raw_check_valid(adc_n, read_val) == false) {
142 return -1;
143 }
144 return read_val;
145 }
146
147 #define ADC_HAL_CAL_TIMES (10)
148 #define ADC_HAL_CAL_OFFSET_RANGE (4096)
149
adc_hal_self_calibration(adc_unit_t adc_n,adc_atten_t atten,bool internal_gnd)150 uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool internal_gnd)
151 {
152 #if SOC_ADC_ARBITER_SUPPORTED
153 if (adc_n == ADC_UNIT_2) {
154 adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
155 adc_hal_arbiter_config(&config);
156 }
157 #endif // #if SOC_ADC_ARBITER_SUPPORTED
158
159 cal_setup(adc_n, atten);
160
161 adc_ll_calibration_prepare(adc_n, internal_gnd);
162
163 uint32_t code_list[ADC_HAL_CAL_TIMES] = {0};
164 uint32_t code_sum = 0;
165 uint32_t code_h = 0;
166 uint32_t code_l = 0;
167 uint32_t chk_code = 0;
168
169 for (uint8_t rpt = 0 ; rpt < ADC_HAL_CAL_TIMES ; rpt ++) {
170 code_h = ADC_HAL_CAL_OFFSET_RANGE;
171 code_l = 0;
172 chk_code = (code_h + code_l) / 2;
173 adc_ll_set_calibration_param(adc_n, chk_code);
174 uint32_t self_cal = read_cal_channel(adc_n);
175 while (code_h - code_l > 1) {
176 if (self_cal == 0) {
177 code_h = chk_code;
178 } else {
179 code_l = chk_code;
180 }
181 chk_code = (code_h + code_l) / 2;
182 adc_ll_set_calibration_param(adc_n, chk_code);
183 self_cal = read_cal_channel(adc_n);
184 if ((code_h - code_l == 1)) {
185 chk_code += 1;
186 adc_ll_set_calibration_param(adc_n, chk_code);
187 self_cal = read_cal_channel(adc_n);
188 }
189 }
190 code_list[rpt] = chk_code;
191 code_sum += chk_code;
192 }
193
194 code_l = code_list[0];
195 code_h = code_list[0];
196 for (uint8_t i = 0 ; i < ADC_HAL_CAL_TIMES ; i++) {
197 code_l = MIN(code_l, code_list[i]);
198 code_h = MAX(code_h, code_list[i]);
199 }
200
201 chk_code = code_h + code_l;
202 uint32_t ret = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4)
203 ? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
204 : (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
205
206 adc_ll_calibration_finish(adc_n);
207 return ret;
208 }
209 #endif //#if SOC_ADC_SELF_HW_CALI_SUPPORTED
210 #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
211
