1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <sys/cdefs.h>
9 #include <sys/param.h>
10 #include "sdkconfig.h"
11 #include "esp_attr.h"
12 #include "esp_log.h"
13 #include "esp_cpu.h"
14 #include "esp_clk_internal.h"
15 #include "esp_rom_uart.h"
16 #include "esp_rom_sys.h"
17 #include "soc/system_reg.h"
18 #include "soc/soc.h"
19 #include "soc/rtc.h"
20 #include "soc/rtc_periph.h"
21 #include "soc/i2s_reg.h"
22 #include "hal/wdt_hal.h"
23 #include "esp_private/periph_ctrl.h"
24 #include "esp_private/esp_clk.h"
25 // #include "bootloader_clock.h"
26 #include "soc/syscon_reg.h"
27
28 static const char *TAG = "clk";
29
30 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
31 * Larger values increase startup delay. Smaller values may cause false positive
32 * detection (i.e. oscillator runs for a few cycles and then stops).
33 */
34 #define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
35
36 #define RTC_XTAL_CAL_RETRY 1
37
38 /* Indicates that this 32k oscillator gets input from external oscillator, rather
39 * than a crystal.
40 */
41 #define EXT_OSC_FLAG BIT(3)
42
43 /* This is almost the same as soc_rtc_slow_clk_src_t, except that we define
44 * an extra enum member for the external 32k oscillator.
45 * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values.
46 */
47 typedef enum {
48 SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator
49 SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL
50 SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256
51 SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
52 } slow_clk_sel_t;
53
54 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
55 static __attribute__((unused)) void recalib_bbpll(void);
56
esp_rtc_init(void)57 void esp_rtc_init(void)
58 {
59 #if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
60 // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
61 // Do calibration again here so that we can use better clock for the timing tuning.
62 recalib_bbpll();
63 #endif
64
65 rtc_config_t cfg = RTC_CONFIG_DEFAULT();
66 soc_reset_reason_t rst_reas;
67 rst_reas = esp_rom_get_reset_reason(0);
68 //When power on, we need to set `cali_ocode` to 1, to do a OCode calibration, which will calibrate the rtc reference voltage to a tested value
69 if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
70 cfg.cali_ocode = 1;
71 }
72 rtc_init(cfg);
73 }
74
esp_clk_init(void)75 __attribute__((weak)) void esp_clk_init(void)
76 {
77 assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
78
79 bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
80 rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
81 rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
82
83 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
84 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
85 // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
86 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
87 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
88 // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
89 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
90 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
91 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
92 wdt_hal_feed(&rtc_wdt_ctx);
93 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
94 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
95 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
96 #endif
97
98 #if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
99 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
100 #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
101 select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
102 #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
103 select_rtc_slow_clk(SLOW_CLK_8MD256);
104 #else
105 select_rtc_slow_clk(SLOW_CLK_RTC);
106 #endif
107
108 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
109 // After changing a frequency WDT timeout needs to be set for new frequency.
110 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000ULL);
111 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
112 wdt_hal_feed(&rtc_wdt_ctx);
113 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
114 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
115 #endif
116
117 rtc_cpu_freq_config_t old_config, new_config;
118 rtc_clk_cpu_freq_get_config(&old_config);
119 const uint32_t old_freq_mhz = old_config.freq_mhz;
120 const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
121
122 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
123 assert(res);
124
125 // Wait for UART TX to finish, otherwise some UART output will be lost
126 // when switching APB frequency
127 if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
128 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
129 }
130
131 if (res) {
132 rtc_clk_cpu_freq_set_config(&new_config);
133 }
134
135 // Re calculate the ccount to make time calculation correct.
136 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
137 }
138
select_rtc_slow_clk(slow_clk_sel_t slow_clk)139 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
140 {
141 soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
142 uint32_t cal_val = 0;
143 /* number of times to repeat 32k XTAL calibration
144 * before giving up and switching to the internal RC
145 */
146 int retry_32k_xtal = RTC_XTAL_CAL_RETRY;
147
148 do {
149 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
150 /* 32k XTAL oscillator needs to be enabled and running before it can
151 * be used. Hardware doesn't have a direct way of checking if the
152 * oscillator is running. Here we use rtc_clk_cal function to count
153 * the number of main XTAL cycles in the given number of 32k XTAL
154 * oscillator cycles. If the 32k XTAL has not started up, calibration
155 * will time out, returning 0.
156 */
157 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
158 if (slow_clk == SLOW_CLK_32K_XTAL) {
159 rtc_clk_32k_enable(true);
160 } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
161 rtc_clk_32k_enable_external();
162 }
163 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
164 if (SLOW_CLK_CAL_CYCLES > 0) {
165 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
166 if (cal_val == 0) {
167 if (retry_32k_xtal-- > 0) {
168 continue;
169 }
170 ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
171 rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
172 }
173 }
174 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
175 rtc_clk_8m_enable(true, true);
176 }
177 rtc_clk_slow_src_set(rtc_slow_clk_src);
178
179 if (SLOW_CLK_CAL_CYCLES > 0) {
180 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
181 * Improve calibration routine to wait until the frequency is stable.
182 */
183 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
184 } else {
185 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
186 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
187 }
188 } while (cal_val == 0);
189 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
190 esp_clk_slowclk_cal_set(cal_val);
191 }
192
rtc_clk_select_rtc_slow_clk(void)193 void rtc_clk_select_rtc_slow_clk(void)
194 {
195 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
196 }
197
198 /* This function is not exposed as an API at this point.
199 * All peripheral clocks are default enabled after chip is powered on.
200 * This function disables some peripheral clocks when cpu starts.
201 * These peripheral clocks are enabled when the peripherals are initialized
202 * and disabled when they are de-initialized.
203 */
esp_perip_clk_init(void)204 __attribute__((weak)) void esp_perip_clk_init(void)
205 {
206 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
207 uint32_t common_perip_clk1 = 0;
208
209 #if CONFIG_FREERTOS_UNICORE
210 soc_reset_reason_t rst_reas[1];
211 #else
212 soc_reset_reason_t rst_reas[2];
213 #endif
214
215 rst_reas[0] = esp_rom_get_reset_reason(0);
216 #if !CONFIG_FREERTOS_UNICORE
217 rst_reas[1] = esp_rom_get_reset_reason(1);
218 #endif
219
220 /* For reason that only reset CPU, do not disable the clocks
221 * that have been enabled before reset.
222 */
223 if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW ||
224 rst_reas[0] == RESET_REASON_CPU0_RTC_WDT || rst_reas[0] == RESET_REASON_CPU0_MWDT1)
225 #if !CONFIG_FREERTOS_UNICORE
226 || (rst_reas[1] == RESET_REASON_CPU1_MWDT0 || rst_reas[1] == RESET_REASON_CPU1_SW ||
227 rst_reas[1] == RESET_REASON_CPU1_RTC_WDT || rst_reas[1] == RESET_REASON_CPU1_MWDT1)
228 #endif
229 ) {
230 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
231 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
232 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
233 } else {
234 common_perip_clk = SYSTEM_WDG_CLK_EN |
235 SYSTEM_I2S0_CLK_EN |
236 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
237 SYSTEM_UART_CLK_EN |
238 #endif
239 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
240 SYSTEM_UART1_CLK_EN |
241 #endif
242 #if CONFIG_ESP_CONSOLE_UART_NUM != 2
243 SYSTEM_UART2_CLK_EN |
244 #endif
245 SYSTEM_USB_CLK_EN |
246 SYSTEM_SPI2_CLK_EN |
247 SYSTEM_I2C_EXT0_CLK_EN |
248 SYSTEM_UHCI0_CLK_EN |
249 SYSTEM_RMT_CLK_EN |
250 SYSTEM_PCNT_CLK_EN |
251 SYSTEM_LEDC_CLK_EN |
252 SYSTEM_TIMERGROUP1_CLK_EN |
253 SYSTEM_SPI3_CLK_EN |
254 SYSTEM_SPI4_CLK_EN |
255 SYSTEM_PWM0_CLK_EN |
256 SYSTEM_TWAI_CLK_EN |
257 SYSTEM_PWM1_CLK_EN |
258 SYSTEM_I2S1_CLK_EN |
259 SYSTEM_SPI2_DMA_CLK_EN |
260 SYSTEM_SPI3_DMA_CLK_EN |
261 SYSTEM_PWM2_CLK_EN |
262 SYSTEM_PWM3_CLK_EN;
263 common_perip_clk1 = 0;
264 hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
265 SYSTEM_CRYPTO_SHA_CLK_EN |
266 SYSTEM_CRYPTO_RSA_CLK_EN;
267 wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
268 SYSTEM_WIFI_CLK_BT_EN_M |
269 SYSTEM_WIFI_CLK_I2C_CLK_EN |
270 SYSTEM_WIFI_CLK_UNUSED_BIT12 |
271 SYSTEM_WIFI_CLK_SDIO_HOST_EN;
272 }
273
274 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
275 common_perip_clk |= SYSTEM_I2S0_CLK_EN |
276 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
277 SYSTEM_UART_CLK_EN |
278 #endif
279 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
280 SYSTEM_UART1_CLK_EN |
281 #endif
282 #if CONFIG_ESP_CONSOLE_UART_NUM != 2
283 SYSTEM_UART2_CLK_EN |
284 #endif
285 SYSTEM_USB_CLK_EN |
286 SYSTEM_SPI2_CLK_EN |
287 SYSTEM_I2C_EXT0_CLK_EN |
288 SYSTEM_UHCI0_CLK_EN |
289 SYSTEM_RMT_CLK_EN |
290 SYSTEM_UHCI1_CLK_EN |
291 SYSTEM_SPI3_CLK_EN |
292 SYSTEM_SPI4_CLK_EN |
293 SYSTEM_I2C_EXT1_CLK_EN |
294 SYSTEM_I2S1_CLK_EN |
295 SYSTEM_SPI2_DMA_CLK_EN |
296 SYSTEM_SPI3_DMA_CLK_EN;
297 common_perip_clk1 = 0;
298
299 /* Disable some peripheral clocks. */
300 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
301 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
302
303 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
304 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
305
306 /* Disable hardware crypto clocks. */
307 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
308 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
309
310 /* Force clear backup dma reset signal. This is a fix to the backup dma
311 * implementation in the ROM, the reset signal was not cleared when the
312 * backup dma was started, which caused the backup dma operation to fail. */
313 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_PERI_BACKUP_RST);
314
315 /* Disable WiFi/BT/SDIO clocks. */
316 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
317 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
318
319 /* Set WiFi light sleep clock source to RTC slow clock */
320 REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
321 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
322 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
323
324 /* Enable RNG clock. */
325 periph_module_enable(PERIPH_RNG_MODULE);
326
327 /* Enable TimerGroup 0 clock to ensure its reference counter will never
328 * be decremented to 0 during normal operation and preventing it from
329 * being disabled.
330 * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
331 * registers (Flashboot protection included) will be reenabled, and some
332 * seconds later, will trigger an unintended reset.
333 */
334 periph_module_enable(PERIPH_TIMG0_MODULE);
335 }
336
337 // Workaround for bootloader not calibrated well issue.
338 // Placed in IRAM because disabling BBPLL may influence the cache
recalib_bbpll(void)339 static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
340 {
341 rtc_cpu_freq_config_t old_config;
342 rtc_clk_cpu_freq_get_config(&old_config);
343
344 // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
345 // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
346 // Turn off the BBPLL and do calibration again to fix the issue.
347 // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
348 // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
349 if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
350 rtc_clk_cpu_freq_set_xtal();
351 rtc_clk_cpu_freq_set_config(&old_config);
352 }
353 }
354
